A B C D E

MODEL NAME : VAZ90

PCB NO : LA-A161P
BOM P/N :
revision: A00
1 1

Compal Confidential
2
ZZZ
MB_PCB

Schematic Document 2

Jarama (Haswell Y-series)

@ : Nopop Component
CONN@ : Connector Component
vPRO@ : SPI ROM (8M+4M) Component
nvPRO@ : SPI ROM (8M) Component
CS@ : Connected Standby Component
3 Non-CS@ : Non-Connected Standby Component 3

2013-08-14
Rev: A00

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P01-Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
X02
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 1 of 49
A B C D E
 A B C D E

http://eloy-motherboards.blogspot.com

Channel A
Memory Bus (DDR3L-RS) DDR3L-RS 4Gb (x16) *4
eDP 1.3* 4lan Dual Channel P.12, 13
eDP Panel
P.19
DDR3L-RS 1600 MHz Channel B
1 1
DDR3L-RS 4Gb (x16) * 4
USB2.0 P.14, 15
Touch Screen
P.17

SATA3.0 Mini Card (Full)

# mSATA P.26
Intel
HDMI Conn HDMI 1.4a Haswell Y-Series SPI ROM
LEVEL SHIFT SPI
P.18 P.18 vPRO: (8M+4M)
BGA 1168 Balls
non vPRO (8M) P.07
7.5W SDP
USB 3.0 Conn. USB3.0/USB2.0
( USB Charger Port ) P.23
PCIE *1 Card Reader 3 in 1
USB 3.0 Conn. USB3.0/USB2.0 RTS5249 Socket P.23
P.23
( USB Charger Port ) P.23
2 2

USB2.0
USB2.0
Digital Camera P.17 DP 4 lan NGFF Slot A-DP
PCIE *2 WiGig/ Tri-Band
ALS+CLS TCS3472 TO EC 802.11abgn/ac/ad, BT3+LE
P.25
UART
level shift NGFF Slot A-SD
SDIO
P.24 I2C WLAN
e-Compass + I2C Sensor HUB USB2.0 BT
USB2.0
Accelerometer STM32F103RC PCIE 802.11abgn/ac, BT4.0+LEP.25
DE303DLHCTR
PCM
Gyro Sensor NFC Module SMLink level shift
Conn P.26
TX3GD20TR
HDA Audio DSP HDA Audio Codec Global headset
3 I2C ALC3661 P.21
3

Daughter Board ALC5505 P.20 P.21

Touch Pad PS2
P.19 TO EC Page 5, 6, 7, 8, 9, 10, 11

Audio AMP Int. Speaker

TPM LPC Bus APA2605 P.22 P.22
AT97SC3204 P.24
1 st Digital MIC P.19
Sensor HUB
ENE KB9012BF
Digital MIC Switch AUDIO Codec GPIO
P.22
P.33
2nd Array MIC P.19 PCH GPIO
FAN conn.
P.32
KSI/KSO
I2C
RTC PWM
P.31 Touch Controller Panel
P.31
I2C SMBus
DC/DC Interface CKT. Win8 KEY
4 P.30 4
P.19
Keyboard BL Resistance Keyboard Capacitance Keyboard
Power Circuit DC/DC P.31 P.31

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/02/23 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P02-Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 2 of 49
A B C D E
 A B C D E

Compal Confidential
Project Code : VAZ90
File Name :

1 1

2 2

3 3

4 4

LA-A161P
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P03-DaughterB block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, August 14, 2013 Sheet 3 of 49
A B C D E
 A

Board ID Table for AD channel

Vcc 3.3V +/- 5% USB PORT# DESTINATION
BOARD ID Table
Ra 100K +/- 1%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision 0 External USB3
0 0 0 Non- VPRO 0.1 (SSI)
1 12K +/- 1% 1 VPRO 0.2 (PT) 1 External USB3
2 15K +/- 1% 2 VPRO 0.3 (ST)
3 20K +/- 1% 3 VPRO 1.0 (XB) 2 NGFF CARD WLAN
4 27K +/- 1% 4
5 33K +/- 1% 5 3 Touch Panel
6 43K +/- 1% 6 PCH
7 56K +/- 1% 7 4 Camera
8 75K +/- 1% 8 USB
5 Sensors HUB
9 100K +/- 1% 9 Port
10 130K +/- 1% 10 VPRO 0.1 (SSI)
11 160K +/- 1% 11 Non- VPRO 0.2 (PT) Mapping 6 NGFF(WiGig)
12 200K +/- 1% 12 Non- VPRO 0.3 (ST)
13 240K +/- 1% 13 Non- VPRO 1.0 (XB) 7
14 270K +/- 1% 14
15 330K +/- 1% 15
16 430K +/- 1% 16
17 560K +/- 1% 17
18 750K +/- 1% 18
19 NC 19

SMBUS Control Table

SOURCE NGFF BATT Charger NFC XDP ALS Panel T-COM Keyboard

EC_SMB_CK1
EC_SMB_DA1
KB9012
V V
EC_SMB_CK2
EC_SMB_DA2
KB9012
V V DDI PORT# DESTINATION
PCH
EC_SMB_CK4
EC_SMB_DA4
KB9012
V DDI 1 NGFF(WiGig)
Link
1
PCH_SML0CLK
PCH_SML0DATA
PCH
V Port 2 HDMI
1

PCH_SML1CLK PCH Mapping

PCH_SML1DATA

PCH_SMBCLK
PCH_SMBDATA
PCH
V
CL_CLK
CL_DATA
PCH
V

DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION SATA DESTINATION PCI EXPRESS DESTINATION

CLKOUT_PCIE0 WiGig CLKOUT_LPC_0 TPM , EC LPC SATA0 m-SATA Lane 1 NGFF(WiGig)

CLKOUT_PCIE1 Card Reader CLKOUT_LPC_1 LPC Debug SATA1 Lane 2 CardReader

CLKOUT_PCIE2 NGFF CARD WLAN SATA2 Lane 3 NGFF(WLAN)

CLK CLKOUT_PCIE3 WiGig SATA3 Lane 4 NGFF(WiGig)

CLKOUT_PCIE4 Lane 5 Symbol Note :

CLKOUT_PCIE5 Lane 6 : means Digital Ground

: means Analog Ground

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P04-Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 4 of 49
A
 5 4 3 2 1

UCPU1A HSW_ULT_DDR3L

C54 C45
25 PCH_DP_N0 C55 DDI1_TXN0 EDP_TXN0 B46 eDP_TXN_P0 19
25 PCH_DP_P0 B58 DDI1_TXP0 EDP_TXP0 A47 eDP_TXP_P0 19
25 PCH_DP_N1 C58 DDI1_TXN1 EDP_TXN1 B47 eDP_TXN_P1 19
25 PCH_DP_P1 B55 DDI1_TXP1 EDP_TXP1 eDP_TXP_P1 19
NGFF(WiGig) 25 PCH_DP_N2 A55 DDI1_TXN2 C47
25 PCH_DP_P2 A57 DDI1_TXP2 EDP_TXN2 C46 eDP_TXN_P2 19
25 PCH_DP_N3 B57 DDI1_TXN3 EDP_TXP2 A49 eDP_TXP_P2 19
D 25 PCH_DP_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49 eDP_TXN_P3 19 D
C51 EDP_TXP3 eDP_TXP_P3 19
18 PCH_DDI2_N0 C50 DDI2_TXN0 A45 +VCCIOA_OUT
18 PCH_DDI2_P0 C53 DDI2_TXP0 EDP_AUXN B45 eDP_AUXN 19
18 PCH_DDI2_N1 DDI2_TXN1 EDP_AUXP eDP_AUXP 19
B54
18 PCH_DDI2_P1 C49 DDI2_TXP1 D20 +EDP_COM RC36 1 2 24.9_0402_1%
19 PCH_INV_PWM @ RC147 1 2 0_0402_5%~D EDP_BKLCTL HDMI 18 PCH_DDI2_N2 B50 DDI2_TXN2 EDP_RCOMP A43 EDP_DISP @ RC158 2 1 0_0402_5%~D
18 PCH_DDI2_P2 A53 DDI2_TXP2 EDP_DISP_UTIL
RC146 2 1 0_0402_5%~D EDP_DISP 18 PCH_DDI2_N3 B53 DDI2_TXN3
@ 18 PCH_DDI2_P3 DDI2_TXP3 Width 20 mils, Spacing 25 mils,
Length < 100 mil

@ RH123 1 2 100K_0402_5%~D ENBKL 1 OF 19

@ RH158 1 2 100K_0402_5%~D PCH_ENVDD

RH300 1 2 1M_0402_5%~D PCH_DP_HPD

@ RH387 1 2 1M_0402_5%~D PCH_HDMI_HPD

HSW_ULT_DDR3L
UCPU1I

EDP_BKLCTL B8 B9 PCH_DP_CLK
+3VS ENBKL A9 EDP_BKLCTL DDPB_CTRLCLK C9 PCH_DP_DAT
19 ENBKL EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA +5VS
19,29,30 PCH_ENVDD PCH_ENVDD C6 D9 PCH_HDMI_CLK PCH_HDMI_CLK 18
EDP_VDDEN DDPC_CTRLCLK D11 PCH_HDMI_DAT
DDPC_CTRLDATA PCH_HDMI_DAT 18
RH281 1 2 2.2K_0402_5%~D PCH_DP_CLK
RH282 1 2 2.2K_0402_5%~D PCH_DP_DAT

2
G
RH388 1 2 2.2K_0402_5%~D PCH_HDMI_CLK MPCIE_RST# U6
23,25 MPCIE_RST# PIRQA/GPIO77
RH389 1 2 2.2K_0402_5%~D PCH_HDMI_DAT TPM_IRQ# P4 C5 PCH_DP_AUXN 25
PCI_PIRQC# N4 PIRQB/GPIO78 DDPB_AUXN B6 3 1
@ RH380 1 2 100K_0402_5%~D TP_INT# PCI_PIRQD# N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5

D
PIRQD/GPIO80 DDPB_AUXP PCH_DP_AUXP 25
@ T123 AD4 A6
PME PCIE DDPC_AUXP @ QC5
C RH455 1 2 10K_0402_5%~D PCI_PIRQC# 32 TP_INT# TP_INT# U7 DII-DMN65D8LW-7~D C
RH456 1 2 10K_0402_5%~D PCI_PIRQD# L1 GPIO55 @ RC148
19 TS_RST# GPIO52
25 NGFF_WAKE# NGFF_WAKE# L3 C8 PCH_DP_HPD PCH_DP_HPD 25 CPU_eDP_HPD# 1 2 eDP_HPD 19
RH463 1 2 10K_0402_5%~D TPM_IRQ# Sensor_RST# R5 GPIO54 DDPB_HPD A8 PCH_HDMI_HPD
24 Sensor_RST# GPIO51 DDPC_HPD PCH_HDMI_HPD 18

1
AUDIO_IRQ# L4 D6 CPU_eDP_HPD# 0_0402_5%~D
GPIO53 EDP_HPD @
@ RH396 1 2 10K_0402_5%~D AUDIO_IRQ# RC160 RC138
RH397 1 2 10K_0402_5%~D NGFF_WAKE# 100K_0402_5%~D 100K_0402_5%~D

2
RH452 1 2 10K_0402_5%~D Sensor_RST# 9 OF 19

RH381 1 2 100K_0402_5%~D MPCIE_RST#

+1.05VS_VCCST
HSW_ULT_DDR3L
UCPU1B
2

D61 PU/PD for JTAG signals

RC43 @ T2 H_CATERR# K61 PROC_DETECT MISC
62_0402_5% N62 CATERR J62 XDP_PRDY#
33 H_PECI PECI PRDY XDP_PRDY# 17 +1.05VS_VCCST
K62 XDP_PREQ#
XDP_PREQ# 17
1

PREQ E60 CPU_XDP_TCK

PROC_TCK E61 CPU_XDP_TCK 17
CPU_XDP_TMS
JTAG PROC_TMS CPU_XDP_TMS 17
H_PROCHOT# 1 2 H_PROCHOT#_R K63 E59 CPU_XDP_TRST#
33,35 H_PROCHOT# PROCHOT PROC_TRST F63 CPU_XDP_TRST# 17
RC41 56_0402_5% THERMAL CPU_XDP_TDI CPU_XDP_TMS 51_0402_5% 1 2 RC45 @
PROC_TDI CPU_XDP_TDI 17
F62 CPU_XDP_TDO
PROC_TDO CPU_XDP_TDO 17
CPU_XDP_TDI 51_0402_5% 1 2 RC46 @
H_CPUPWRGD_R C61
1 2 H_CPUPWRGD_R PROCPWRGD CPU_XDP_TDO 51_0402_5% 1 2 RC48
RC44 10K_0402_5%~D
PWR

BPM#0
J60
XDP_BPM0# 17
R1d
H60 Stuffed : Dual TCK
BPM#1 XDP_BPM1# 17
H61 @ T226
Width 15 mils, Spacing 25 mils, Length < 500 mil BPM#2 H62 @ T227
unstuffed : Singel TCK
200_0402_1%~D 2 1 RC55 SM_RCOMP0 AU60 BPM#3 K59 @ T228
Avoid stub in the PWRGD path SM_RCOMP0 DDR3L BPM#4
121_0402_1% 2 1 RC58 SM_RCOMP1 AV60 H63 @ T229
while placing resistors RC44 & RC53 100_0402_1%~D 2 1 RC60 SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 @ T230
B
H_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 @ T231
B
DDR3 Compensation Signals DDR_PG_CNTL AV61 SM_DRAMRST BPM#7 Stuffed : Single & Dual TCK
SM_PG_CNTL1 CPU_XDP_TCK 51_0402_5% 1 2 RC52
R2
2 OF 19 CPU_XDP_TRST# 51_0402_5% 1 2 RC54 @
closed MCP 1000 mils R9
XDP_PRDY# TP@ T263
XDP_PREQ# TP@ T264

+3VS +1.35V_DDR CPU_XDP_TCK TP@ T265

CPU_XDP_TMS TP@ T266
CPU_XDP_TRST# TP@ T267
CC240 1 2 0.1U_0402_10V7K~D CPU_XDP_TDI TP@ T268
1

CPU_XDP_TDO TP@ T269

UC1
RC159 5 1
220K_0402_5%~D VCC NC
2 DDR_PG_CNTL
2

4 A
42 SM_PG_CTRL Y 3
GND
1

74AUP1G07GW_TSSOP5
@
RC161
2M_0402_5%
2

+1.35V_DDR

A A
1

RC75
470_0402_5%~D
2

H_DRAMRST# @ RC162 1 2 0_0402_5%~D

DDR3_DRAMRST# 12,13,14,15

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P05-MCP(1/7) DDI,EDP,PM,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 5 of 49
5 4 3 2 1
 5 4 3 2 1

D D

HSW_ULT_DDR3L HSW_ULT_DDR3L
UCPU1C UCPU1D
12,13 DDR_A_D[0..63]
14,15 DDR_B_D[0..63]
DDR_A_D0 AH63 AU37
SA_DQ0 SA_CLK#0 M_CLK_A_DDR#0 12,13,16
DDR_A_D1 AH62 AV37 M_CLK_A_DDR0 12,13,16 DDR_B_D0 AY31 AM38 M_CLK_B_DDR#0 14,15,16
DDR_A_D2 AK63 SA_DQ1 SA_CLK0 AW36 DDR_B_D1 AW31 SB_DQ0 SB_CK#0 AN38
SA_DQ2 SA_CLK#1 SB_DQ1 SB_CK0 M_CLK_B_DDR0 14,15,16
DDR_A_D3 AK62 AY36 DDR_B_D2 AY29 AK38
DDR_A_D4 AH61 SA_DQ3 SA_CLK1 DDR_B_D3 AW29 SB_DQ2 SB_CK#1 AL38
DDR_A_D5 AH60 SA_DQ4 AU43 DDR_B_D4 AV31 SB_DQ3 SB_CK1
SA_DQ5 SA_CKE0 DDR_A_CKE0 12,13,16 SB_DQ4
DDR_A_D6 AK61 AW43 DDR_A_CKE1 12,13,16 DDR_B_D5 AU31 AY49 DDR_B_CKE0 14,15,16
DDR_A_D7 AK60 SA_DQ6 SA_CKE1 AY42 DDR_B_D6 AV29 SB_DQ5 SB_CKE0 AU50
SA_DQ7 SA_CKE2 SB_DQ6 SB_CKE1 DDR_B_CKE1 14,15,16
DDR_A_D8 AM63 AY43 DDR_B_D7 AU29 AW49
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D8 AY27 SB_DQ7 SB_CKE2 AV50
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_B_D9 AW27 SB_DQ8 SB_CKE3
SA_DQ10 SA_CS#0 DDR_A_CS0# 12,13,16 SB_DQ9
DDR_A_D11 AP62 AR32 DDR_A_CS1# 12,13,16 DDR_B_D10 AY25 AM32 DDR_B_CS0# 14,15,16
DDR_A_D12 AM61 SA_DQ11 SA_CS#1 DDR_B_D11 AW25 SB_DQ10 SB_CS#0 AK32
SA_DQ12 SB_DQ11 SB_CS#1 DDR_B_CS1# 14,15,16
DDR_A_D13 AM60 AP32 DDR_B_D12 AV27
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D13 AU27 SB_DQ12 AL32
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_B_D14 AV25 SB_DQ13 SB_ODT0
DDR_A_D16 AP58 SA_DQ15 SA_RAS AW34 DDR_A_RAS# 12,13,16 DDR_B_D15 AU25 SB_DQ14 AM35
DDR_A_D17 AR58 SA_DQ16 SA_WE AU34 DDR_A_WE# 12,13,16 DDR_B_D16 AM29 SB_DQ15 SB_RAS AK35 DDR_B_RAS# 14,15,16
DDR_A_D18 AM57 SA_DQ17 SA_CAS DDR_A_CAS# 12,13,16 DDR_B_D17 AK29 SB_DQ16 SB_WE AM33 DDR_B_WE# 14,15,16
DDR_A_D19 AK57 SA_DQ18 AU35 DDR_B_D18 AL28 SB_DQ17 SB_CAS DDR_B_CAS# 14,15,16
DDR_A_D20 AL58 SA_DQ19 SA_BA0 AV35 DDR_A_BS0 12,13,16 DDR_B_D19 AK28 SB_DQ18 AL35
DDR_A_D21 AK58 SA_DQ20 SA_BA1 AY41 DDR_A_BS1 12,13,16 DDR_B_D20 AR29 SB_DQ19 SB_BA0 AM36 DDR_B_BS0 14,15,16
DDR_A_D22 AR57 SA_DQ21 SA_BA2 DDR_A_BS2 12,13,16 DDR_B_D21 AN29 SB_DQ20 SB_BA1 AU49 DDR_B_BS1 14,15,16
SA_DQ22 DDR_A_MA[0..15] 12,13,16 SB_DQ21 SB_BA2 DDR_B_BS2 14,15,16
DDR_A_D23 AN57 AU36 DDR_A_MA0 DDR_B_D22 AR28
SA_DQ23 SA_MA0 SB_DQ22 DDR_B_MA[0..15] 14,15,16
C DDR_A_D24 AP55 AY37 DDR_A_MA1 DDR_B_D23 AP28 AP40 DDR_B_MA0 C
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D24 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D31 AN54 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDR_A_MA8 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D32 AY23 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDR_B_MA9
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D35 AW56 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D34 AY21 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D36 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D39 AU56 SA_DQ38 SA_MA15 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
SA_DQ39 DDR_A_DQS#[0..7] 12,13 SB_DQ38 SB_MA15
DDR_A_D40 AY54 AJ61 DDR_A_DQS#0 DDR_B_D39 AU21
SA_DQ40 SA_DQSN0 SB_DQ39 DDR_B_DQS#[0..7] 14,15
DDR_A_D41 AW54 AN62 DDR_A_DQS#1 DDR_B_D40 AY19 AW30 DDR_B_DQS#0
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D41 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_B_DQS#1
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D42 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
DDR_A_D44 AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#4 DDR_B_D43 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW22 DDR_B_DQS#4
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D48 AK40 SA_DQ47 SA_DQSN7 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
SA_DQ48 DDR_A_DQS[0..7] 12,13 SB_DQ47 SB_DQSN7
DDR_A_D49 AK42 AJ62 DDR_A_DQS0 DDR_B_D48 AR21 DDR_B_DQS[0..7] 14,15
DDR_A_D50 AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D49 AR22 SB_DQ48 AV30 DDR_B_DQS0
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_B_DQS1
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57 DDR_A_DQS4 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS5 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_B_DQS5
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D58 AM49 SA_DQ57 AP49 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA V_DDR_REF_CA 16 SB_DQ57
DDR_A_D59 AK49 AR51 V_DDR_REFA_R 16 DDR_B_D58 AK18
DDR_A_D60 AM48 SA_DQ59 SM_VREF_DQ0 AP51 DDR_B_D59 AL18 SB_DQ58
SA_DQ60 SM_VREF_DQ1 V_DDR_REFB_R 16 SB_DQ59
DDR_A_D61 AK48 DDR_B_D60 AK20
B
DDR_A_D62 AM51 SA_DQ61 DDR_B_D61 AM20 SB_DQ60 B
SA_DQ62 10 mil trace width SB_DQ61
DDR_A_D63 AK51 DDR_B_D62 AR18
SA_DQ63 DDR_B_D63 AP18 SB_DQ62
SB_DQ63

3 OF 19 4 OF 19

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P06-MCP(2/7) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 6 of 49
5 4 3 2 1
 5 4 3 2 1

UCPU1E HSW_ULT_DDR3L
CH2 2 1 15P_0402_50V8J~D PCH_RTCX1

PCH_RTCX1 AW5
RTCX1

1
PCH_RTCX2 AY5 2 1 HDA_SDOUT
RTCX2

1
RH2 +RTCVCC RH11 1 2 1M_0402_5%~D SM_INTRUDER# AU6 J5
SATA_PRX_DTX_N0 26 @RF@MC103
@RF@ MC103 10P_0402_50V8J~D
INTRUDER SATA_RN0/PERN6_L3

mSATA
YH1 10M_0402_5% PCH_INTVRMEN AV7 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DTX_P0 26
32.768KHZ_12.5PF_9H03200031 PCH_SRTCRST# AV6 RTC B15
SRTCRST SATA_TN0/PETN6_L3 SATA_PTX_DRX_N0 26
PCH_RTCRST# AU7 A15 SATA_PTX_DRX_P0 26 Reserve for RF please close to UH1

2
17 PCH_RTCRST# RTCRST SATA_TP0/PETP6_L3
J8
CH3 2 1 PCH_RTCX2 RP3 SATA_RN1/PERN6_L2 H8
15P_0402_50V8J~D 1 8 HDA_BIT_CLK SATA_RP1/PERP6_L2 A17
20 HDA_BITCLK_AUDIO SATA_TN1/PETN6_L2
far away hot spot 20 HDA_RST_AUDIO#
2 7 HDA_RST# B17
3 6 HDA_SYNC SATA_TP1/PETP6_L2 +3VS
20 HDA_SYNC_AUDIO
4 5 HDA_SDOUT HDA_BIT_CLK AW8 J6
D
20 HDA_SDOUT_AUDIO HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 D
HDA_SYNC AV11 H6 PCH_GPIO35 @ RH390 1 2 10K_0402_5%~D
33_8P4R_5% HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14 PCH_GPIO36 RH391 1 2 200K_0402_5%~D
AY10 HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1 C15 mSATA_DET# RH392 1 2 100K_0402_5%~D
20 HDA_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 closed MCP 2000 mils
AU12
HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5 EC_SMI# TP@ T270
+RTCVCC CMOS AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5 PCH_GPIO35 TP@ T271
1 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0
1

SP@ AV10 C17 PCH_GPIO36 TP@ T272

CH4 CLRP1 @EMI@ MC96 TP@ T273 PCH_JTAG_JTAGX AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 mSATA_DET# TP@ T274
1U_0402_6.3V6K~D SHORT PADS 2 1 HDA_BIT_CLK TP@ T275 PCH_JTAG_TDO I2S1_SCLK SATA_TP3/PETP6_L0
2

1 2 2 PCH_RTCRST# TP@ T276 PCH_JTAG_TMS

RH25 20K_0402_5%~D
1 2 PCH_SRTCRST#
22P_0402_50V8J~D TP@
TP@
T277
T278
PCH_JTAG_TCK
PCH_JTAG_TDI SATA0GP/GPIO34
SATA1GP/GPIO35
V1 EC_SMI#
U1 PCH_GPIO35
V6
EC_SMI# 33 HDA_SDO
RH23 20K_0402_5%~D 1 Reserve for EMI please close to UCPU1E closed MCP 1000 mils PCH_GPIO36 ME debug mode , this signal has a weak internal PD
SATA2GP/GPIO36
1

SP@ AC1 mSATA_DET# +V1.05S_ASATA3PLL

SATA3GP/GPIO37 mSATA_DET# 26
CH5 CLRP2 AU62 L=>security measures defined in the Flash
17 PCH_JTAG_TRST# AE62 PCH_TRST A12
1U_0402_6.3V6K~D SHORT PADS PCH_JTAG_TCK
2

2 17 PCH_JTAG_TCK AD61 PCH_TCK SATA_IREF L11 Descriptor will be in effect (default)

ME CMOS PCH_JTAG_TDI
17 PCH_JTAG_TDI AE61 PCH_TDI RSVD K10
PCH_JTAG_TDO
17 PCH_JTAG_TDO PCH_JTAG_TMS AD62 PCH_TDO RSVD C12 SATA_RCOMP RH43 1 2 3K_0402_1%~D
CLP1 & CLP2 place near DIMM JTAG
H=>Flash Descriptor Security will be overridden
17 PCH_JTAG_TMS AL11 PCH_TMS SATA_RCOMP U3 PCH_SATALED# 2 1
RSVD SATALED +3VS
AC4 RH35 10K_0402_5%~D
+5VALW PCH_JTAG_JTAGX AE63 RSVD +3V_PCH
17 PCH_JTAG_JTAGX AV2 JTAGX Width = 15 mil, Spacing = 12 mil
+RTCVCC RSVD
Close PCH within 500 mil

2
@ RH42 1 2 1K_0402_5%~D HDA_SDOUT

1 2 PCH_INTVRMEN R1341
RH31 330K_0402_5%~D 1M_0402_5%~D 5 OF 19 *Low = Disabled
High = Enabled
1 2

1
@RH34
@ RH34 330K_0402_5%~D 33 HDA_SDO

* HL：：Integrated
INTVRMEN From EC, for enable

2
Q351

G
Integrated VRM enable ME code programing
VRM disable
1 3 RH24 1 2 1K_0402_5%~D HDA_SDOUT
+3V_PCH HSW_ULT_DDR3L
UCPU1F XTAL24_IN
D

S
DII-DMN65D8LW-7~D
0312-45
XTAL24_OUT 1 2
C
PCH JTAG 25 CLK_PCIE0#
C43
C42 CLKOUT_PCIE_N0 XTAL24_IN
A25
B25
XTAL24_IN
XTAL24_OUT
RH117 1M_0402_5%~D C

+1.05V_M WiGig 25 CLK_PCIE0

RH91 1 2 10K_0402_5%~D PCH_GPIO18 U2 CLKOUT_PCIE_P0 XTAL24_OUT YH2
+3VS PCIECLKRQ0/GPIO18 K21 XCLK_BIASREF <100 MILS 24MHZ_12PF_7V24000020
B41 RSVD M21 1 3
Stuffed : Single & Dual TCK 23 CLK_PCIE_CD#
A41 CLKOUT_PCIE_N1 RSVD C26 XCLK_BIASREF 1 2 3K_0402_1%~D 2 4
RH113
R4 RH40 1 2 51_0402_5% PCH_JTAG_TDI CardReader
23 CLK_PCIE_CD
+3VS RH95 1 2 10K_0402_5%~D PCH_GPIO19 Y5 CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
DIFFCLK_BIASREF +V1.05S_AXCK_LCPLL
C35 TESTLOW1 1 1
23 CDCLK_REQ# TESTLOW_C35
RH445 1 2 51_0402_5% PCH_JTAG_TDO C41 CLOCK C34 TESTLOW2
R3d WLAN
25 CLK_PCIE2#
25 CLK_PCIE2
B42 CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
TESTLOW_C34
TESTLOW_AK8
AK8 TESTLOW3 CH24 CH23
RH39 1 2 51_0402_5% PCH_JTAG_TMS RH100 1 2 10K_0402_5%~D PCH_GPIO20 AD1 SIGNALS AL8 TESTLOW4
R5 +3VS PCIECLKRQ2/GPIO20 TESTLOW_AL8 RH428 1 2 22_0402_5%~D
CLK_PCI_TPM 24
2
15P_0402_50V8J~D
2
15P_0402_50V8J~D

@ RH375 1 2 1K_0402_5%~D PCH_JTAG_JTAGX B38 AN15 CLKOUT_LPC0 RH360 1 2 22_0402_5%~D

R8 WiGig
25
25
CLK_PCIE3#
CLK_PCIE3
C37 CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
CLKOUT_LPC_0
CLKOUT_LPC_1
AP15 CLKOUT_LPC1 RH386 1 2 22_0402_5%~D CLK_LPC_DEBUG
CLK_PCI_LPC 33
17
RH103 1 2 10K_0402_5%~D PCH_GPIO21 N1
+3VS PCIECLKRQ3/GPIO21
@ RH53 1 2 51_0402_5% PCH_JTAG_TCK B35
R6 A39
CLKOUT_PCIE_N4
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
A35
B39 LPC CLOCK CAN FEED ONLY 1 LOAD AT A TIME
RH107 1 2 10K_0402_5%~D PCH_GPIO22 U5 CLKOUT_PCIE_P4 @RH417
@ RH417
+3VS PCIECLKRQ4/GPIO22 1 2
B37
A37 CLKOUT_PCIE_N5 TESTLOW1 RH76 1 2 10K_0402_5%~D 0_0402_5%~D
@ RH410
@RH410 T2 CLKOUT_PCIE_P5 TESTLOW2 RH77 1 2 10K_0402_5%~D DII-DMN65D8LW-7~D
1 2 22 DMIC_SW_PCH PCIECLKRQ5/GPIO23 TESTLOW3 RH78 1 2 10K_0402_5%~D

D
TESTLOW4 RH79 1 2 10K_0402_5%~D 3 1 PCH_GPIO18
25 CLK_REQ0#
0_0402_5%~D 6 OF 19
DII-DMN65D8LW-7~D Q348
+3.3V_M

G
2
3 1
S

PCH_GPIO20
25 CLK_REQ2# +3VS_NGFF
RH54 1 2 1K_0402_5%~D PCH_SPI_IO2

1
Q346
RH56 1 2 1K_0402_5%~D PCH_SPI_IO3 R1200
G
2

+3VS_NGFF HSW_ULT_DDR3L
100K_0402_5%~D
UCPU1G
1

2
R1197 AU14 AN2 SMBALERT#
17,24,33 LPC_AD0 LAD0 SMBALERT/GPIO11 SMBALERT# 24
100K_0402_5%~D AW12 AP2 SMBCLK
17,24,33 LPC_AD1 LAD1 SMBCLK
vPRO:SPI ROM (8M+4M)
AY12 LPC AH1 SMBDATA
17,24,33 LPC_AD2 LAD2 SMBDATA
AW11 SMBUS AL2 CR_PWREN
17,24,33 LPC_AD3
2

AV12 LAD3 SML0ALERT/GPIO60 AN1 SML0CLK CR_PWREN 23

non vPRO:SPI ROM (8M)

B
17,24,33 LPC_FRAME# LFRAME SML0CLK SML0CLK 26 B
AK1 SML0DATA SML0DATA 26 Connect NFC @RH418
@ RH418
SML0DATA AU4 SML1ALERT# 1 2
SML1ALERT/PCHHOT/GPIO73 AU3 SML1ALERT# 24
SML1CLK
SML1CLK/GPIO75 AH3 SML1DATA
Closed to UCPU1 @EMI@ MC118
1 2 PCH_SPI_CLK PCH_SPI_CLK AA3 SML1DATA/GPIO74
0_0402_5%~D
DII-DMN65D8LW-7~D
SPI_CLK_ROM vPRO@ RH258 1 2 33_0402_5%~D PCH_SPI_CLK PCH_SPI_CS# Y7 SPI_CLK AF2
SPI_CS0 CL_CLK CL_CLK 25
Y4 AD2 3 1

D
PCH_SPI_CS1# PCH_GPIO21
12P_0402_50V8J~D SPI_CS1 CL_DATA CL_DATA 25 25 CLK_REQ3#
vPRO@ RP4 AC2 SPI C-LINK AF4
SPI_SO_ROM 1 8 PCH_SPI_SO PCH_SPI_SI AA2 SPI_CS2 CL_RST CL_RST# 25 Q350
SPI_IO2_ROM 2 7 PCH_SPI_IO2 PCH_SPI_SO AA4 SPI_MOSI

G
2
SPI_SI_ROM 3 6 PCH_SPI_SI PCH_SPI_IO2 Y6 SPI_MISO
SPI_IO2 +3VS_NGFF
SPI_IO3_ROM 4 5 PCH_SPI_IO3 PCH_SPI_IO3 AF1
SPI_IO3

1
RP4 RH258
33_8P4R_5% R1205
100K_0402_5%~D

SPI ROM ( 8MByte )

7 OF 19

2
+3VS +3VS

ROM is Quad SPI +3.3V_M

15_0804_8P4R_5%
SD300001P00
15_0402_5%~D
SD028150A80 +3V_PCH

U48 nvPRO@ nvPRO@

PCH_SPI_CS# 1 8
SPI_SO_ROM 2 /CS VCC 7 SPI_IO3_ROM
DO(IO1) /HOLD(IO3)

1
SPI_IO2_ROM 3 6 SPI_CLK_ROM +3VS
/WP(IO2) CLK 1
4 5 SPI_SI_ROM CH6 SML1CLK RH469 1 2 2.2K_0402_5%~D
GND DI(IO0) .1U_0402_16V7K~D RH98 RH99 SMBCLK RH470 1 2 2.2K_0402_5%~D
W25Q64FVSSIQ_SO8 10K_0402_5%~D 10K_0402_5%~D SMBDATA RH471 1 2 2.2K_0402_5%~D
2

2
2 QH3A SML1DATA RH472 1 2 2.2K_0402_5%~D

2
SML1CLK 6 1 SMBCLK 6 1
PCH_SMLCLK 19,28,32,33 PCH_SMBCLK 17
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
SPI_CLK32 vPRO@ RH256 1 2 33_0402_5%~D PCH_SPI_CLK QH4A
1 2 Connect EC, ALS SML0CLK RH70 1 2 499_0402_1%~D
5

vPRO@ RP5 @RH453

@ RH453 0_0402_5%~D 1 2 Connect XDP
5

SPI_DIN32 1 8 PCH_SPI_SO @ RH105 0_0402_5%~D QH3B SML0DATA RH72 1 2 499_0402_1%~D

SPI_PCH_DO2_32 2 7 PCH_SPI_IO2 SML1DATA 3 4
PCH_SMLDATA 19,28,32,33
SPI_DO32 3 6 PCH_SPI_SI SMBDATA 3 4
A DMN66D0LDW-7_SOT363-6~D PCH_SMBDATA 17 +3V_PCH A
SPI_PCH_DO3_32 4 5 PCH_SPI_IO3
QH4B
33_8P4R_5% 1 2 DMN66D0LDW-7_SOT363-6~D
@ RH454 0_0402_5%~D RH80 1 2 10K_0402_5%~D
9 USB_OC2#
SPI ROM ( 4MByte )
1 2 SMBALERT# RH81 1 2 10K_0402_5%~D
@ RH111 0_0402_5%~D EC_SMI# RH82 1 2 10K_0402_5%~D +3VS

ROM is Quad SPI

@EMI@ MC94 @EMI@ MR256 CR_PWREN RH83 1 2 10K_0402_5%~D
2 1 1 2 SPI_CLK_ROM
+3.3V_M
22P_0402_50V8J~D 33_0402_5%~D
U2 vPRO@ Reserve for EMI please close to U48
PCH_SPI_CS1# 1 8
SPI_DIN32 2 /CS
DO/IO1
VCC
/HOLD/IO3
7 SPI_PCH_DO3_32 Security Classification Compal Secret Data Compal Electronics, Inc.
SPI_PCH_DO2_32 3 6 SPI_CLK32 1 vPRO@ @EMI@ MC95 @EMI@ MR257 2011/06/02 2013/10/28 Title
4 /WP/IO2 CLK 5 SPI_DO32 CH7 2 1 1 2 SPI_CLK32
Issued Date Deciphered Date
GND DI/IO0 .1U_0402_16V7K~D THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P07-MCP(3/7) SATA,HDA,CLK,SPI
W25Q32FVSSIQ_SO8 22P_0402_50V8J~D 33_0402_5%~D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
2 A00
Reserve for EMI please close to U2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 7 of 49
5 4 3 2 1
 5 4 3 2 1

+3V_PCH +3V_PCH_DSW
+3VS
PBTN_OUT#_R @ R1312 1 2 3K_0402_5%~D WAKE# RH146 1 2 1K_0402_5%~D

PM_CLKRUN# RH248 2 1 8.2K_0402_5%~D

UCPU1H HSW_ULT_DDR3L +3V_PCH
Non Deep S3 (Pop RH429) CRB 10K
Deep S3 (Pop RH430) SYSTEM POWER MANAGEMENT PCH_SUSWARN#R RH154 1 2 1M_0402_5%~D
PCH_SUSWARN#R CS@ RH429 2 1 0_0402_5%~D
Deep S3 support, connect to EC Non-CS@ RH430 2 1 0_0402_5%~D SUSACK#_R AK2 AW7 DSWODVREN
33 SUSACK# SUSACK DSWVRMEN
17 PM_SYS_RESET# @ RH450 2 1 0_0402_5% SYS_RESET# AC3 AV5 PCH_DPWROK @
SYS_PWROK AG2 SYS_RESET DPWROK AJ5 WAKE# PCH_DPWROK RH401 1 2 100K_0402_5%~D
17,32 SYS_PWROK SYS_PWROK WAKE
PCH_PWROK AY7
32 PCH_PWROK PCH_PWROK
vPRO@ RH131 2 1 0_0402_5%~D APWROK_R AB5
29,33,41 APOWER_OK AG7 APWROK V5
PCH_PLTRST# PM_CLKRUN#
PLTRST CLKRUN/GPIO32 PM_CLKRUN# 24,33
PCH_PWROK nvPRO@ RH134 2 1 0_0402_5%~D AG4 SUS_STAT# SUS_STAT# 24
D SUS_STAT/GPIO61 AE6 SUSCLK @ RH132 2 1 0_0402_5% D
SUSCLK/GPIO62 AP5
SUSCLK_R
PM_SLP_S5#
25,33
17,33
PCH DPWROK Option for Deep S3
PCH_RSMRST# @ RH133 2 1 0_0402_5% PCH_RSMRST#_R AW6 SLP_S5/GPIO63
33 PCH_RSMRST# RSMRST
@ RH297 2 1 0_0402_5% PCH_SUSWARN#R AV4
33 PCH_SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
33 PBTN_OUT# @ RH293 2 1 0_0402_5% PBTN_OUT#_R AL7 AJ6 PM_SLP_S4# PM_SLP_S4# 17,33,42 Non-CS@ RH309 Deep S3 Support
AC_PRESENT @ RH137 2 1 0_0402_5% AC_PRESENT_R AJ8 PWRBTN SLP_S4 AT4 PM_SLP_S3# 0_0402_5%~D
33 AC_PRESENT ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# 17,29,30,33,40
DMIC_SW_DIS AN4 AL5 2 1
PM_SLP_A# 17,29,30,33 3VALW_PG 37
@ RH447 222 DMIC_SW_DIS
1 0_0402_5%~D AF3 BATLOW/GPIO72 SLP_A AP4 RH313 2 1 0_0402_5%~D PM_SLP_SUS# 29,30,33
17,33,41 PM_SLP_S0# SLP_WLAN# AM5 SLP_S0 SLP_SUS AJ7 Non-CS@
33 SLP_WLAN# SLP_WLAN/GPIO29 SLP_LAN
SYS_RESET# RH467 1 2 10K_0402_5%~D
Deep S3 Support PCH_DPWROK 1 2 PCH_RSMRST#_R
+3VS Non Deep S3 (De-pop RH313)
RH468 1 2 10K_0402_5%~D CS@ RH126
Non Deep S3
27,9 USB_OC0# +3V_PCH
@ RH438 2 1 0_0402_5%~D APWROK_R 8 OF 19 0_0402_5%~D
17,32 1.05VS_PG
+3V_PCH_DSW
@ RH439 2 1 0_0402_5%~D PBTN_OUT#_R
17,20,33 PBTN_SW# PBTN_OUT#_R 17
SLP_WLAN# @ RH402 1 2 10K_0402_5%~D
Deep S3 support, connect to DSW power rail @ RH310
1 2 PCH Strap PIN +RTCVCC 0_0402_5%~D
PCH_GPIO27 RH464 1 2 10K_0402_5%~D @ RH168 0_0402_5%~D SUSCLK 2 1 PCH_GPIO27 2 1
@RF@ MC102 10P_0402_50V8J~D
DMIC_SW_DIS RH466 1 2 10K_0402_5%~D +3VS DSWODVREN RH147 2 1 330K_0402_5%~D

AC_PRESENT RH12 1 2 1M_0402_5%~D DSWODVREN @ RH151 2 1 330K_0402_5%~D Reserve for RF please close to UH1 25,33 WAKE_PCH#
1 2 WAKE#

5
@ RH128

* ：：
PCH_GPIO27 @ RH186 2 1 1K_0402_5%~D 1 PCH_PLTRST# DSWODVREN - On Die DSW VR Enable 0_0402_5%

P
4 IN1
17,23,24,25,33 PLT_RST# O H Enable 0802-12
PCH_RSMRST# RH159 1 2 10K_0402_5%~D 2 L Disable
IN2

G
1

SYS_PWROK @ RH272 1 2 10K_0402_5%~D

3
UH5

2
PCH_PWROK RH394 1 2 100K_0402_5%~D RH171 SN74AHC1G08DCKR_SC70-5~D PCH_GPIO27 @ RH427 1 2 0_0402_5% EC_WAKE_SCI# 33
100K_0402_5%~D @
RH183
2

10K_0402_5%~D +3VS +1.05VS_VCCST

C
U682
0802-12 C

1
1 5 H_THERMTRIP# RC149 1 2 1K_0402_5%~D
NC VCC
PCH_GPIO15
TLS Confidentiality SSD_PWREN# 2 +3VS
IN A
Low - Intel ME Crypto Transport Layer Security (TLS)
* cipher suite with no confidentiality
closed MCP 2000 mils 3 4 KB_DET# RH302 1 2 100K_0402_5%~D
High - Intel ME Crypto Transport Layer Security (TLS) @EMI@ 2 1 PLT_RST# GND OUT Y SSD_PWREN 26
cipher suite with confidentiality MC104 10P_0402_50V8J~D SERIRQ RH29 1 2 10K_0402_5%~D
+3V_PCH TP@ T279
TP@T279 AUDIO_PWREN SN74AUP1G04DCKR_SOT23-5~D
KB_RST# RH196 1 2 10K_0402_5%~D
vPRO@ TP@T281
TP@ T281 PCH_GPIO17 @ RH431 2 1 0_0402_5%~D
RH270 2 1 1K_0402_5%~D PCH_GPIO15 TP@ T282
TP@T282 KB_DET#
Reserve for EMI please close to UH5 SSD_PWREN# RH423 1 2 100K_0402_5%~D DDR_CHA_EN RH440 1 2 100K_0402_5%~D
TP@T284
TP@ T284 KB_BL_DET
TP@ T285
TP@T285 SENSOR_INT# DDR_CHB_EN RH441 1 2 100K_0402_5%~D
+3V_PCH TP@ T286
TP@T286 MEM_CONFIG0
TP@ T287
TP@T287 MEM_CONFIG1
HSW_ULT_DDR3L
@ RH294 2 1 10K_0402_5%~D NFC_IRQ TP@ T288
TP@T288 UART_WAKE# UCPU1J DDR_CHA_EN @ RH442 1 2 SHORT PADS

RH383 2 1 100K_0402_5%~D UART_WAKE# DDR_CHB_EN @ RH443 1 2 SHORT PADS

RH295 2 1 10K_0402_5%~D CR_WAKE# PCH_OPIRCOMP RC156 1 2 49.9_0402_1%~D

AUDIO_PWREN P1 D60 H_THERMTRIP#_R 1 2 H_THERMTRIP#
RH298 2 1 10K_0402_5%~D SENSOR_INT# 20,29,30 AUDIO_PWREN KB_BL_DET AU2 BMBUSY/GPIO76 THRMTRIP V4 KB_RST# @ RC49 0_0402_5%
31 KB_BL_DET GPIO8 RCIN/GPIO82 KB_RST# 33
GPIO12 AM7 T4 SERIRQ SERIRQ 24,33

Boot BIOS Strap

2 1 10K_0402_5%~D EC_RUNTIME_SCI# PCH_GPIO15 AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 PCH_OPIRCOMP
RH299
GPIO15 MISC PCH_OPI_RCOMP GPIO86 have internal pull down
31 KB_DET# KB_DET# Y1 AF20
RH301 2 1 10K_0402_5%~D PCH_GPIO17 PCH_GPIO17 T3 GPIO16 RSVD AB21 Width = 15 mil, Spacing = 12 mil
+3VS GPIO17 RSVD
CR_WAKE# AD5 Close PCH within 500 mil PCH_GPIO86 Boot BIOS Location
23 CR_WAKE# GPIO24
Deep S3 support, PCH_GPIO27 AN5
+3V_PCH_DSW AD7 GPIO27
0 SPI
PCH_GPIO27 connect from EC PCH_WAKE# 26 NFC_RST#
26 NFC_IRQ NFC_IRQ AN3 GPIO28
GPIO26
*
RH296 2 1 10K_0402_5%~D GPIO12 R6
AG6 GSPI0_CS/GPIO83 L6 NGFF_PWREN 25,30
B +3VS 24 TPM_RST# GPIO56 GSPI0_CLK/GPIO84 +VS_LPSS_SDIO B
AP1 N6
25 BT_CS_NOTICE GPIO57 GSPI0_MISO/GPIO85 TP_EN 30
AL4 L8
24 SLATE_MODE GPIO58 GSPI0_MOSI/GPIO86
R1185 1 2 100K_0402_5%~D MPHY_PWREN MEM_CONFIG0 AT5 R7 BT_RADIO_DIS# 25 SDIO_D0 @ RH434 2 1 1K_0402_5%~D
AK4 GPIO59 GPIO GSPI1_CS/GPIO87 L5 @ RH448 2 1 0_0402_5% PM_SLP_S0#
24 SENSOR_DFU_EN# GPIO44 GSPI1_CLK/GPIO88
MEM_CONFIG2 AB6 N7
2 1 100K_0402_5%~D USB0_PWR_EN MEM_CONFIG1 U4 GPIO47 GSPI1_MISO/GPIO89 K2 SSD_PWREN# TS_EN 30
RH400
GPIO48 GSPI_MOSI/GPIO90 GPIO66 have internal pull down
Y3 J1 DDR_CHA_EN
24 SENSOR_HUB_I2C_WAKE TS_INT# P3 GPIO49 UART0_RXD/GPIO91 K3 DDR_CHB_EN
19 TS_INT# Y2 GPIO50 UART0_TXD/GPIO92 J2
30 MPHY_PWREN MPHY_PWREN Top-Block Swap Override mode
+3VS USB0_PWR_EN AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1
27 USB0_PWR_EN GPIO13 UART0_CTS/GPIO94
SENSOR_INT# AH4 K4 UART1_RXD
24 SENSOR_INT# GPIO14 UART1_RXD/GPIO0 UART1_RXD 25
2 1 1M_0402_5%~D NFC_DET# AM4 G2 UART1_TXD
RH465 30 EN_CAM
TPM_DET AG5 GPIO25
GPIO45
UART1_TXD/GPIO1
UART1_RST/GPIO2
J3 UART1_RTS# UART1_TXD 25
UART1_RTS# 25
*01 = Enable
= Disable
RH457 2 1 49.9K_0402_1%~D UART1_RXD AG3 J4 UART1_CTS#
24,30 SENSOR_EN GPIO46 UART1_CTS/GPIO3 UART1_CTS# 25
F2 I2C0_SDA
I2C0_SDA/GPIO4 I2C0_SDA 33
RH458 2 1 49.9K_0402_1%~D UART1_TXD UART_WAKE# AM3 F3 I2C0_SCK
25 UART_WAKE# GPIO9 I2C0_SCL/GPIO5 I2C0_SCK 33
EC_RUNTIME_SCI# AM2 G4
33 EC_RUNTIME_SCI# GPIO10 I2C1_SDA/GPIO6 I2C1_SDA 19
RH459 2 1 49.9K_0402_1%~D UART1_RTS# P2 F1
26 DEVSLP0 C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 I2C1_SCK 19
RH460 2 1 49.9K_0402_1%~D UART1_CTS# 24 SENSOR_STANDBY# L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 SDIO_CLK 25 DDR Memory Configuration Type Strap pin
25 WL_OFF# DEVSLP1/GPIO38 SDIO_CMD/GPIO65 SDIO_CMD 25
NFC_DET# N5 D3 SDIO_D0
26 NFC_DET# DEVSLP2/GPIO39 SDIO_D0/GPIO66 SDIO_D0 25 +3V_PCH
@ RH384 2 1 100K_0402_5%~D TS_INT# HDA_SPKR V2 E4
21 HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 SDIO_D1 25
C3
SDIO_D2/GPIO68 E2 SDIO_D2 25 2 1 10K_0402_5%~D 2 1 10K_0402_5%~D
@ RH271 MEM_CONFIG2 RH314
SDIO_D3/GPIO69 SDIO_D3 25
10 OF 19 @ RH303 2 1 10K_0402_5%~D MEM_CONFIG0 RH316 2 1 10K_0402_5%~D

+3VS @ RH180 2 1 10K_0402_5%~D MEM_CONFIG1 RH315 2 1 10K_0402_5%~D

+3VS

@ RH37 1 2 1K_0402_5%~D HDA_SPKR

+3VNS_PWR +3VS

*LOW=Default
HIGH=No Reboot I2C0_SDA CS@ RH461 1 2 2.2K_0402_5%~D I2C0_SDA @ RH424 1 2 2.2K_0402_5%~D GPIO Pin Pin Name Samsung 4G Hynix 4G Micron 4G
I2C is daisy chain
+3V_PCH I2C0_SCK CS@ RH462 1 2 2.2K_0402_5%~D I2C0_SCK @ RH425 1 2 2.2K_0402_5%~D routing with pull up
A @ PCH_GPIO59 MEM_CONFIG0 0 1 0 A
RH274 1 2 10K_0402_5%~D TPM_DET
on the last device

RH337 2 1 100K_0402_5%~D TPM_DET PCH_GPIO48 MEM_CONFIG1 0 0 1

@ @ RA7 1 2 0_0402_5%~D I2C0_SDA
20 I2C0_SDA_DSP
Audio DSP PCH_GPIO47 MEM_CONFIG2 0 0 0
@ RA8 1 2 0_0402_5%~D I2C0_SCK
20 I2C0_SCK_DSP
TPM BOM Optional 24 I2C0_SDA_SNR
CS@ R1225 2 1 0_0402_5%~D

TPM_DET Sensor HUB 24 I2C0_SCK_SNR

CS@ R1224 2 1 0_0402_5%~D Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

TPM 1 = W/TPM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P08-MCP(4/7) PM,GPIO,LPIO,MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0 = W/O TPM A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 8 of 49
5 4 3 2 1
 5 4 3 2 1

UCPU1K HSW_ULT_DDR3L

F10 AN8
PERN5_L0 USB2N0 USB20_N0 27
E10 AM8 USB3.0 (Power Share)
PERP5_L0 USB2P0 USB20_P0 27
C23 AR7
PETN5_L0 USB2N1 USB20_N1 27
C22 AT7 USB20_P1 27 USB3.0 (Power Share) Debug Port
D PETP5_L0 USB2P1 D
F8 AR8
PERN5_L1 USB2N2 USB20_N2 25
E8 AP8 USB20_P2 25 NGFF (WLAN)
PERP5_L1 USB2P2
B23 AR10 USB20_N3 19
A23 PETN5_L1 USB2N3 AT10
PETP5_L1 USB2P3 USB20_P3 19 Touch Panel
H10 AM15 USB20_N4 19
G10 PERN5_L2 USB2N4 AL15
PERP5_L2 USB2P4 USB20_P4 19 Camera
B21 AM13
PETN5_L2 USB2N5 USB20_N5 24
C21 AN13 Sensors HUB
PETP5_L2 USB2P5 USB20_P5 24
E6 AP11
PERN5_L3 USB2N6 USB20_N6 25
F6 AN11 USB20_P6 25 NGFF(WiGig)
PERP5_L3 USB2P6
B22 AR13
A21 PETN5_L3 USB2N7 AP13
PETP5_L3 USB2P7

25 PCIE_PRX_WLANTX_N3 G11
F11 PERN3 G20
25 PCIE_PRX_WLANTX_P3 PERP3 USB3RN1 USB3RN0 27
NGFF (WLAN) H20
USB3RP1 USB3RP0 27
25 PCIE_PTX_WLANRX_N3 CH11 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_N3_C C29
CH16 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_P3_C B30 PETN3 PCIE USB C33
25 PCIE_PTX_WLANRX_P3 PETP3 USB3TN1 USB3TN0 27
B34 USB3TP0 27
F13 USB3TP1
25 PCIE_PRX_DTX_N4 PERN4
G13 E18
25 PCIE_PRX_DTX_P4 PERP4 USB3RN2 USB3RN1 27
F18 USB3RP1 27
CH1237 1 2 0.1U_0402_10V7K~D PCIE_PTX_DRX_N4_C B29 USB3RP2
25 PCIE_PTX_DRX_N4 PETN4
25 PCIE_PTX_DRX_P4 CH1238 1 2 0.1U_0402_10V7K~D PCIE_PTX_DRX_P4_C A29 B33 USB3TN1 27
PETP4 USB3TN2 A33
USB3TP2 USB3TP1 27
G17
NGFF(WiGig) 25 PCIE_PRX_DTX_N1
F17 PERN1/USB3RN3
25 PCIE_PRX_DTX_P1 PERP1/USB3RP3
CH1242 1 2 0.1U_0402_10V7K~D PCIE_PTX_DRX_N1_C C30
Within 450 mils
25 PCIE_PTX_DRX_N1 PETN1/USB3TN3
25 PCIE_PTX_DRX_P1 CH1243 1 2 0.1U_0402_10V7K~D PCIE_PTX_DRX_P1_C C31 AJ10 USBRBIAS 1 2 Net USB_BIAS route impedacnes should be 50-ohm
PETP1/USB3TP3 USBRBIAS AJ11 and length less than 450-mil spacing is 15-mil.
F15 USBRBIAS AN10 RH163
C C
23 PCIE_PRX_CARDTX_N2 G15 PERN2/USB3RN4 RSVD AM10 22.6_0402_1%
23 PCIE_PRX_CARDTX_P2 PERP2/USB3RP4 RSVD
CardReader CH25 1 2 0.1U_0402_10V7K~D PCIE_PTX_C_CARDRX_N2 B31
23 PCIE_PTX_CARDRX_N2 PETN2/USB3TN4
23 PCIE_PTX_CARDRX_P2 CH26 1 2 0.1U_0402_10V7K~D PCIE_PTX_C_CARDRX_P2 A31
PETP2/USB3TP4 AL3
OC0/GPIO40 USB_OC0# 27,8
AT1 USB_OC1#
+V1.05S_AUSB3PLL OC1/GPIO41 USB_OC1# 27
AH2
OC2/GPIO42 USB_OC2# 7
E15 AV3 USB1_PWR_EN
E13 RSVD OC3/GPIO43 USB1_PWR_EN 27
RH338 1 2 3K_0402_1%~D PCIE_RCOMP A27 RSVD
B27 PCIE_RCOMP USB_OC1# RH160 1 2 10K_0402_5%~D
PCIE_IREF +3V_PCH

USB1_PWR_EN RH403 2 1 100K_0402_5%~D

Width = 15 mil, Spacing = 15 mil 11 OF 19
Close PCH within 500 mil

HSW_ULT_DDR3L
UCPU1Q

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4
AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1
B
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 B
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63
17 OF 19 DAISY_CHAIN_NCTF_AW63

HSW_ULT_DDR3L
UCPU1R

N23
RSVD R23
RSVD T23
AT2 RSVD
RSVD U10
AU44 RSVD
AV44 RSVD
D15 RSVD
RSVD AL1
RSVD AM11
RSVD AP7
F22 RSVD
RSVD AU10
H22 RSVD
RSVD AU15
J21 RSVD
RSVD AW14
RSVD AY14
RSVD

18 OF 19

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P09-MCP(5/7) PCIE,USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 9 of 49
5 4 3 2 1
 5 4 3 2 1

+1.35V_DDR

+1.35V_DDR +VCC_CORE
HSW_ULT_DDR3L
UCPU1L
+1.05VS_VCCST

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
1 1 1 1 1 1
4.2A L59 C36
J58 RSVD VCC C40
RSVD VCC

CC160

CC161

CC162

CC163

CC164

CC165
C44
VCC

1
AH26 C48
2 2 2 2 2 2 R1211 AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
1M_0402_5%~D VDDQ VCC
AJ37 E23
AN33 VDDQ VCC E25

2
AP43 VDDQ VCC E27
IMVP_VR_PG AR48 VDDQ VCC E29
32,43 IMVP_VR_PG VDDQ VCC
AY35 E31
D
AY40 VDDQ VCC E33 D
+VCC_CORE AY44 VDDQ VCC E35
VDDQ VCC
2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D

2.2U_0402_6.3V6M~D
AY50 E37
VDDQ VCC E39
1 1 1 1 VCC
+VCC_CORE
CC233

CC238

CC239

CC234
F59 E41
+VCCIO_OUT N58 VCC VCC E43
RC97 & RC98 close to PCH RSVD VCC
AC58 E45
2 2 2 2 RC97 1 2 100_0402_1%~D RSVD VCC E47
@ RC98 1 2 0_0402_5% VCCSENSE_R E63 VCC E49
1 43 VCCSENSE VCC_SENSE VCC
AB23 E51
CH1241 A59 RSVD VCC E53
+VCCIO_OUT VCCIO_OUT VCC
0.1U_0402_10V7K~D E20 E55
2 +VCCIOA_OUT VCCIOA_OUT VCC
AD23 E57
AA23 RSVD VCC F24
AE59 RSVD VCC F28
RSVD VCC F32
RC94 1 2 43_0402_5%~D H_CPU_SVIDALRT# L62 VCC F36
43 VR_SVID_ALRT# VIDALERT HSW ULT POWER VCC
43 VR_SVID_CLK @ RC92 1 2 0_0402_5%~D H_CPU_SVIDCLK N63 F40
@ RC96 1 2 0_0402_5%~D H_CPU_SVIDDAT L63 VIDSCLK VCC F44
43 VR_SVID_DAT VIDSOUT VCC
@ RC150 1 2 0_0402_5%~D VCCSTPG_MCP B59 F48
17,32 1.05VS_VCCST_PG VCCST_PWRGD VCC
43 VR_ON VR_ON @ RC151 1 2 0_0402_5%~D VR_ON_MCP F60 F52
IMVP_VR_PG @ RC152 1 2 0_0402_5%~D VRPG_MCP C59 VR_EN VCC F56
VR_READY VCC G23
D63 VCC G25
FIVE_EN H59 VSS VCC G27
17 FIVE_EN PWR_DEBUG VCC
close to CPU P62 G29
+1.05VS_VCCST P60 VSS VCC G31
P61 RSVD_TP VCC G33
+1.05VS SIP +1.05VS_VCCST N59 RSVD_TP VCC G35
RC93 2 1 75_0402_5% H_CPU_SVIDALRT# N61 RSVD_TP VCC G37
@ RH340 T59 RSVD_TP VCC G39
RC95 1 2 130_0402_1% H_CPU_SVIDDAT 1 2
0802-12 +1.05VS_VCCST AD60 RSVD VCC G41
R1179 RSVD VCC
AD59 G43
VIDSOUT: 0_0805_5% 1 2 FIVE_EN AA59 RSVD VCC G45
1 1 RSVD VCC
Requires a pull-up to VCCIO through a pull-up resistor of 110 ±5% close to the processor, and a pull-up AE60 G47
to VCCIO through a pull-up resistor of 110 ±5% close to Intel MVP 7. CH1204 CH1205 150_0402_5%~D AC59 RSVD VCC G49
VIDSCLK: 22U_0603_6.3V6M~D 1U_0402_6.3V6K~D AG58 RSVD VCC G51
Required pull-up to VCCIO through 55 ±5% close to Intel IMVP 7. 2 2 RSVD VCC
C U59 G53 C
V59 RSVD VCC G55
RSVD VCC G57
AC22 VCC H23
+1.05VS_VCCST VCCST VCC
AE22 J23
AE23 VCCST VCC K23
VCCST VCC K57
AB57 VCC L22
+VCC_CORE VCC VCC
AD57 M23
AG57 VCC VCC M57
+1.05VDX_MODPHY C24 VCC VCC P57
SIP C28 VCC VCC U57
R1240 1 2 0_1206_5% +V1.05VS_VCCHSIO C32 VCC VCC W57
VCC VCC
12 OF 19
0802-13 1 1
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
CH40

CH41

2 2

+1.5VS_3.3VS_AUDIO

HSW_ULT_DDR3L
UCPU1M
+1.5VS_3.3VS_AUDIO
+1.05VS +V1.05VS_VCCHSIO K9
+1.05VDX_MODPHY +V1.05S_AUSB3PLL L10 VCCHSIO +RTCVCC
1 VCCHSIO
LH10 M9
1 2 CH85 N8 VCCHSIO HSIO RTC AH11 +RTC_VCCSUS
1U_0402_6.3V6K~D P9 VCC1_05 VCCSUS3_3 AG10
2.2UH_LQM21PN2R2MC0D_20% 2 B18 VCC1_05 VCCRTC AE7 CH1206 1 2 0.1U_0402_10V7K~D
1 1 1 +V1.05S_AUSB3PLL VCCUSB3PLL DCPRTC
B11
+V1.05S_ASATA3PLL VCCSATA3PLL
CH1208 CH1209 CH39
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V6K~D
2 2 2 Y20 SPI Y8
RSVD VCCSPI +3.3V_M
+V1.05S_APLLOPI AA21 OPI
W21 VCCAPLL
VCCAPLL 1
AG14 +1.05V_M @
B +1.05VS +1.05V_M VCCASW AG13 CH47
B

LH12 @ RH405 VCCASW 0.1U_0402_10V7K~D +1.05VS

1 2 1 2 J13 USB3 2
+V1.05S_APLLOPI +V1.05A_DCPSUS
DCPSUS3 closed to VCC1P05
1 J11
2.2UH_LQM2MPN2R2NG0L_30% @ VCC1_05 H11
1 1 1@ 0_0603_5%~D
VCC1_05
CH1212 + CH1239 CH1214 +1.5VS_3.3VS_AUDIO AH14 HDA H15 1 1 1
100U_A_6.3V_R70M CH1213 10U_0603_6.3V6M~D 1U_0402_6.3V6K~D VCCHDA VCC1_05 AE8
1U_0402_6.3V6K~D VCC1_05 AF22 CH1215 CH1216 CH1217
2 2 2 2 AH13 VRM VCC1_05 AG19 @ RH346 CH1218 1U_0402_6.3V6K~D 1U_0402_6.3V6K~D 10U_0603_6.3V6M~D
DCPSUS2 CORE DCPSUSBYP AG20 +PCH_VCCDSW 1 2 1 2 2 2 2
+3V_PCH DCPSUSBYP AE9 +1.05V_M +RTCVCC
VCCASW AF9
VCCASW
0_0402_5% 1U_0402_6.3V6K~D closed to VCCRTC
AC9 AG8
+1.05VDX_MODPHY +V1.05S_ASATA3PLL AA9 VCCSUS3_3 GPIO/LPC
VCCASW AD10
LH11 AH10 VCCSUS3_3 DCPSUS1 AD8 +V1.05A_DCPSUS
1 +3V_PCH_DSW VCCDSW3_3 DCPSUS1 1 1 1 1 1
1 2 V8 @
+3VS VCC3_3
CH1220 W9 CH1222 CH1223 CH84 CH83 CH82
2.2UH_LQM21PN2R2MC0D_20% 22U_0603_6.3V6M~D VCC3_3 J15 1U_0402_6.3V6K~D 22U_0603_6.3V6M~D 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
1 1 2 1 VCCTS1_5 +1.5VS 2 2 2 2 2
THERMAL SENSOR K14
CH1210 CH1211 CH1225 VCC3_3 K16
VCC3_3 +3VS
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0603_6.3V6M~D
2 2 2
+V1.05S_AXCK_DCB J18
1 0802-12 RH350
+1.05VS K19 VCCCLK SERIAL IO U8 +VS_LPSS_SDIO CH1226 1 2
+V1.05S_AXCK_LCPLL A20 VCCCLK VCCSDIO T9 0.1U_0402_10V7K~D 0806-22 +1.8VS
+V1.05S_AXCK_LCPLL VCCACLKPLL VCCSDIO 2
J17 0_0603_5%~D
R21 VCCCLK +VS_LPSS_SDIO
Deep S3 Support +1.05VS
T21 VCCCLK LPT LP POWER SIP +3V_PCH @ RH354
1 VCCCLK
Non-CS@ RH348 K18 SUS OSCILLATOR AB8 +V1.05A_AOSCSUS @ RH341 +VS_LPSS_SDIO 1 2
1 RSVD DCPSUS4 +3VS
+3VALW 1 2 CH1234 M20 +RTC_VCCSUS 2 1
0_0603_5%~D 1U_0402_6.3V6K~D CH1235 V21 RSVD 0_0603_5%~D
RSVD 1
2 1U_0402_6.3V6K~D AE20 AC20 T280@ 0_0603_5%~D
2 VCCSUS3_3 RSVD 1
AE21 AG16 +1.05VS CH1227
CS@ 1 RH351 2 VCCSUS3_3 USB2 VCC1_05 AG17 CH1207 1U_0402_6.3V6K~D
+3V_PCH +3V_PCH_DSW VCC1_05 2 +1.05V_M
0_0603_5%~D 1 1U_0402_6.3V6K~D
2 @
Non Deep S3 1
CH1233 L63 @ RH406
A CH1224 13 OF 19 1U_0402_6.3V6K~D +V1.05A_AOSCSUS 1 2 +V1.05A_AOSCSUS_L 1 2 A
1U_0402_6.3V6K~D 2
2 1
1 2.2UH_LQM2MPN2R2NG0L_30% 0_0603_5%~D
DCPSUS can be NC, if INTVRMEN pull up @ + CH1240
CH1232 100U_A_6.3V_R70M
+1.05VS +1.05VS to enable Integrated VRM 1U_0402_6.3V6K~D @
2 2
@ RH355 L61 @ RH356 L62
1 2 +V1.05S_AXCK_DCB_L 1 2 +V1.05S_AXCK_DCB 1 2 +V1.05S_AXCK_LCPLL_L 1 2 +V1.05S_AXCK_LCPLL
1
0_0603_5%~D 2.2UH_LQM2MPN2R2NG0L_30% 0_0603_5%~D 2.2UH_LQM2MPN2R2NG0L_30%
CH1228 +
1 1 1 Security Classification Compal Secret Data Compal Electronics, Inc.
100U_A_6.3V_R70M CH1229 CH1230 CH1231 2011/06/02 2013/10/28 Title
Issued Date Deciphered Date
1U_0402_6.3V6K~D 100U_1206_6.3V6M 1U_0402_6.3V6K~D
2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P10-MCP(6/7) PWR,VCC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 10 of 49
5 4 3 2 1
 5 4 3 2 1

UCPU1S HSW_ULT_DDR3L

AC60 AV63
17 CFG0 AC62 CFG0 RSVD_TP AU63
17 CFG1 CFG1 RSVD_TP
AC63
D 17 CFG2 CFG2 D
1K_0402_5% 2 1 RC81 CFG4 CFG3 AA63
17 CFG3 AA60 CFG3 C63
CFG4
17 CFG4 CFG4 RSVD_TP
Y62 C62
17 CFG5 Y61 CFG5 RSVD_TP B43
17 CFG6 CFG6 RSVD
eDP Strap Y60
17 CFG7 CFG7
V62 A51
17 CFG8 V61 CFG8 RSVD_TP B51
17 CFG9 CFG9 RSVD_TP
1 : Disabled; No Physical Display Port V60
17 CFG10 U60 CFG10 L60
attached to Embedded Display Port 17 CFG11
T63 CFG11 RSVD_TP
17 CFG12 CFG12 RESERVED
T62 N60
17 CFG13 T61 CFG13 RSVD
CFG4 17 CFG14 CFG14
T60 W23
* 0 : Enabled; An external Display 17 CFG15 CFG15 RSVD Y22
Port device is connected to the AA62 RSVD AY15 PROC_OPI_COMP
17 CFG16 CFG16 PROC_OPI_RCOMP
Embedded Display Port 17 CFG18
U63
CFG18
AA61 AV62
17 CFG17 CFG17 RSVD
U62 D58
17 CFG19 CFG19 RSVD
CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
A5 VSS
RSVD P20
49.9_0402_1%~D 2 1 RC153 CFG_RCOMP E1 RSVD R20
D1 RSVD RSVD
49.9_0402_1%~D 2 1 RC154 PROC_OPI_COMP J20 RSVD
H18 RSVD
8.2K_0402_1% 2 1 RC155 TD_IREF TD_IREF B12 RSVD 19 OF 19
TD_IREF

Width = 15 mil, Spacing = 15 mil

Close PCH within 500 mil

C C

HSW_ULT_DDR3L HSW_ULT_DDR3L
UCPU1N UCPU1O
UCPU1P HSW_ULT_DDR3L
A11 AJ35 AP22 AV59 H17
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D33 VSS H57
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D34 VSS VSS J10
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D35 VSS VSS J22
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D37 VSS VSS J59
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D38 VSS VSS J63
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D39 VSS VSS K1
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D41 VSS VSS K12
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D42 VSS VSS L13
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D43 VSS VSS L15
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D45 VSS VSS L17
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D46 VSS VSS L18
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D47 VSS VSS L20
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D49 VSS VSS L58
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D5 VSS VSS L61
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D50 VSS VSS L7
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D51 VSS VSS M22
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D53 VSS VSS N10
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D54 VSS VSS N3
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D55 VSS VSS P59
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D57 VSS VSS P63
B
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D59 VSS VSS R10 B
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D62 VSS VSS R22
AE5 VSS VSS AL29 AT13 VSS VSS AY33 D8 VSS VSS R8
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E11 VSS VSS T1
AF11 VSS VSS AL33 AT37 VSS VSS AY51 E17 VSS VSS T58
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F20 VSS VSS U20
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F26 VSS VSS U22
AF15 VSS VSS AL40 AT43 VSS VSS AY59 F30 VSS VSS U61
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F34 VSS VSS U9
AF18 VSS VSS AL46 AT49 VSS VSS B20 F38 VSS VSS V10
AG1 VSS VSS AL51 AT61 VSS VSS B24 F42 VSS VSS V3
AG11 VSS VSS AL52 AT62 VSS VSS B26 F46 VSS VSS V7
AG21 VSS VSS AL54 AT63 VSS VSS B28 F50 VSS VSS W20
AG23 VSS VSS AL57 AU1 VSS VSS B32 F54 VSS VSS W22
AG60 VSS VSS AL60 AU16 VSS VSS B36 F58 VSS VSS Y10
AG61 VSS VSS AL61 AU18 VSS VSS B4 F61 VSS VSS Y59
AG62 VSS VSS AM1 AU20 VSS VSS B40 G18 VSS VSS Y63
AG63 VSS VSS AM17 AU22 VSS VSS B44 G22 VSS VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G3 VSS
AH19 VSS VSS AM31 AU26 VSS VSS B52 G5 VSS V58
AH20 VSS VSS AM52 AU28 VSS VSS B56 G6 VSS VSS AH46
VSS VSS VSS VSS VSS VSS RC99 & RC100 close to PCH
AH22 AN17 AU30 B60 G8 V23
AH24 VSS VSS AN23 AU33 VSS VSS C11 H13 VSS VSS E62 VSSSENSE_R @ RC99 1 2 0_0402_5%
VSS VSS VSS VSS VSS VSS_SENSE VSSSENSE 43
AH28 AN31 AU51 C14 AH16 RC100 1 2 100_0402_1%~D
AH30 VSS VSS AN32 AU53 VSS VSS C18 16 OF 19 VSS
AH32 VSS VSS AN35 AU55 VSS VSS C20
AH34 VSS VSS AN36 AU57 VSS VSS C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
AH51 VSS VSS AN48 AV33 VSS VSS D18
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23
AJ13 VSS VSS AN60 AV41 VSS VSS D25
A A
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 VSS

14 OF 19
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P11-MCP(7/7) PWR,VSS,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 11 of 49
5 4 3 2 1
 5 4 3 2 1

follow INTEL PDG

CD1 1 2 0.047U_0402_16V4Z
http://eloy-motherboards.blogspot.com
CD2 1 2 0.047U_0402_16V4Z
+VREFCA

CD3 1 2 0.047U_0402_16V4Z

CD4 1 2 0.047U_0402_16V4Z
+VREFDQ_A
D D

PLACE THESE CAPS

NEAR TO RESPECTIVE DRAM

UD1 UD2

M8 E3 DDR_A_D6 M8 E3 DDR_A_D18
+VREFCA VREFCA DQL0 +VREFCA VREFCA DQL0
H1 F7 DDR_A_D0 H1 F7 DDR_A_D16
+VREFDQ_A VREFDQ DQL1 +VREFDQ_A VREFDQ DQL1
F2 DDR_A_D2 F2 DDR_A_D22
DDR_A_MA0 N3 DQL2 F8 DDR_A_D5 DDR_A_MA0 N3 DQL2 F8 DDR_A_D21
13,6 DDR_A_DQS#[0..7] A0 DQL3 A0 DQL3
DDR_A_MA1 P7 H3 DDR_A_D3 DDR_A_MA1 P7 H3 DDR_A_D19
DDR_A_MA2 P3 A1 DQL4 H8 DDR_A_D4 DDR_A_MA2 P3 A1 DQL4 H8 DDR_A_D20
13,6 DDR_A_DQS[0..7] A2 DQL5 A2 DQL5
DDR_A_MA3 N2 G2 DDR_A_D7 DDR_A_MA3 N2 G2 DDR_A_D23
DDR_A_MA4 P8 A3 DQL6 H7 DDR_A_D1 DDR_A_MA4 P8 A3 DQL6 H7 DDR_A_D17
13,6 DDR_A_D[0..63] A4 DQL7 A4 DQL7
DDR_A_MA5 P2 DDR_A_MA5 P2
DDR_A_MA6 R8 A5 DDR_A_MA6 R8 A5
13,16,6 DDR_A_MA[0..15] A6 A6
DDR_A_MA7 R2 D7 DDR_A_D13 DDR_A_MA7 R2 D7 DDR_A_D29
DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D15 DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D27
DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D12 DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D28
DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D14 DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D26
DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D8 DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D24
DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D11 DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D31
All VREF traces should A12/BC# DQU5 A12/BC# DQU5
have 10 mil trace width DDR_A_MA13 T3 B8 DDR_A_D9 DDR_A_MA13 T3 B8 DDR_A_D25
DDR_A_MA14 T7 A13 DQU6 A3 DDR_A_D10 DDR_A_MA14 T7 A13 DQU6 A3 DDR_A_D30
DDR_A_MA15 M7 A14 DQU7 DDR_A_MA15 M7 A14 DQU7
A15/NC A15/NC

DDR_A_BS0 M2 B2 DDR_A_BS0 M2 B2
13,16,6 DDR_A_BS0 BA0 VDD +1.35V_DDR BA0 VDD +1.35V_DDR
DDR_A_BS1 N8 D9 DDR_A_BS1 N8 D9
13,16,6 DDR_A_BS1 M3 BA1 VDD G7 M3 BA1 VDD G7
DDR_A_BS2 DDR_A_BS2
13,16,6 DDR_A_BS2 BA2 VDD BA2 VDD
K2 K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK_A_DDR0 J7 VDD N9 M_CLK_A_DDR0 J7 VDD N9
C C
13,16,6 M_CLK_A_DDR0 K7 CK VDD R1 K7 CK VDD R1
M_CLK_A_DDR#0 M_CLK_A_DDR#0
13,16,6 M_CLK_A_DDR#0 CK# VDD CK# VDD
R9 R9
VDD VDD
DDR_A_CKE0 K9 DDR_A_CKE0 K9
13,16,6 DDR_A_CKE0 CKE0 CKE0
DDR_A_CKE1 J9 A1 DDR_A_CKE1 J9 A1
13,16,6 DDR_A_CKE1 K1 CKE1/NC VDDQ A8 K1 CKE1/NC VDDQ A8
M_ODT0 M_ODT0
13,16 M_ODT0 ODT0 VDDQ ODT0 VDDQ
J1 C1 J1 C1
DDR_A_CS0# L2 ODT1/NC VDDQ C9 DDR_A_CS0# L2 ODT1/NC VDDQ C9
13,16,6 DDR_A_CS0# L1 CS0# VDDQ D2 L1 CS0# VDDQ D2
DDR_A_CS1# DDR_A_CS1#
13,16,6 DDR_A_CS1# CS1#/NC VDDQ CS1#/NC VDDQ
E9 E9
VDDQ F1 VDDQ F1
DDR_A_RAS# J3 VDDQ H2 DDR_A_RAS# J3 VDDQ H2
13,16,6 DDR_A_RAS# RAS# VDDQ RAS# VDDQ
DDR_A_CAS# K3 H9 DDR_A_CAS# K3 H9
13,16,6 DDR_A_CAS# L3 CAS# VDDQ L3 CAS# VDDQ
DDR_A_WE# DDR_A_WE#
13,16,6 DDR_A_WE# WE# WE#
A9 A9
DDR_A_DQS0 F3 VSS B3 DDR_A_DQS2 F3 VSS B3
DDR_A_DQS1 C7 DQSL VSS E1 DDR_A_DQS3 C7 DQSL VSS E1
DQSU VSS G8 DQSU VSS G8
VSS J2 VSS J2
DDR_A_DQS#0 G3 VSS J8 DDR_A_DQS#2 G3 VSS J8
DDR_A_DQS#1 B7 DQSL# VSS M1 DDR_A_DQS#3 B7 DQSL# VSS M1
DQSU# VSS M9 DQSU# VSS M9
VSS P1 VSS P1
E7 VSS P9 E7 VSS P9
D3 DML VSS T1 D3 DML VSS T1
DMU VSS T9 DMU VSS T9
VSS VSS

13,14,15,5 DDR3_DRAMRST# DDR3_DRAMRST# T2 B1 DDR3_DRAMRST# T2 B1

RESET# VSSQ B9 RESET# VSSQ B9
VSSQ VSSQ
0.1U_0402_25V6K~D

D1 D1
@ VSSQ D8 VSSQ D8
1 VSSQ VSSQ
C
CD5

RD1 2 1 240_0402_1% L8 E2 RD2 2 1 240_0402_1% L8 E2

D5

ZQ0 VSSQ E8 ZQ0 VSSQ E8

RD79 2 1 240_0402_1% L9 VSSQ F9 RD80 2 1 240_0402_1% L9 VSSQ F9
2 ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
B VSSQ G9 VSSQ G9 B
VSSQ VSSQ
96-BALL 96-BALL
CAD NOTE: SDRAM DDR3L SDRAM DDR3L
MT41K256M16HA-125M:E_FBGA96 MT41K256M16HA-125M:E_FBGA96
PLACE THE CAP NEAR TO
SDRAM RESET PIN

+1.35V_DDR
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

1 1 1 1 1 1 1 1 1
1

1
CD14

CD17

CD19

CD20

CD21

CD111

CD113
CD15

CD16

CD18

CD112

CD114

@
+ CD22
A 330U_B2_2VM_R15M A
2

2 2 2 2 2 2 2 2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P12-DDRIII Channel_A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
X02
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 12 of 49
5 4 3 2 1
 5 4 3 2 1

follow INTEL PDG

CD24 1 2 0.047U_0402_16V4Z

CD25 1 2 0.047U_0402_16V4Z +VREFCA

CD26 1 2 0.047U_0402_16V4Z
D D
CD27 1 2 0.047U_0402_16V4Z
+VREFDQ_A

PLACE THESE CAPS

NEAR TO RESPECTIVE DRAM UD4 UD5

+VREFCA M8 E3 DDR_A_D39 +VREFCA M8 E3 DDR_A_D55

H1 VREFCA DQL0 F7 DDR_A_D37 H1 VREFCA DQL0 F7 DDR_A_D53
+VREFDQ_A VREFDQ DQL1 +VREFDQ_A VREFDQ DQL1
F2 DDR_A_D34 F2 DDR_A_D54
DDR_A_MA0 N3 DQL2 F8 DDR_A_D32 DDR_A_MA0 N3 DQL2 F8 DDR_A_D51
DDR_A_MA1 P7 A0 DQL3 H3 DDR_A_D35 DDR_A_MA1 P7 A0 DQL3 H3 DDR_A_D49
DDR_A_MA2 P3 A1 DQL4 H8 DDR_A_D33 DDR_A_MA2 P3 A1 DQL4 H8 DDR_A_D52
DDR_A_MA3 N2 A2 DQL5 G2 DDR_A_D38 DDR_A_MA3 N2 A2 DQL5 G2 DDR_A_D48
DDR_A_MA4 P8 A3 DQL6 H7 DDR_A_D36 DDR_A_MA4 P8 A3 DQL6 H7 DDR_A_D50
12,6 DDR_A_DQS#[0..7] A4 DQL7 A4 DQL7
DDR_A_MA5 P2 DDR_A_MA5 P2
DDR_A_MA6 R8 A5 DDR_A_MA6 R8 A5
12,6 DDR_A_DQS[0..7] A6 A6
DDR_A_MA7 R2 D7 DDR_A_D44 DDR_A_MA7 R2 D7 DDR_A_D62
DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D47 DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D57
12,6 DDR_A_D[0..63] A8 DQU1 A8 DQU1
DDR_A_MA9 R3 C8 DDR_A_D45 DDR_A_MA9 R3 C8 DDR_A_D63
DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D46 DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D56
12,16,6 DDR_A_MA[0..15] A10/AP DQU3 A10/AP DQU3
DDR_A_MA11 R7 A7 DDR_A_D41 DDR_A_MA11 R7 A7 DDR_A_D59
DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D42 DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D61
DDR_A_MA13 T3 A12/BC# DQU5 B8 DDR_A_D40 DDR_A_MA13 T3 A12/BC# DQU5 B8 DDR_A_D58
DDR_A_MA14 T7 A13 DQU6 A3 DDR_A_D43 DDR_A_MA14 T7 A13 DQU6 A3 DDR_A_D60
All VREF traces should
DDR_A_MA15 M7 A14 DQU7 DDR_A_MA15 M7 A14 DQU7
have 10 mil trace width A15/NC A15/NC

DDR_A_BS0 M2 B2 DDR_A_BS0 M2 B2
12,16,6 DDR_A_BS0 BA0 VDD +1.35V_DDR BA0 VDD +1.35V_DDR
DDR_A_BS1 N8 D9 DDR_A_BS1 N8 D9
12,16,6 DDR_A_BS1 BA1 VDD BA1 VDD
DDR_A_BS2 M3 G7 DDR_A_BS2 M3 G7
12,16,6 DDR_A_BS2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK_A_DDR0 J7 VDD N9 M_CLK_A_DDR0 J7 VDD N9
12,16,6 M_CLK_A_DDR0 CK VDD CK VDD
M_CLK_A_DDR#0 K7 R1 M_CLK_A_DDR#0 K7 R1
12,16,6 M_CLK_A_DDR#0 CK# VDD R9 CK# VDD R9
VDD VDD
C C
DDR_A_CKE0 K9 DDR_A_CKE0 K9
12,16,6 DDR_A_CKE0 CKE0 CKE0
DDR_A_CKE1 J9 A1 DDR_A_CKE1 J9 A1
12,16,6 DDR_A_CKE1 CKE1/NC VDDQ CKE1/NC VDDQ
M_ODT0 K1 A8 M_ODT0 K1 A8
12,16 M_ODT0 J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
DDR_A_CS0# L2 ODT1/NC VDDQ C9 DDR_A_CS0# L2 ODT1/NC VDDQ C9
12,16,6 DDR_A_CS0# L1 CS0# VDDQ D2 L1 CS0# VDDQ D2
DDR_A_CS1# DDR_A_CS1#
12,16,6 DDR_A_CS1# CS1#/NC VDDQ CS1#/NC VDDQ
E9 E9
VDDQ F1 VDDQ F1
DDR_A_RAS# J3 VDDQ H2 DDR_A_RAS# J3 VDDQ H2
12,16,6 DDR_A_RAS# RAS# VDDQ RAS# VDDQ
DDR_A_CAS# K3 H9 DDR_A_CAS# K3 H9
12,16,6 DDR_A_CAS# L3 CAS# VDDQ L3 CAS# VDDQ
DDR_A_WE# DDR_A_WE#
12,16,6 DDR_A_WE# WE# WE#
A9 A9
DDR_A_DQS4 F3 VSS B3 DDR_A_DQS6 F3 VSS B3
DDR_A_DQS5 C7 DQSL VSS E1 DDR_A_DQS7 C7 DQSL VSS E1
DQSU VSS G8 DQSU VSS G8
VSS J2 VSS J2
DDR_A_DQS#4 G3 VSS J8 DDR_A_DQS#6 G3 VSS J8
DDR_A_DQS#5 B7 DQSL# VSS M1 DDR_A_DQS#7 B7 DQSL# VSS M1
DQSU# VSS M9 DQSU# VSS M9
VSS P1 VSS P1
E7 VSS P9 E7 VSS P9
D3 DML VSS T1 D3 DML VSS T1
DMU VSS T9 DMU VSS T9
VSS VSS

12,14,15,5 DDR3_DRAMRST# DDR3_DRAMRST# T2 B1 DDR3_DRAMRST# T2 B1

RESET# VSSQ RESET# VSSQ
0.1U_0402_25V6K~D

B9 B9
VSSQ D1 VSSQ D1
@ VSSQ D8 VSSQ D8
1 VSSQ VSSQ
CD28

RD5 2 1 240_0402_1% L8 E2 RD6 2 1 240_0402_1% L8 E2

ZQ0 VSSQ E8 ZQ0 VSSQ E8
RD81 2 1 240_0402_1% L9 VSSQ F9 RD82 2 1 240_0402_1% L9 VSSQ F9
2 ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
B B
CAD NOTE: SDRAM DDR3L SDRAM DDR3L
PLACE THE CAP NEAR TO MT41K256M16HA-125M:E_FBGA96 MT41K256M16HA-125M:E_FBGA96
SDRAM RESET PIN

+1.35V_DDR
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1 1 1 1 1 1 1 1
1

1
CD37

CD38

CD39

CD40

CD41

CD42

CD43

CD44

CD115

CD116

CD117

CD118
2

2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P13-DDRIII Channel_A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 13 of 49
5 4 3 2 1
 5 4 3 2 1

follow INTEL PDG

CD45 1 2 0.047U_0402_16V4Z

CD46 1 2 0.047U_0402_16V4Z +VREFCA

CD47 1 2 0.047U_0402_16V4Z
D D
CD48 1 2 0.047U_0402_16V4Z
+VREFDQ_B
UD6 UD7
PLACE THESE CAPS
+VREFCA M8 E3 DDR_B_D22 +VREFCA M8 E3 DDR_B_D7
NEAR TO RESPECTIVE DRAM +VREFDQ_B
H1 VREFCA DQL0 F7 DDR_B_D21 +VREFDQ_B
H1 VREFCA DQL0 F7 DDR_B_D1
VREFDQ DQL1 F2 DDR_B_D18 VREFDQ DQL1 F2 DDR_B_D3
DDR_B_MA0 N3 DQL2 F8 DDR_B_D17 DDR_B_MA0 N3 DQL2 F8 DDR_B_D5
DDR_B_MA1 P7 A0 DQL3 H3 DDR_B_D23 DDR_B_MA1 P7 A0 DQL3 H3 DDR_B_D6
DDR_B_MA2 P3 A1 DQL4 H8 DDR_B_D16 DDR_B_MA2 P3 A1 DQL4 H8 DDR_B_D4
DDR_B_MA3 N2 A2 DQL5 G2 DDR_B_D19 DDR_B_MA3 N2 A2 DQL5 G2 DDR_B_D2
DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D20 DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D0
DDR_B_MA5 P2 A4 DQL7 DDR_B_MA5 P2 A4 DQL7
15,6 DDR_B_DQS#[0..7] A5 A5
DDR_B_MA6 R8 DDR_B_MA6 R8
DDR_B_MA7 R2 A6 D7 DDR_B_D30 DDR_B_MA7 R2 A6 D7 DDR_B_D8
15,6 DDR_B_DQS[0..7] A7 DQU0 A7 DQU0
DDR_B_MA8 T8 C3 DDR_B_D26 DDR_B_MA8 T8 C3 DDR_B_D12
DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D29 DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D15
15,6 DDR_B_D[0..63] A9 DQU2 A9 DQU2
DDR_B_MA10 L7 C2 DDR_B_D27 DDR_B_MA10 L7 C2 DDR_B_D14
DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D25 DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D13
15,16,6 DDR_B_MA[0..15] A11 DQU4 A11 DQU4
DDR_B_MA12 N7 A2 DDR_B_D28 DDR_B_MA12 N7 A2 DDR_B_D10
DDR_B_MA13 T3 A12/BC# DQU5 B8 DDR_B_D24 DDR_B_MA13 T3 A12/BC# DQU5 B8 DDR_B_D9
DDR_B_MA14 T7 A13 DQU6 A3 DDR_B_D31 DDR_B_MA14 T7 A13 DQU6 A3 DDR_B_D11
DDR_B_MA15 M7 A14 DQU7 DDR_B_MA15 M7 A14 DQU7
A15/NC A15/NC

All VREF traces should DDR_B_BS0 M2 B2 DDR_B_BS0 M2 B2

15,16,6 DDR_B_BS0 BA0 VDD +1.35V_DDR BA0 VDD +1.35V_DDR
have 10 mil trace width DDR_B_BS1 N8 D9 DDR_B_BS1 N8 D9
15,16,6 DDR_B_BS1 BA1 VDD BA1 VDD
DDR_B_BS2 M3 G7 DDR_B_BS2 M3 G7
15,16,6 DDR_B_BS2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK_B_DDR0 J7 VDD N9 M_CLK_B_DDR0 J7 VDD N9
15,16,6 M_CLK_B_DDR0 CK VDD CK VDD
M_CLK_B_DDR#0 K7 R1 M_CLK_B_DDR#0 K7 R1
15,16,6 M_CLK_B_DDR#0 CK# VDD R9 CK# VDD R9
VDD VDD
DDR_B_CKE0 K9 DDR_B_CKE0 K9
15,16,6 DDR_B_CKE0 J9 CKE0 A1 J9 CKE0 A1
DDR_B_CKE1 DDR_B_CKE1
15,16,6 DDR_B_CKE1 CKE1/NC VDDQ CKE1/NC VDDQ
C M_ODT2 K1 A8 M_ODT2 K1 A8 C
15,16 M_ODT2 J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
DDR_B_CS0# L2 ODT1/NC VDDQ C9 DDR_B_CS0# L2 ODT1/NC VDDQ C9
15,16,6 DDR_B_CS0# CS0# VDDQ CS0# VDDQ
DDR_B_CS1# L1 D2 DDR_B_CS1# L1 D2
15,16,6 DDR_B_CS1# CS1#/NC VDDQ E9 CS1#/NC VDDQ E9
VDDQ F1 VDDQ F1
DDR_B_RAS# J3 VDDQ H2 DDR_B_RAS# J3 VDDQ H2
15,16,6 DDR_B_RAS# RAS# VDDQ RAS# VDDQ
DDR_B_CAS# K3 H9 DDR_B_CAS# K3 H9
15,16,6 DDR_B_CAS# CAS# VDDQ CAS# VDDQ
DDR_B_WE# L3 DDR_B_WE# L3
15,16,6 DDR_B_WE# WE# WE#
A9 A9
DDR_B_DQS2 F3 VSS B3 DDR_B_DQS0 F3 VSS B3
DDR_B_DQS3 C7 DQSL VSS E1 DDR_B_DQS1 C7 DQSL VSS E1
DQSU VSS G8 DQSU VSS G8
VSS J2 VSS J2
DDR_B_DQS#2 G3 VSS J8 DDR_B_DQS#0 G3 VSS J8
DDR_B_DQS#3 B7 DQSL# VSS M1 DDR_B_DQS#1 B7 DQSL# VSS M1
DQSU# VSS M9 DQSU# VSS M9
VSS P1 VSS P1
E7 VSS P9 E7 VSS P9
D3 DML VSS T1 D3 DML VSS T1
DMU VSS T9 DMU VSS T9
VSS VSS

DDR3_DRAMRST# T2 B1 DDR3_DRAMRST# T2 B1
12,13,15,5 DDR3_DRAMRST# RESET# VSSQ RESET# VSSQ
0.1U_0402_25V6K~D

B9 B9
VSSQ D1 VSSQ D1
@ VSSQ D8 VSSQ D8
1 VSSQ VSSQ
CD49

RD7 2 1 240_0402_1% L8 E2 RD8 2 1 240_0402_1% L8 E2

ZQ0 VSSQ E8 ZQ0 VSSQ E8
RD83 2 1 240_0402_1% L9 VSSQ F9 RD84 2 1 240_0402_1% L9 VSSQ F9
2 ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
CAD NOTE: SDRAM DDR3L SDRAM DDR3L
PLACE THE CAP NEAR TO MT41K256M16HA-125M:E_FBGA96 MT41K256M16HA-125M:E_FBGA96
B B
SDRAM RESET PIN

+1.35V_DDR
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1
1 1 1 1 1 1 1 1 @
1

1
CD58

CD59

CD60

CD61

CD62

CD63

CD64

CD65

CD119

CD120

CD121

CD122

+ CD66
A 330U_B2_2VM_R15M A
2

2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P14-DDRIII Channel_B Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 14 of 49
5 4 3 2 1
 5 4 3 2 1

follow INTEL PDG

CD68 1 2 0.047U_0402_16V4Z

CD69 1 2 0.047U_0402_16V4Z
+VREFCA

CD70 1 2 0.047U_0402_16V4Z
D D
CD71 1 2 0.047U_0402_16V4Z
+VREFDQ_B

PLACE THESE CAPS

UD9 UD10
NEAR TO RESPECTIVE DRAM
+VREFCA M8 E3 DDR_B_D39 +VREFCA M8 E3 DDR_B_D48
H1 VREFCA DQL0 F7 DDR_B_D33 H1 VREFCA DQL0 F7 DDR_B_D52
+VREFDQ_B VREFDQ DQL1 +VREFDQ_B VREFDQ DQL1
F2 DDR_B_D38 F2 DDR_B_D50
DDR_B_MA0 N3 DQL2 F8 DDR_B_D37 DDR_B_MA0 N3 DQL2 F8 DDR_B_D55
DDR_B_MA1 P7 A0 DQL3 H3 DDR_B_D34 DDR_B_MA1 P7 A0 DQL3 H3 DDR_B_D53
DDR_B_MA2 P3 A1 DQL4 H8 DDR_B_D32 DDR_B_MA2 P3 A1 DQL4 H8 DDR_B_D51
14,6 DDR_B_DQS#[0..7] A2 DQL5 A2 DQL5
DDR_B_MA3 N2 G2 DDR_B_D35 DDR_B_MA3 N2 G2 DDR_B_D54
DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D36 DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D49
14,6 DDR_B_DQS[0..7] A4 DQL7 A4 DQL7
DDR_B_MA5 P2 DDR_B_MA5 P2
DDR_B_MA6 R8 A5 DDR_B_MA6 R8 A5
14,6 DDR_B_D[0..63] A6 A6
DDR_B_MA7 R2 D7 DDR_B_D45 DDR_B_MA7 R2 D7 DDR_B_D60
DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D47 DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D62
14,16,6 DDR_B_MA[0..15] A8 DQU1 A8 DQU1
DDR_B_MA9 R3 C8 DDR_B_D44 DDR_B_MA9 R3 C8 DDR_B_D61
DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D42 DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D63
DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D40 DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D57
DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D46 DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D58
All VREF traces should
DDR_B_MA13 T3 A12/BC# DQU5 B8 DDR_B_D41 DDR_B_MA13 T3 A12/BC# DQU5 B8 DDR_B_D56
have 10 mil trace width A13 DQU6 A13 DQU6
DDR_B_MA14 T7 A3 DDR_B_D43 DDR_B_MA14 T7 A3 DDR_B_D59
DDR_B_MA15 M7 A14 DQU7 DDR_B_MA15 M7 A14 DQU7
A15/NC A15/NC

DDR_B_BS0 M2 B2 DDR_B_BS0 M2 B2
14,16,6 DDR_B_BS0 BA0 VDD +1.35V_DDR BA0 VDD +1.35V_DDR
DDR_B_BS1 N8 D9 DDR_B_BS1 N8 D9
14,16,6 DDR_B_BS1 BA1 VDD BA1 VDD
DDR_B_BS2 M3 G7 DDR_B_BS2 M3 G7
14,16,6 DDR_B_BS2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
M_CLK_B_DDR0 J7 VDD N9 M_CLK_B_DDR0 J7 VDD N9
14,16,6 M_CLK_B_DDR0 CK VDD CK VDD
M_CLK_B_DDR#0 K7 R1 M_CLK_B_DDR#0 K7 R1
14,16,6 M_CLK_B_DDR#0 CK# VDD R9 CK# VDD R9
VDD VDD
C C
DDR_B_CKE0 K9 DDR_B_CKE0 K9
14,16,6 DDR_B_CKE0 CKE0 CKE0
DDR_B_CKE1 J9 A1 DDR_B_CKE1 J9 A1
14,16,6 DDR_B_CKE1 CKE1/NC VDDQ CKE1/NC VDDQ
M_ODT2 K1 A8 M_ODT2 K1 A8
14,16 M_ODT2 J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
DDR_B_CS0# L2 ODT1/NC VDDQ C9 DDR_B_CS0# L2 ODT1/NC VDDQ C9
14,16,6 DDR_B_CS0# L1 CS0# VDDQ D2 L1 CS0# VDDQ D2
DDR_B_CS1# DDR_B_CS1#
14,16,6 DDR_B_CS1# CS1#/NC VDDQ CS1#/NC VDDQ
E9 E9
VDDQ F1 VDDQ F1
DDR_B_RAS# J3 VDDQ H2 DDR_B_RAS# J3 VDDQ H2
14,16,6 DDR_B_RAS# RAS# VDDQ RAS# VDDQ
DDR_B_CAS# K3 H9 DDR_B_CAS# K3 H9
14,16,6 DDR_B_CAS# L3 CAS# VDDQ L3 CAS# VDDQ
DDR_B_WE# DDR_B_WE#
14,16,6 DDR_B_WE# WE# WE#
A9 A9
DDR_B_DQS4 F3 VSS B3 DDR_B_DQS6 F3 VSS B3
DDR_B_DQS5 C7 DQSL VSS E1 DDR_B_DQS7 C7 DQSL VSS E1
DQSU VSS G8 DQSU VSS G8
VSS J2 VSS J2
DDR_B_DQS#4 G3 VSS J8 DDR_B_DQS#6 G3 VSS J8
DDR_B_DQS#5 B7 DQSL# VSS M1 DDR_B_DQS#7 B7 DQSL# VSS M1
DQSU# VSS M9 DQSU# VSS M9
VSS P1 VSS P1
E7 VSS P9 E7 VSS P9
D3 DML VSS T1 D3 DML VSS T1
DMU VSS T9 DMU VSS T9
VSS VSS

12,13,14,5 DDR3_DRAMRST# DDR3_DRAMRST# T2 B1 DDR3_DRAMRST# T2 B1

RESET# VSSQ RESET# VSSQ
0.1U_0402_25V6K~D

B9 B9
VSSQ D1 VSSQ D1
@ VSSQ D8 VSSQ D8
1 VSSQ VSSQ
CD72

RD11 2 1 240_0402_1% L8 E2 RD12 2 1 240_0402_1% L8 E2

ZQ0 VSSQ E8 ZQ0 VSSQ E8
RD85 2 1 240_0402_1% L9 VSSQ F9 RD86 2 1 240_0402_1% L9 VSSQ F9
2 ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
B B
CAD NOTE: SDRAM DDR3L SDRAM DDR3L
PLACE THE CAP NEAR TO MT41K256M16HA-125M:E_FBGA96 MT41K256M16HA-125M:E_FBGA96
SDRAM RESET PIN

+1.35V_DDR
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

1 1 1 1 1 1 1 1
1

1
CD81

CD82

CD83

CD84

CD85

CD86

CD87

CD88

CD123

CD124

CD125

CD126
2

2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P15-DDRIII Channel_B Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 15 of 49
5 4 3 2 1
 5 4 3 2 1

+1.35V_DDR

M3 M1

1
+VREFCA
RD13
1.8K_0402_1%

.1U_0402_16V7K~D
2
RD14 1
D D
1 2
6 V_DDR_REF_CA +VREFCA

CD90
1
2.7_0402_1%
CD89 2
0.022U_0402_16V7K~D

1
2
RD15
1.8K_0402_1%

1
RD16

2
24.9_0402_1%
All VREF traces should
have 10 mil trace width

2
+1.35V_DDR +1.35V_DDR

M3 M1 M3 M1
1

1
RD17 RD18
1.8K_0402_1% 1.8K_0402_1%
2

2
RD19 RD20
1 2 1 2
6 V_DDR_REFA_R +VREFDQ_A 6 V_DDR_REFB_R +VREFDQ_B

1 4.99_0402_1%~D 1 4.99_0402_1%~D

CD91 CD92

1
1

0.022U_0402_16V7K~D 0.022U_0402_16V7K~D
2 RD21 2 RD22
C 1.8K_0402_1% 1.8K_0402_1% C

1
1

RD24

2
2

RD23 24.9_0402_1%
24.9_0402_1%

2
+0.675VS +0.675VS
2

DDR_A_MA12 RD25 1 2 34.8_0402_1%~D DDR_B_MA12 RD26 1 2 34.8_0402_1%~D

DDR_A_MA15 RD27 1 2 34.8_0402_1%~D DDR_B_MA15 RD28 1 2 34.8_0402_1%~D
DDR_A_MA0 RD29 1 2 34.8_0402_1%~D DDR_B_MA0 RD30 1 2 34.8_0402_1%~D
DDR_A_MA10 RD31 1 2 34.8_0402_1%~D DDR_B_MA10 RD32 1 2 34.8_0402_1%~D

DDR_A_MA4 RD33 1 2 34.8_0402_1%~D DDR_B_MA14 RD34 1 2 34.8_0402_1%~D

DDR_A_MA2 RD35 1 2 34.8_0402_1%~D DDR_B_MA6 RD36 1 2 34.8_0402_1%~D
DDR_A_MA1 RD37 1 2 34.8_0402_1%~D DDR_B_MA4 RD38 1 2 34.8_0402_1%~D
DDR_A_MA6 RD39 1 2 34.8_0402_1%~D DDR_B_MA2 RD40 1 2 34.8_0402_1%~D
12,13,6 DDR_A_MA[0..15]

DDR_A_MA3 RD41 1 2 34.8_0402_1%~D DDR_B_MA8 RD42 1 2 34.8_0402_1%~D

14,15,6 DDR_B_MA[0..15]
DDR_A_MA9 1 2 DDR_B_MA1 1 2
http://eloy-motherboards.blogspot.com DDR_A_MA11
DDR_A_MA5
RD43
RD45
RD47
1
1
2
2
34.8_0402_1%~D
34.8_0402_1%~D
34.8_0402_1%~D
DDR_B_MA13
DDR_B_MA7
RD44
RD46
RD48
1
1
2
2
34.8_0402_1%~D
34.8_0402_1%~D
34.8_0402_1%~D

DDR_A_MA14 RD49 1 2 34.8_0402_1%~D DDR_B_MA3 RD50 1 2 34.8_0402_1%~D

+0.675VS DDR_A_MA7 RD51 1 2 34.8_0402_1%~D DDR_B_MA9 RD52 1 2 34.8_0402_1%~D
B B
DDR_A_MA8 RD53 1 2 34.8_0402_1%~D DDR_B_MA11 RD54 1 2 34.8_0402_1%~D
DDR_A_MA13 RD55 1 2 34.8_0402_1%~D DDR_B_MA5 RD56 1 2 34.8_0402_1%~D
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

1 1 1 1 1 1
1
CD93

CD96

CD97

CD98
CD94

CD95

CD101

RD57 1 2 34.8_0402_1%~D RD58 1 2 34.8_0402_1%~D

12,13,6 DDR_A_CKE0 14,15,6 DDR_B_CKE0
12,13,6 DDR_A_RAS# RD59 1 2 34.8_0402_1%~D 14,15,6 DDR_B_CS0# RD60 1 2 34.8_0402_1%~D
RD61 1 2 34.8_0402_1%~D RD62 1 2 34.8_0402_1%~D
12,13,6 DDR_A_CS0# 14,15,6 DDR_B_CAS#
2

2 2 2 2 2 2 RD63 1 2 34.8_0402_1%~D RD64 1 2 34.8_0402_1%~D

12,13,6 DDR_A_CAS# 14,15,6 DDR_B_RAS#

12,13,6 DDR_A_WE# RD65 1 2 34.8_0402_1%~D 14,15,6 DDR_B_BS1 RD66 1 2 34.8_0402_1%~D

RD67 1 2 34.8_0402_1%~D RD68 1 2 34.8_0402_1%~D
12,13,6 DDR_A_BS0 14,15,6 DDR_B_BS2
RD69 1 2 34.8_0402_1%~D RD70 1 2 34.8_0402_1%~D
12,13,6 DDR_A_BS2 14,15,6 DDR_B_BS0
12,13,6 DDR_A_BS1 RD71 1 2 34.8_0402_1%~D 14,15,6 DDR_B_WE# RD72 1 2 34.8_0402_1%~D

+0.675VS
RD87 1 2 34.8_0402_1%~D RD89 1 2 34.8_0402_1%~D
12,13,6 DDR_A_CKE1 14,15,6 DDR_B_CKE1
12,13,6 DDR_A_CS1# RD88 1 2 34.8_0402_1%~D 14,15,6 DDR_B_CS1# RD90 1 2 34.8_0402_1%~D
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1 1 1
1
CD103

CD105

+1.35V_DDR +1.35V_DDR
CD104

CD110
CD102

CD106

CD107

2 2 2 2 2 2 RD73 1 2 30_0402_1%~D RD74 1 2 30_0402_1%~D

12,13 M_ODT0 14,15 M_ODT2

+0.675VS +0.675VS

RD75 1 2 26.1_0402_1%~D RD76 1 2 26.1_0402_1%~D

12,13,6 M_CLK_A_DDR0 14,15,6 M_CLK_B_DDR0
A A

12,13,6 M_CLK_A_DDR#0 RD77 1 2 26.1_0402_1%~D 14,15,6 M_CLK_B_DDR#0 RD78 1 2 26.1_0402_1%~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P16-DDRIII Vref & Termination
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 16 of 49
5 4 3 2 1
 5 4 3 2 1

U663 200ps of XDP

0806-16 NC the XDP control circuit for XB phase +3V_PCH

1
@ CH1236 @
0.1U_0402_25V6K~D
2 U663

14
VCC
D D
CPU_XDP_TRST# 2 3 XDP_TRST#
5 CPU_XDP_TRST# 1A 1B

1
1OE
5 6 XDP_TDO
5 CPU_XDP_TDO 2A 2B

4
2OE
9 8 XDP_TDI_SWITCH
5 CPU_XDP_TDI 3A 3B

10
3OE
12 11 XDP_TMS
5 CPU_XDP_TMS 4A 4B

CPU_PATH_EN_G 13 7
+3V_PCH 4OE GND
15
GND PAD

5
U697 @
+3V_PCH 1

P
32,8 1.05VS_PG IN1 4 CPU_PATH_EN_G
@ R1324 1 2 10K_0402_5%~D CPU_PATH_EN 2 O
IN2

G
@ R1325 1 2 10K_0402_5%~D SN74AHC1G08DCKR_SC70-5
5 CPU_XDP_TCK
CPU_XDP_TCK RS5 @ RH446 1 2 0_0402_5% XDP_TCK0

3
7 PCH_JTAG_TRST# @ RH370 1 2 0_0402_5% CPU_XDP_TRST#

@ RH371 1 2 0_0402_5% XDP_TDI

7 PCH_JTAG_TDI
C C
@ RH372 1 2 0_0402_5% XDP_TMS
Resistors Resistors 7 PCH_JTAG_TMS
Topolog Description Be st Use for Stuffed ufStuffed
7 PCH_JTAG_TCK
J1D @ RH373 1 2 0_0402_5% XDP_TCK1 Stuffed : Dual TCK
Default Setting: Dual In this topology, the - Run control oper. R1, R2, J1s, J2s,
TCK S can Chains CPU JTAG chain will be - ME/Sx debug J1d, J2d, J3s J1D, J1S
<200ps of the XDP J1S @ RH411 1 2 0_0402_5% XDP_TCK0
Stuffed : Singel TCK
(also known as controlled by TCK0 and J3d, J4d,
"Shared JTAG" in TCK1 will control R3, R4, R5 Stub<200ps
other docum ent) the PCH JTAG chain. J2D @ RH374 1 2 0_0402_5% XDP_TCK0
7 PCH_JTAG_JTAGX

J2D, J2S
In th is topolog y, PCH -B oundary Scan/ J1s , J2s , R1, J1d, J2d, <200ps of the XDP J2S @ RH412 1 2 0_0402_5% XDP_TDO
Single TCK scan chain TDI- TDO and CPU TDI-TDO Manufacturing est J3s , J3d , J4d
(also known as "Com m on Stub <200ps
will be chained to form R2, R3, R4,
JTAG" in other docum one JTAG scan chain R5 J3D
PCH_JTAG_TDO @ RH369 1 2 0_0402_5% XDP_TDO
ent) controlled by TCK0
7 PCH_JTAG_TDO

J3D, J3S, R3
<200ps of the XDP J3S @ RH413 1 2 0_0402_5% XDP_TDI_SWITCH

0806-18 NC the JDebug connector for XB phase Stub <200ps

+1.05VA

XDP_TDI J4D @ RH414 1 2 0_0402_5% XDP_TDI_SWITCH

JDebug R7 J4D
1 @
24,33,7 LPC_FRAME# 1 +3VS
24,33,7 LPC_AD3 2
3 2
XDP_TDO 51_0402_5% 2 1 RH38 <200ps of the XDP
24,33,7 LPC_AD2 3
24,33,7 LPC_AD1 4 XDP_DBRESET# @ RH367 1 2 1K_0402_5%
B
5 4 B
24,33,7 LPC_AD0 5
6 SYS_PWROK_XDP @ R1311 1 2 3K_0402_5%~D
17,23,24,25,33,8 PLT_RST# 6
7 CLK_LPC_DEBUG 7
8 7
9 8
+3VS 9 +1.05VS
10
11 10 13 @ RH51 JXDP
33 EC_TX 11 GND
12 14 1 2 +1.05VS_XDP 1 2
33 EC_RX 12 GND 3 GND0 GND1 4
1 5 XDP_PREQ# OBSFN_A0 OBSFN_C0 CFG17 11
ACES_50281-0120N-001 0_0402_5% 5 6
5 XDP_PRDY# OBSFN_A1 OBSFN_C1 CFG16 11
CONN@ @ CH1 7 8
0.1U_0402_25V6K~D 9 GND2 GND3 10
2 11 CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 11
11 12
11 CFG1 13 OBSDATA_A1 OBSDATA_C1 14 CFG9 11
0802-12 15 GND4 GND5 16
11 CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 11
17 18
11 CFG3 19 OBSDATA_A3 OBSDATA_C3 20 CFG11 11
21 GND6 GND7 22
5 XDP_BPM0# 23 OBSFN_B0 OBSFN_D0 24 CFG19 11
+3VALW +3V_PCH 5 XDP_BPM1# OBSFN_B1 OBSFN_D1 CFG18 11
JAPS 25 26
20 27 GND8 GND9 28
19 GND 11 CFG4 29 OBSDATA_B0 OBSDATA_D0 30 CFG12 11
GND 11 CFG5 OBSDATA_B1 OBSDATA_D1 CFG13 11
18 31 32
17 18 33 GND10 GND11 34
29,30,33,40,8 PM_SLP_S3# 17 11 CFG6 OBSDATA_B2 OBSDATA_D2 CFG14 11
16 35 36
16 11 CFG7 OBSDATA_B3 OBSDATA_D3 CFG15 11
15 37 38
33,8 PM_SLP_S5# 14 15 GND12 GND13
10,32 1.05VS_VCCST_PG @ R1180 1 2 1K_0402_5%~D XDP_PWRGD 39 40
33,42,8 PM_SLP_S4# 14 PWRGOOD/HOOK0 ITPCLK/HOOK4
13 17,20,33,8 PBTN_SW# @ RH21 1 2 0_0402_5% PCH_PWRBTN#_XDP 41 42
29,30,33,8 PM_SLP_A# 12 13 HOOK1 ITPCLK#/HOOK5
+3V_PCH 8 PBTN_OUT#_R @ RH444 1 2 0_0402_5% 43 44 +1.05VS_XDP
11 12 45 VCC_OBS_AB VCC_OBS_CD 46 PLTRST1#_XDP @ RH363 1 2 1K_0402_5%
11 10 FIVE_EN HOOK2 RESET#/HOOK6 PLT_RST# 17,23,24,25,33,8
10 @ R1309 1 2 0_0402_5% SYS_PWROK_XDP 47 48 XDP_DBRESET# @ RH451 1 2 0_0402_5%
7 PCH_RTCRST# 9 10 32,8 SYS_PWROK 49 HOOK3 DBR#/HOOK7 50 PM_SYS_RESET# 17,8
9 GND14 GND15 1
8 51 52 XDP_TDO
17,20,33,8 PBTN_SW#
7 8 0802-12 7 PCH_SMBDATA
53 SDA TD0 54 XDP_TRST# C1237 @
7 7 PCH_SMBCLK SCL TRST#
17,8 PM_SYS_RESET# 6 XDP_TCK1 55 56 XDP_TDI 0.1U_0402_10V7K~D
5 6 XDP_TCK0 57 TCK1 TDI 58 XDP_TMS 2
4 5 59 TCK0 TMS 60 XDP_PIN60
33,41,8 PM_SLP_S0# 4 GND16 GND17
A 3 SYS_PWROK_XDP A
2 3 SAMTE_BSH-030-01-L-D-A
1 2 CONN@ @
1 1 R1198
E-T_6705K-Y18N-00L C1282 @ XDP_PIN60 1 2 CFG3
CONN@
2
0.1U_0402_10V7K~D TCK0, TCK1 and TMS stub <200ps 1K_0402_5%~D

Security Classification Compal Secret Data Compal Electronics, Inc.

0806-18 NC the JAPS connector for XB phase Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P17-XDP,APS,Debug CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 17 of 49
5 4 3 2 1
 5 4 3 2 1

+5VS +HDMI_5V_OUT
+5VS D110
D111 RV28 1 2 2.2K_0402_5%~D HDMI_CLK 3 NC FV2 W=40mils
D D
DB2J31400L_SOD323-2 2 1 +HDMI_5V 1 2
2 1 RV29 1 2 2.2K_0402_5%~D HDMI_DAT

1U_0603_25V6K

CV41
1 SMD1812P110TF 1.1A 8V 1
@ BAT1000-7-F_SOT23-3~D
CV40
1U_0603_25V6K
2 2
+1.5VS +3VS

0.01U_0402_16V7K~D

0.1U_0402_10V7K~D

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

0.1U_0402_10V7K~D

0.01U_0402_16V7K~D
CV31

CV42

CV43

CV44
1 1 1 1 1 1

CV32

CV39
2 2 2 2 2 2 close to connector
+3VS +1.5VS

HDMI_D2_P 3
L64 DLW21SN900HQ2L_0805_4P~D
4 HDMI_D2_P_R
HDMI conn
3 4

11
37

12
40
20
31
19
U722 HDMI_D2_N 2 1 HDMI_D2_N_R
2 1 +HDMI_5V_OUT

VDD33
VDD33

VDDRX
VDDRX
VDDTX
VDDTX
VDDTA
CV27 1 2 0.1U_0402_10V7K~D PCH_DDI2_P0_C 6
5 PCH_DDI2_P0 IN_D0p
CV30 1 2 0.1U_0402_10V7K~D PCH_DDI2_N0_C 7 HDMI_EMI@ JHDMI
5 PCH_DDI2_N0 IN_D0n
5 PCH_DDI2_P1 CV28 1 2 0.1U_0402_10V7K~D PCH_DDI2_P1_C 4 HDMI_HPD 19
CV33 1 2 0.1U_0402_10V7K~D PCH_DDI2_N1_C 5 IN_D1p 18 HP_DET
5 PCH_DDI2_N1 IN_D1n +5V
5 PCH_DDI2_P2 CV29 1 2 0.1U_0402_10V7K~D PCH_DDI2_P2_C 1 17
CV34 1 2 0.1U_0402_10V7K~D PCH_DDI2_N2_C 2 IN_D2p HDMI_DAT 16 DDC/CEC_GND
5 PCH_DDI2_N2 IN_D2n SDA
CV36 1 2 0.1U_0402_10V7K~D PCH_DDI2_P3_C 9 L65 DLW21SN900HQ2L_0805_4P~D HDMI_CLK 15
5 PCH_DDI2_P3 IN_CKp SCL
C 5 PCH_DDI2_N3 CV35 1 2 0.1U_0402_10V7K~D PCH_DDI2_N3_C 10 HDMI_D1_P 3 4 HDMI_D1_P_R HDMI_Reserved 14 23 C
IN_CKn 25 HDMI_D2_P 3 4 HDMI_CEC 13 Reserved GND4 22
36 OUT_D0p 24 HDMI_D2_N HDMI_CK_N_R 12 CEC GND3 21
PD# OUT_D0n 27 HDMI_D1_P HDMI_D1_N 2 1 HDMI_D1_N_R 11 CK- GND2 20
HDMI_I2C_CTL_EN 8 OUT_D1p 26 HDMI_D1_N 2 1 HDMI_CK_P_R 10 CK_shield GND1
I2C_CTL_EN OUT_D1n 30 HDMI_D0_P HDMI_D0_N_R 9 CK+
OUT_D2p 29 HDMI_D0_N 8 D0-
OUT_D2n HDMI_EMI@ D0_shield
HDMI_DCIN_EN 13 22 HDMI_CK_P HDMI_D0_P_R 7
HDMI_DDCBUF 14 DCIN_EN/SCL_CTL OUT_CKp 21 HDMI_CK_N HDMI_D1_N_R 6 D0+
DDCBUF/SDA_CTL OUT_CKn 5 D1-
ISET 34 HDMI_D1_P_R 4 D1_shield
ISET L66 DLW21SN900HQ2L_0805_4P~D HDMI_D2_N_R 3 D1+
HDMI_D0_P 3 4 HDMI_D0_P_R 2 D2-
38 32 HDMI_CLK 3 4 HDMI_D2_P_R 1 D2_shield
5 PCH_HDMI_CLK SCL_SRC SCL_SNK D2+
39 33 HDMI_DAT
5 PCH_HDMI_DAT SDA_SRC SDA_SNK HDMI_D0_N 2 1 HDMI_D0_N_R ACON_HMR2G-AK120C
2 1 CONN@
HDMI_CFG 23
CFG 28 HDMI_HPD
HPD_SNK HDMI_EMI@
HDMI_EQ 17 PT Change to LTCX0023H00
HDMI_PRE 16 EQ/I2C_ADDR0
PRE/I2C_ADDR1 Footprint: ACON_HMR2G-AK120C_19P-T
L67 DLW21SN900HQ2L_0805_4P~D
3 HDMI_CK_P 3 4 HDMI_CK_P_R
5 PCH_HDMI_HPD HPD_SRC 3 4
+3VS
GND_PAD

HDMI_REXT 18 HDMI_CK_N 2 1 HDMI_CK_N_R

REXT 2 1
GND
GND

RV16 2 1 10K_0402_5%~D HDMI_DDCBUF

@ RV17 2 1 10K_0402_5%~D HDMI_DCIN_EN HDMI_EMI@
@ RV18 2 1 10K_0402_5%~D HDMI_EQ PS8401ATQFN40GTR-A4_TQFN40_5X5 For EMI Reserve
15
35
41

@ RV19 2 1 10K_0402_5%~D HDMI_I2C_CTL_EN

RV20 2 1 10K_0402_5%~D HDMI_CFG HDMI_EMI@
RV21 2 1 10K_0402_5%~D HDMI_PRE CV768 1 2 0.1U_0402_25V6K~D HDMI_HPD
@ RV32 2 1 10K_0402_5%~D ISET HDMI_EMI@
CV795 1 2 0.1U_0402_25V6K~D HDMI_Reserved
HDMI_EMI@
B B
CV796 1 2 0.1U_0402_25V6K~D HDMI_CEC

@ RV22 2 1 10K_0402_5%~D HDMI_DDCBUF close to JHDMI

@ RV24 2 1 10K_0402_5%~D HDMI_EQ

@ RV26 2 1 10K_0402_5%~D HDMI_CFG

RV27 2 1 10K_0402_5%~D HDMI_PRE
@ RV30 1 2 20K_0402_5%~D HDMI_HPD
RV31 1 2 5.11K_0402_1% HDMI_REXT DV4 @HDMI_ESD@ DV5 @HDMI_ESD@
@ RV33 2 1 10K_0402_5%~D ISET HDMI_CK_N_R 1 1 10 9 HDMI_CK_N_R HDMI_D1_P_R 1 1 10 9 HDMI_D1_P_R

HDMI_CK_P_R 2 2 9 8 HDMI_CK_P_R HDMI_D1_N_R 2 2 9 8 HDMI_D1_N_R

HDMI_D0_N_R 4 4 7 7 HDMI_D0_N_R HDMI_D2_P_R 4 4 7 7 HDMI_D2_P_R

HDMI_D0_P_R 5 5 6 6 HDMI_D0_P_R HDMI_D2_N_R 5 5 6 6 HDMI_D2_N_R

3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P18-HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 18 of 49
5 4 3 2 1
 5 4 3 2 1

eDP BackLight Power B+ +INV_PWR_SRC +LCDVDD

eDP Conn eDP_TXN_P0_CONN
eDP_TXP_P0_CONN
1
2
JLVDS2
1
@EMI@ R1004 1 2 0_0402_5%~D 3 2
@ R531 1 2 0_0603_5%~D eDP_TXN_P1_CONN 4 3
eDP_TXP_P1_CONN 5 4
5

.1U_0402_16V7K~D

10U_0603_6.3V6M~D
ML55 EMI@ 6
4 3 USB20_P4_CONN eDP_TXN_P2_CONN 7 6
9 USB20_P4 4 3 1 1 7

C1145

C1143
Q70 eDP_TXP_P2_CONN 8
SI3457CDV-T1-GE3_TSOP6~D 9 8
60mil

D
6 1 2 USB20_N4_CONN eDP_TXN_P3_CONN 10 9

S
9 USB20_N4 1 2 2 2 10
4 5 eDP_TXP_P3_CONN 11
2 60mil DLW21HN900SQ2L_4P 12 11
12

1
1 eDP_AUXP_CONN 13
13

G
@EMI@ R1005 1 2 0_0402_5%~D eDP_AUXN_CONN 14
14

1
D D
R535 Vgs(th) = -1 ~ -3, max 20V 1 15

3
C613 1M_0402_5%~D 16 15
+LCDVDD 16
0.1U_0402_25V6K~D C612 17

2
0.1U_0402_25V6K~D 18 17
2 EMI@ R1006 1 2 0_0402_5%~D 19 18
PWR_SRC_ON 20 19
5 eDP_HPD 20
MLK IC : 21
21

1
@EMI@ ML56 DISPOFF# 22
R1161 2 1 220K_0402_5%~D +LCDVDD_R R536 113m ohm C1061 1 2 eDP_TXN_P1_C 4 3 eDP_TXN_P1_CONN INV_PWM_R 23 22
5 eDP_TXN_P1 23
100K_0402_5%~D 550m A 24
24
0.1U_0402_10V7K~D 25
+INV_PWR_SRC 25
5 eDP_TXP_P1 C1063 1 2 eDP_TXP_P1_C 1 2 eDP_TXP_P1_CONN 26

2
D105 For T-C0M 27 26
2 0.1U_0402_10V7K~D DLW21SN670HQ2L_4P~D 28 27
29,30,5 PCH_ENVDD 33 EC_SMB_CK4 28

1
D 29
33 EC_SMB_DA4

3
1 +LCDVDD_R 2
G
Q71
DII-DMN65D8LW-7~D Discharge Circuit EMI@ R1007 1 2 0_0402_5%~D 30
31
32
29
30
31
29,30,33 EC_ENVDD 3 S
+INV_PWR_SRC EMI@ R1008 1 2 0_0402_5%~D Sensor_I2C_SCL 33 32
19,24 Sensor_I2C_SCL 33
Sensor_I2C_SDA 34
19,24 Sensor_I2C_SDA 34
BAT54CW_SOT323-3 GYRO_DRDY 35
24 GYRO_DRDY 35

1
+LCDVDD @ @EMI@ ML57 GYRO_INT# 36
24 GYRO_INT# 36
U708 @ R541 5 eDP_TXN_P0 C1060 1 2 eDP_TXN_P0_C 4 3 eDP_TXN_P0_CONN MAG_DRDY 37
24 MAG_DRDY 38 37
820_0805_1% ACCEL_INT1
24 ACCEL_INT1 38
1 5 0.1U_0402_10V7K~D ACCEL_INT2 39
NC VCC 24 ACCEL_INT2 39
5 eDP_TXP_P0 C1062 1 2 eDP_TXP_P0_C 1 2 eDP_TXP_P0_CONN +3VNS_PWR
40

2
41 40
33 Win8_INT# 41
+LCDVDD_R 2 0.1U_0402_10V7K~D DLW21SN670HQ2L_4P~D 42
IN A 33 LCD_TEST 1 2 0_0402_5% 43 42
@ R1016 EC_SMB_CK1_R
33,35,36 EC_SMB_CK1 43

1
D +3VS EMI@ R1009 1 2 0_0402_5%~D @ R1017 1 2 0_0402_5% EC_SMB_DA1_R 44
33,35,36 EC_SMB_DA1 44
3 4 2 @ Q305 45 51
GND OUT Y +3VALW 45 GND
G DII-DMN65D8LW-7~D 46 52
46 GND

2
S @ I2C1_SCK_TS 47 53

3
SN74AUP1G04DCKR_SOT23-5~D R1033 EMI@ R1010 1 2 0_0402_5%~D I2C1_SDA_TS 48 47 GND 54
100K_0402_5%~D TS_RST#_R 49 48 GND
50 49
+3VS_TS 50
@EMI@ ML58

1
C 5 eDP_AUXP C1064 1 2 eDP_AUXP_C 4 3 eDP_AUXP_CONN STARC_300E50-0011RA-G3 C
SP01001FT00
0.1U_0402_10V7K~D CONN@
5 eDP_AUXN C1065 1 2 eDP_AUXN_C 1 2 eDP_AUXN_CONN

BackLight PWM Control

2
0.1U_0402_10V7K~D @ DLW21SN670HQ2L_4P~D
R1034
100K_0402_5%~D EMI@ R1011 1 2 0_0402_5%~D

D72

1
5 ENBKL 2

1 DISPOFF# JLVDS1
EMI@ R1013 1 2 0_0402_5%~D
+3VS_CAM
1
1
1

3 2
33 BKOFF# 2
R540 USB20_P4_CONN 3
@EMI@ ML59 USB20_N4_CONN 4 3
220K_0402_5%~D 4
BAT54CW_SOT323-3 5 eDP_TXN_P2 C1066 1 2 eDP_TXN_P2_C 4 3 eDP_TXN_P2_CONN 5
6 5
2

0.1U_0402_10V7K~D 7 6
+3VS 7
5 eDP_TXP_P2 C1067 1 2 eDP_TXP_P2_C 1 2 eDP_TXP_P2_CONN DMIC_DAT 8
22 DMIC_DAT DMIC_CLK R1342 1 2 100_0402_5%~D DMIC_CLK_R 9 8
0.1U_0402_10V7K~D DLW21SN670HQ2L_4P~D 22 DMIC_CLK ALS_SMBCLK 10 9
D106 ALS_SMBDATA 11 10
2 EMI@ R1012 1 2 0_0402_5%~D ALS_INT# 12 11
13 12
1 INV_PWM_R 14 13
15 14
22 Array_MIC_DAT 15
1

3 1 EMI@ R1015 1 2 0_0402_5%~D 16

5 PCH_INV_PWM 22 Array_MIC_CLK 16
R545 17
+3VS 17
100K_0402_5%~D @MC1151
@ MC1151 18
BAT54CW_SOT323-3 680P_0402_50V7K~D @EMI@ ML60 19 18
2 28 MOTOR_P1 19
5 eDP_TXN_P3 C1068 1 2 eDP_TXN_P3_C 1 2 eDP_TXN_P3_CONN 20
28 MOTOR_N1
2

21 20
0.1U_0402_10V7K~D 22 G1
C1069 1 2 4 3 23 G2
PT Change to 4.7K (short term solution) 5 eDP_TXP_P3 eDP_TXP_P3_C eDP_TXP_P3_CONN
G3
24
ST:100K 0.1U_0402_10V7K~D DLW21SN670HQ2L_4P~D G4
B B
ACES_50406-02071-001
EMI@ R1014 1 2 0_0402_5%~D CONN@

Array_MIC_DAT Array_MIC_CLK DMIC_DAT DMIC_CLK_R

1
@EMI@ @EMI@ @EMI@ EMI@
MC1211 MC1212 MC1210 MC1133
10P_0402_50V8J~D 10P_0402_50V8J~D 10P_0402_50V8J~D 10P_0402_50V8J~D

2
MD50 MD90
DMIC_CLK 6 1 USB20_N4_CONN 6 1 I2C1_SCK_TS
V I/O V I/O V I/O V I/O
5 2 @ R1376 2 1 100K_0402_5%~D TS_RST# 5 2
+3VS V BUS Ground +3VS_TS V BUS Ground
DMIC_DAT 4 3 USB20_P4_CONN 4 3 I2C1_SDA_TS
V I/O V I/O V I/O V I/O
IP4223CZ6_SO6~D IP4223CZ6_SO6~D Closed to JLVDS2 0802-12
@ RA9 1 2 0_0402_5%
22 DMIC_CLK_SW DMIC_CLK_CODEC 21
@ RA10 1 2 0_0402_5%
ALC3661
22 DMIC_DAT_SW DMIC_DAT_CODEC 21
@ RA5 1 2 0_0402_5%~D
DMIC_CLK_DSP 20
@ RA6 1 2 0_0402_5%~D
ALC5505
+3VS_TP +3VS_TS DMIC_DAT_DSP 20

+3VS_TS I2C1_SCK RH364 1 2 4.7K_0402_5%~D I2C1_SCK @ RH436 1 2 4.7K_0402_5%~D

Default control from EC connect to PCH<->EC SMBus
I2C1_SDA RH365 1 2 4.7K_0402_5%~D I2C1_SDA @ RH437 1 2 4.7K_0402_5%~D
0802-12
0802-12 For ALS Sensor
1

@ R1116 2 1 0_0402_5%~D ALS_INT#

@ I2C1_SCK @ R1257 1 2 0_0402_5% 24 ALS_INT#_HUB
8 I2C1_SCK I2C1_SCK_TP 32
R1385 Touch PAD 28,32,33,7 PCH_SMLCLK @ R983 2 1 0_0402_5% ALS_SMBCLK
A 100K_0402_5%~D 8 I2C1_SDA I2C1_SDA @ R1258 1 2 0_0402_5% To EC A
I2C1_SDA_TP 32
2

@ Q363 @ R984 2 1 0_0402_5% ALS_SMBDATA

G

28,32,33,7 PCH_SMLDATA
2

@ R1152 1 2 0_0402_5%~D I2C1_SCK_TS

1 3 TS_INT#_R @ R985 2 1 0_0402_5%~D
8 TS_INT# 19,24 Sensor_I2C_SCL
@ R1153 1 2 0_0402_5%~D I2C1_SDA_TS Touch Panel
D

To Sensor HUB 19,24 Sensor_I2C_SDA @ R986 2 1 0_0402_5%~D

DII-DMN65D8LW-7~D 9 USB20_N3 @ R1218 1 2 0_0402_5%

@ R1384 @ R1219 1 2 0_0402_5%

1 2
9 USB20_P3 0802-12
0_0402_5%~D
5 TS_RST#
@ R1227 1 2 0_0402_5% TS_RST#_R Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title
TS_INT#_R @ R1157 1 2 0_0402_5%~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P19-eDP/ Camera CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 19 of 49
5 4 3 2 1
 5 4 3 2 1

Volume Control Conn

Hinge angle detect Conn
JVOL
1 VOLUME_UP_SW#_C
1 2 VOLUME_DOWN_SW#_C JROT1
2 Pull-up resistor is on EC page (100K)
3 1 ROTATION_SW#_C
3 4 1 2
4 2

2
3 VOLUME_UP_SW#_C 1 2 VOLUME_UP_SW# VOLUME_UP_SW# 33

PJDLC05_SOT23-3
5 3 4
GND 6 4 R953
GND 1
5 1K_0402_5%~D
ACES_51522-00401-001 GND 6 C1123
GND

@ESD@ DA6
CONN@ 0.01U_0402_16V7K~D
ACES_51522-00401-001 2

D CONN@ D

1
Pull-up resistor is on EC page (100K)

VOLUME_DOWN_SW#_C 1 2 VOLUME_DOWN_SW#
PWR Conn VOLUME_DOWN_SW# 33
R955 1
JPWR1 1K_0402_5%~D
1
2
3
1
2
3
+5VALW
PBTN_SW#
PWR_LED#
PBTN_SW#
PWR_LED#
17,33,8
28
LID SW +3VALW 2
C1124
0.01U_0402_16V7K~D
4 BATT_LOW_LED#_C BATT_LOW_LED#_C 28
4 5
5 6
6

1
7 +3VALW
G1 8 @ R11
G2 U725 47K_0402_5%~D Pull-up resistor is on PCH (10K)
3

2
HB_A520620-SCHR22 YB8251ST23 TSOT-23 3P
PJDLC05_SOT23-3

PJDLC05_SOT23-3
CONN@

2
2 3 LID_SW_IN# ROTATION_SW#_C 1 2

GND
VDD VOUT LID_SW_IN# 33 ROTATION_SW# 33

1 R957 1

2
@ESD@ DA8

@ESD@ DA9
1K_0402_5%~D

1
C8 C9 C1125
0.1U_0402_10V7K~D 10P_0402_50V8J~D 0.01U_0402_16V7K~D

1
2 2
1

+1.2VS_DVDD
C C

+3VS_AUDIO
4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

Closed to UA1 Pin 16

1 1 1 1 1 1
+1.5VS_3.3VS_AUDIO
CA1

CA2

CA3

CA4

CA5

CA6

10U_0603_6.3V6M~D

0.1U_0402_10V7K~D
2 2 2 2 2 2 1 1
1

CA8

CA10
CA22
10U_0603_6.3V6M~D +1.2VS_DVDD +3VS_AUDIO 2 2
2 UA1

+1.2VS_DVDD 1 14
Closed to UA1 Pin 13 25 DVDD-12-I DVDD-33-SWR
+3VS_AUDIO LA1 +1.5VS_3.3VS_AUDIO 37 DVDD-12-I 16
1 2 DVDD-12-SWR DVDD-12-I DVDD-33-SWR-C 1.2_PGND +3VS_AUDIO
4.7UH_PG031B-4R7MS_1.1A_20% 42
DVDD-33-LDO-I
0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D

10U_0603_6.3V6M~D

9
DVDD-IO
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 1 1 32
MCLKO 29 I2S_BCLK_OUT
1 1 1 1 I2SCLKO

1
CA18

CA19

CA20

+1.2VS_DVDD 15 30
FB-SWR I2SCLRCKO I2S_SFRM_OUT 25
CA7

CA9

CA11

CA12

DVDD-12-SWR 13 31 R1261
2 2 2 DVDD-12-SWR I2SSDO0 I2S_SDO_OUT 25
2 2 2 2
43
ALC5505 I2SCLKI
38
39
I2S_CLK_IN
10K_0402_5%~D

DVDD_25 I2S_SFRM_IN

2
DDR_VREF 40 DVDD-25-LDO-O I2SLRCKI 41
DDR-VERF I2SSDI0 I2S_SDI_IN 25
17 DSP_PD#_R @ R1262 2 1 0_0402_5%~D
DSP-PD# DSP_PD# 33
1.2_PGND HDA_BITCLK_AUDIO 6 23 HDA_BITCLK_DSP
7 HDA_BITCLK_AUDIO BITCLK/I2SCLKI-2 BITCLK-V/MCLKI-2 HDA_BITCLK_DSP 21
7 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO 5 24 HDA_SDOUT_DSP
DVDD_25 RA1 1 2 33_0402_5%~D HDA_SDIN0_AUDIO 8 SDTA-OUT/I2SSDO0-2 SDATA-OUT-V/I2SSDO1 21 HDA_SDIN0_DSP HDA_SDOUT_DSP 21
7 HDA_SDIN0 SDATA-IN/I2SSDI0-2 VGPIO1/SDATA-IN-V/I2SSDI3 HDA_SDIN0_DSP 21
1 HDA_SYNC_AUDIO 10 19 HDA_SYNC_DSP
7 HDA_SYNC_AUDIO SYNC/I2SLRCLKI-2 SYNC-V/I2SSDO2 HDA_SYNC_DSP 21
1

7 HDA_RST_AUDIO# HDA_RST_AUDIO# 11 18 HDA_RST_DSP#

RESETB RESETB-V/I2SSDO3 HDA_RST_DSP# 21
10U_0603_6.3V6M~D

R1186 CA13
0.1U_0402_10V7K~D

1 1 20K_0402_1%~D 0.1U_0402_10V7K~D
B 2 B
45 7 TABLET_MODE_R T283TP@
VDMIC-CLK2/I2SSDI1 VGPIO0/TRST#
CA21

CA14

46 28
2

DDR_VREF VDMIC-DAT2/I2SSDI2 VGPIO2/TMS 4 VOLUME_DOWN_SW#_DSP @ R1263 2 1 0_0402_5%~D VOLUME_DOWN_SW#_C

2 2 VGPIO3/VOL-DN/TDI 20 VOLUME_UP_SW#_DSP @ R1264 2 1 0_0402_5%~D VOLUME_UP_SW#_C
1 VGPIO4/VOL-UP/TCLK
1

47 22
19 DMIC_CLK_DSP VDIMC-CLK1 VGPIO5/VOL-MUTE/TDO
R1187 CA15 48
19 DMIC_DAT_DSP VDMIC-DAT1
20K_0402_1%~D 0.1U_0402_10V7K~D
2 26
2 I2C-MASTER-SCL/I2C-SLAVE-SCL 27 I2C0_SCK_DSP 8
AUDIO_XTAL24_IN
I2C0_SDA_DSP 8
2

@ RA11 1 2 0_0402_5% AUDIO_XTAL24_OUT 3 XTAL-IN I2C-MASTER-SDA/I2C-SLAVE-SDA

@ RA12 1 2 0_0402_5% XTAL-OUT
@ RA13 1 2 0_0402_5% 33
12 CS-L 34
AUDIO_XTAL24_OUT 44 DVSS-SWR SCK 35
49 DVSS SI 36
YA1 DGND SO +3VS_AUDIO
24MHZ_12PF_7V24000020 1.2_PGND
1 3 AUDIO_XTAL24_IN ALC5505_QFN48_7X7~D VOLUME_DOWN_SW#_DSP R1265 2 1 10K_0402_5%~D
2 4 VOLUME_UP_SW#_DSP R1266 2 1 10K_0402_5%~D
1.2_PGND
1 1

CA16 CA17
2 18P_0402_50V8J~D 2 18P_0402_50V8J~D
MLK IC : I2S_BCLK_OUT @ R1372 2 1 0_0402_5%
I2S_CLK_IN @ R1373 2 1 0_0402_5%~D I2S_CLK 25
20m ohm I2S_SFRM_IN @ R1374 2 1 0_0402_5%~D
+3VS_AUDIO 230m A
U664
0802-12 Intel : HDA_BITCLK_AUDIO @ RA58 1 2 0_0402_5%~D HDA_BITCLK_DSP
1 14 @ R1318 1 2 0_0603_5% 165m ohm HDA_SDOUT_AUDIO @ RA59 1 2 0_0402_5%~D HDA_SDOUT_DSP
+5VALW +3VALW VIN1 VOUT1
2
VIN1 VOUT1
13 200m A HDA_SDIN0_AUDIO @ RA60 1 2 0_0402_5%~D HDA_SDIN0_DSP
HDA_SYNC_AUDIO @ RA61 1 2 0_0402_5%~D HDA_SYNC_DSP
AUDIO_PWREN 3 12 C1212 1 2 2200P_0402_25V7K~D HDA_RST_AUDIO# @ RA62 1 2 0_0402_5%~D HDA_RST_DSP#
29,30,8 AUDIO_PWREN ON1 CT1
1
4 11
+5VALW VBIAS GND +5VS_AUDIO
A C1213 MLK IC : A
0.1U_0402_10V7K~D 5 10 C1214 1 2 2200P_0402_25V7K~D
2 ON2 CT2 20m ohm
+5VALW
6
VIN2 VOUT2
9 570m A
7 8 @ R1125 1 2 0_0603_5% Intel :
VIN2 VOUT2
+3VS 15 33m ohm
GPAD
0802-12 1500m A
TPS22966DPUR_SON14_2X3
R1182 2 1 100K_0402_5%~D AUDIO_PWREN
Security Classification Compal Secret Data Compal Electronics, Inc.
@ R1140 2 1 1K_0402_5%~D AUDIO_PWREN 2011/06/02 2013/10/28 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P20-Audio DSP, IOL Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 20 of 49
5 4 3 2 1
 5 4 3 2 1

For EMI
80mA RA24 5.1K_0402_1%
2 1 20mil 10mil HD Audio Codec SENSE_B 1 2 JACK_PLUG_DL#
+5VS_AUDIO +5VS_LDO-IN +1.5VS_3.3VS_AUDIO

4.7U_0603_6.3V6K~D
CA36

0.1U_0402_10V7K~D
CA37
@ RA2 1 1 1 2 RA24 close

0.1U_0402_10V7K~D
CA33

4.7U_0603_6.3V6K~D
CA43
0_0603_5% UA2 with UA2.33
CA46,CA31 close
2 MONO_IN
2 2 2 1 with UA2.23 10mil 23 PCBEEP
+3VS_AUDIO HVDD
39
+5VS_LDO-IN LDO-IN
1 1 46
LINE1-R 45
0807-24 CA46 CA31 11 LINE1-L 32 SLEEVE RA41
+3VS_DVDD DVDD LINE2-IN-R/SLEEVE
CA5,CA6 close 10U_0603_6.3V6M~D 0.1U_0402_10V7K~D +1.5VS_3.3VS_AUDIO 7 31 L_MIC1 10K_0402_1% Q107
2 2 DVDD_IO 25 DVDD-IO LINE2-IN-L/RING2 SENSE_A 1 2 2N7002KW_SOT323-3
with UA2.39 DVDD-IO-CP

1
D
AGND D D

CA33,CA43 close HDA_SDIN0_R 8 37 2 TABLET_MODE

SDATA-IN MIC1-R @ T254 TABLET_MODE 33
For EMI AGND HDA_SDOUT_AUDIO_R 4 36 MIC_CAP G
with UA2.7 SDATA-OUT MIC1-L/MIC-CAP

1
HDA_BITCLK_AUDIO_R 5 48 MIC2_R S

3
HDA_SYNC_AUDIO_R 9 BCLK MIC2-R 47 MIC2_L
2 1
3mA 10mil HDA_RST_AUDIO#_R 6 SYNC MIC2-L
+3VS_AUDIO +3VS_DVDD RA42
RESETB 10K_0402_5%~D
CA40,CA45 close
@ RA32 2 1 with UA2.40

2
4.7U_0603_6.3V6K~D
CA42

0.1U_0402_10V7K~D
CA35
0_0603_5% MIC2-VREFO-L 1 34 SENSE_A
CA40 0.1U_0402_10V7K~D 20mil LINE2-VREFO 29 MIC2-VREFO SENSE A 33 SENSE_B
1 2 LDO_OUT 10mil MIC2-VREFO-R 30 LINE2-VREFO SENSE B
1 2 MIC1-VREFO
CA45 10U_0603_6.3V6M~D
SURR-R
27 HP2_D_R Beep sound
1 2 CA44 1U_0603_6.3V6M 24 26 HP2_D_L
2 1 21 CBP SURR-L 19
CA67 10U_0603_6.3V6M~D JDREF 35 CBN CEN 18 RA56
2 1 MIC_CAP 10mil LDO_OUT 40 JDREF LFE CA58 1 2 1 2 1K_0402_5%~D
VREF_Codec 41 LDO-CAP 22 AMP_SPK_RR
VRP 38 VREF 44 AMP_SPK_RC 100P_0402_50V8J~D
VRP FRONT-R AMP_SPK_RC 22
CA52 100U_A_6.3V_R70M 43 AMP_SPK_LC
60mil FRONT-L AMP_SPK_LC 22 CA47

+
CA42,CA4 close 2 1 VRP RA33
1 2 1 2 MONO_IN
with UA2.11 15
GPIO2 internal pull-low by 47K ohm 33 BEEP#
RA25 20K_0402_1%
10mil 20 SPDIF-OUT 16 RA45 close 47K_0402_5%~D
2 1 JDREF 10mil 10 CPVEE SPDIF-in 0.1U_0402_10V7K~D
10mA 10mil 10mil REGREF with UA2.12
1 2 DVDD_IO CA39 2.2U_0603_6.3V6K 12 RA31
10mil 1 1

1U_0603_6.3V6M
+3VS_AUDIO DMIC_CLK_CODEC 19

10U_0603_6.3V6M~D
LH2 1 2 VREF_Codec 28 GPIO/DMIC-CLK 13 1 2

CA51

CA23
CPVREF GPIO1/DMIC-DATA DMIC_DAT_CODEC 19 8 HDA_SPKR
BLM18BA220SN1D_2P~D 1 1 22 17
AVSS1 GPIO2/Combo-Jack1 DMIC_SW_CODEC 22

1
10U_0603_6.3V6M~D
CA25

0.1U_0402_10V7K~D
CA34

42 3 47K_0402_5%~D 1
2 2 AVSS2 GPIO3/Combo-Jack2 R7 CA48
49 4.7K_0402_5%~D 100P_0402_50V8J~D
2 2 AGND Thermal PAD 14 EAPD#
EAPD EAPD# 33 2

2
AGND AGND
ALC3661-CG_MQFN48_6X6~D
C C
Close to UA2 Pin2
CA1,CA3 close
with UA2.25
AGND

+3VS_AUDIO
RA11,CA26 CA18 close Close to UA2
SP@ JPA1 Close UA2 Pin6 UA2 Pin12
Codec 20 HDA_SDIN0_DSP
RA36 1 2 33_0402_5%~D HDA_SDIN0_R 2 1 HDA_SYNC_DSP
2

1
RA52 1 2 33_0402_5%~D HDA_SDOUT_AUDIO_R JUMP_43X39 @EMI@ DMIC_CLK_CODEC
20 HDA_SDOUT_DSP
JPA2 RA30 @ CA50
Analog RA53 1 2 33_0402_5%~D HDA_SYNC_AUDIO_R 2
SP@ 1 4.7K_0402_5%~D @EMI@
2
10P_0402_50V8J~D
20 HDA_SYNC_DSP 1
Pin18~48 CA49
RA54 1 2 33_0402_5%~D HDA_RST_AUDIO#_R JUMP_43X39 10P_0402_50V8J~D
20 HDA_RST_DSP#

2
SP@ JPA3 1
20 HDA_BITCLK_DSP RA29 1 2 33_0402_5%~D HDA_BITCLK_AUDIO_R 2 1 HDA_RST_AUDIO#_R
1 DMIC_DAT_CODEC
JUMP_43X39 @EMI@ 2
CA41 CA26 @EMI@ HDA_SDOUT_DSP
Digital 22P_0402_50V8J~D 100P_0402_50V8J~D CA24
2 2
Pin2~17 10P_0402_50V8J~D
1 @ CA27
GND AGND 10P_0402_50V8J~D
1
Reserved for EMI Reserved for EMI

RA27

JACK_PLUG_DL#
Reserved Delay cricutis LINE2-VREFO
2.2K_0402_5%~D
1 2
+3VS_AUDIO
PT Change to LTCX004YP00

1
+3VS_AUDIO
ST Footprint change to:
1 2 RA14
RA28 10K_0402_5%~D
SINGA_2SJ3061-030111F_6P-T
QA6B 2.2K_0402_5%~D
0807-23 40mil JHP1
1

B B
DMN66D0LDW-7_SOT363-6~D 7

2
3

D @ RA37 @ RA38 L_MIC1 3

JACK_PLUG_DL 5 100K_0402_5%~D 100K_0402_5%~D 1
G HP_PLUG# HP2_D_L RA15 1 2 8.06_0402_1% HP2_D_L_R1 @ RA3 1 2 0_0402_5% HP2_D_L_C
HP_PLUG# 22
2

S JACK_PLUG_DL 5
4

@ RA39
6

100K_0402_5%~D D JACK_PLUG EMI@ RA35 1 2 0_0402_5%~D JACK_PLUG_C

@ QA3B 1 2 2 6
6

AGND D DMN66D0LDW-7_SOT363-6~D G HP2_D_R RA17 1 2 8.06_0402_1% HP2_D_R_R2 @ RA4 1 2 0_0402_5% HP2_D_R_C

3

2 D 2
1

G JACK_PLUG 5 S SLEEVE 4
1

1 @ G @CA38
@ CA38 @ QA3A
0.1U_0402_25V6K~D DMN66D0LDW-7_SOT363-6~D SINGA_2SJ3061-018111F
S
40mil
1

2
10U_0603_6.3V6M~D
CA57

QA6A S CONN@
4

2
100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D
DMN66D0LDW-7_SOT363-6~D

PJDLC05_SOT23-3

PJDLC05_SOT23-3

PJDLC05_SOT23-3
2

1000P_0402_25V8J
RA20
1 1 1

1
CA68

CA69

CA28

CA29
AGND AGND

100K_0402_5%~D
AGND
@ RA26 1 2 0_0402_5%
0802-12

@ESD@ DA2

ESD@ DA1

@ESD@ DA5
2
2 2 2

2
1

1
Prevent S3/S4/S5 Entry/Resume Noise For De-pop noise @ AGND AGND AGND AGND AGND AGND AGND
UA3 MAX9892ERT+T_UCSP6~D
+RTCVCC
+1.5VS_3.3VS_AUDIO HP2_D_L_R1 RA21 1 @ 2 0_0402_5%~D A1
0812-28 For EMC request, populate DA1.
INL MIC2-VREFO-R RA48 1 2 2.2K_0402_5%~D
1

RA16 SLEEVE HP2_D_R_R2 RA22 1 @ 2 0_0402_5%~D A3

+3VS_AUDIO EAPD# RA23 1 @ 2 0_0402_5%~D B1 INR +3VS_AUDIO MIC2-VREFO-L RA49 1 2 2.2K_0402_5%~D
/MUTE
1

100K_0402_5%~D
RA75 AUD_MUTE_EC# RA44 1 @ 2 0_0402_5%~D
22,33 AUD_MUTE_EC#
1

@ @ QA1B D B2
2

100K_0402_5%~D RA18 5 2 1 B3 VDD MIC2_R CA70 1 2 4.7U_0402_6.3V6M MIC2_R_C RA50 1 2 1K_0402_5%~D HP2_D_R_R2
SET 1
A 10K_0402_5%~D G @ A
GND
2 2

@ CA30 CA32 MIC2_L CA71 1 2 4.7U_0402_6.3V6M MIC2_L_C RA51 1 2 1K_0402_5%~D HP2_D_L_R1

G

S 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
2

4
6

QA1A D DMN66D0LDW-7_SOT363-6~D AGND 2

A2

HDA_RST_AUDIO#_R 3 1 2 RA43 1 2 9.09K_0402_1%

AGND
G AGND AGND
S

Setting the Turn-Off Time:

@ 1 AGND RA45 1 2 9.09K_0402_1%
Q6 S DMN66D0LDW-7_SOT363-6~D Ton (ms) = 0.02 x Cset (pF)
1

DII-DMN65D8LW-7~D @ CA74 AGND

1U_0402_6.3V6K~D
1 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
@ RA57 2011/06/02 2013/10/28 Title
Issued Date Deciphered Date
0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P21-Audio DSP, IOL Conn
AGND AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
0802-12 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 21 of 49
5 4 3 2 1
 5 4 3 2 1

+5PVDD +5PVDD

+5PVDD +5PVDD +5PVDD

2
C21,C27 close C43,C44 close
U4 +5VS_AUDIO +5PVDD
with U4.2 with U4.14 R24
2 1 SPK_OUT_L- R23
14 PVDD1 LOUIN 19 L1
SPK_OUT_L+ 49.9K_0402_1% 30.1K_0402_1%
4 PVDD2 LOUTP 1 2

1
VDD BLM21PG600SN1D_0805 VOLUME AGC
15 SPK_OUT_R-
ROUTN

2
1 1 1 1 BYPASS 9 17 SPK_OUT_R+ 1 1
BYPASS ROUTP
10U_0603_6.3V6M~D
C27

0.1U_0402_10V7K~D
C21

10U_0603_6.3V6M~D
C43

0.1U_0402_10V7K~D
C44
@
RA55 C48 @ R26 R27 C45
AMP_SPK_RR 11 3 AUD_MUTE# 1 2 150_0402_5%~D AUD_MUTE#_R 1U_0402_6.3V6K~D 49.9K_0402_1% 12K_0402_1% 1U_0402_6.3V6K~D
2 2 2 2 21 AMP_SPK_RR RINN MUTE# 2 2

1
D D
5 AMP_SPK_LR
8 LINN
18 NC1 6 AGND AGND
NC2 VDC +5PVDD
AGND
7 VOLUME
16 VOLUME
20 PGND1 10 AGC
12 PGND2 AGC
AGND 21 GND 13 1 2
GNDPAD SD# +5PVDD
R34
APA2605QAI-TRG_QFN20_4X4 100K_0402_5%~D

20mil AGND Int. Speaker Conn.

+5PVDD BYPASS
L2
40mil = For 4ohm 2W Speaker
AGC Setting (VDD=5V) BLM18PG181SN1_0603~D
SPK_OUT_L+ 1 2
SPK_OUT_L- 1 2
1 2 X7R RL R24 (K ohm) R27 (K ohm) Po(W) VAGC(V)
L3
C46 C47 RL=4 ohm 30.1 12 2.19 1.425 BLM18PG181SN1_0603~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D
1U_0603_6.3V6M 2.2U_0603_10V7K

2
2 1
RL=4 ohm 26.7 12 1.71 1.550 2 2

CA53

CA55
C46 close C47 close RL=8 ohm 30.9 12 1.15 1.400
with U4.4 with U4.9 1 1
AGND AGND

AGC Setting Threshold v.s Output Power JSPK1

DA3 @ESD@ SPK_L+_C 4 6
AGC Setting (VDD=5V) Output Power

1
PJDLC05C_SOT23-3 SPK_L-_C 3 4 G2 5
SPK_R+_C 2 3 G1
VDD~0.45VDD Disable AGC Function 2
SPK_R-_C 1
1
0.45VDD~0.27VDD Po= 8 X 0.95 (1/2 VDD - VACG)^2 / RL
AGND AGND CVILU_CI4304M2HR0-NH
0.27VDD~GND (AGC Floating) (Max Output Power 4Ω) Po=2.513W CONN@
C C
(Max Output Power 8Ω) Po=1.26W
L4
BLM18PG181SN1_0603~D
SPK_OUT_R+ 1 2
SPK_OUT_R- 1 2
RA46
C32 C50 L5
21 AMP_SPK_RC 1 2 AMP_SPK_R 1 2 AMP_SPK_R1 1 2 AMP_SPK_RR BLM18PG181SN1_0603~D
+3VS_AUDIO

1000P_0402_50V7K~D

1000P_0402_50V7K~D

2
1U_0603_6.3V6M 33K_0603_1% 1U_0603_6.3V6M 2 2

CA56

CA54
2

RA68
R25 33K_0603_1%
100K_0402_5%~D 1 1

2
D3
1

DB2J31400L_SOD323-2
AUD_MUTE#_R 2 1 DA4 @ESD@
AUD_MUTE_EC# 21,33

1
D4 AGND PJDLC05C_SOT23-3
1U_0603_6.3V6M

1 @ DB2J31400L_SOD323-2
2 1
HP_PLUG# 21
C42

RA47
C29 C51 AGND AGND
2 1 2 AMP_SPK_L 1 2 AMP_SPK_L1 1 2 AMP_SPK_LR
21 AMP_SPK_LC
1U_0603_6.3V6M 33K_0603_1% 1U_0603_6.3V6M

1
AGND
RA69
33K_0603_1%

2
AGND

B B

+3VALW

C96

D-MIC & 2nd D-MIC Switch 1 2

0.1U_0402_25V6K~D

U23
1 14
2 BE0 VCC 13
19 Array_MIC_DAT A0 BE3
3 12
19 DMIC_DAT_SW B0 A3 DMIC_DAT 19
4 11
5 BE1 B3 10
19 Array_MIC_CLK A1 BE2
6 9
19 DMIC_CLK_SW B1 A2 DMIC_CLK 19
7 8
GND B2
PI3C3125LEX_TSSOP14~D

1 2 +3VALW
R162 100K_0402_5%~D
1

@
1

D
2 @ 0_0402_5%
8 DMIC_SW_DIS R988
G Q135
S 2N7002KW_SOT323-3
3

@ RH420 1 2 0_0402_5%~D
7 DMIC_SW_PCH
A A
@ RH419 1 2 0_0402_5%
21 DMIC_SW_CODEC 0812-27 Change to short pad
1

D
@ R31 1 2 0_0402_5%~D 2 @
24 DMIC_SW_HUB
G Q134 R163 1 2 100K_0402_5%~D
+3VALW
S 2N7002KW_SOT323-3
3

D
1

2 @ @
G Q136
S 2N7002KW_SOT323-3
0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
3

R990 2011/06/02 2013/10/28 Title

Issued Date Deciphered Date
P22-Audio DSP, IOL Conn
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 22 of 49
5 4 3 2 1
 5 4 3 2 1

Pin11, Pin12 trace fixed width is 40 mils. Support Runtime D3 mode

Pin27 trace fixed width is 30mils.
Pin10, pin14, pin18 trace fixed width is 20 mils. => unstuff:JP1,RR10
Pin 9 trace fixed width is 12 mils.
Trace routing length < 200mils. Not Support Runtime D3 mode
Via size: Pad>=28 mils, Finished hole>=16 mils.

D Card Reader => unstuff:U720,R1380,C1300.

stuff:JP1,PP10. +ODR_PWR +SD_VDD2
D

+3VS_CR
+3VALW +3VS_CR

10U_0603_6.3V6M~D

0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D

0.1U_0402_10V7K~D
U1 1 1
JP1 SP@ 1

CR4

CR3

CR19

CR5
1 2 11 30 SD_CD#
1 2 3V3_IN SD_CD# 0802-12
2 2
10U_0603_6.3V6M~D

0.1U_0402_10V7K~D
JUMP_43X79 1 2 DV33_18 18 31 @ RR18 1 2 0_0402_5%

2
CR1 1U_0603_10V6K~D DV33_18 MS_INS# CR_WAKE# 8 2
1 1 2 AV12 10 32 SD_WAKE#_R 1 2
AV12 WAKE# +3VALW
1

CR7

CR2
CR8 0.1U_0402_10V7K~D @ RR10 10K_0402_5%~D
DV12S 14
DV12S
2

0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D
1 1 +ODR_PWR 15 SD_RCLK_M_R 1 2 SD_RCLK_M
SP1 @ RR2 0_0402_5% Close to JP2

CR9

CR10
12 16 SD_RCLK_P_R 1 2 SD_RCLK_P
Card_3V3 SP2 @ RR3 0_0402_5%
2 2 17 SD_CLK_R 1 2 SD_CLK
27 SP3 @ RR4 0_0402_5%
3V3aux

2.2P_0402_50V8C
19 SD_CMD_R 1 2 SD_CMD
SP4 @ RR5 0_0402_5% 1

CR20
1 2 RREF 9 20 SD_D3_R 1 2 SD_D3
+3VALW RR6 6.2K_0402_1% RREF SP5 @ RR7 0_0402_5%
21 SD_D2_R 1 2 SD_D2
SP6 @ RR8 0_0402_5% 2
3 29 SP7_SDWP
9 PCIE_PTX_CARDRX_P2 HSIP SP7 +SD_VDD2 +ODR_PWR
0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D

4
9 PCIE_PTX_CARDRX_N2 HSIN
1 1
9 PCIE_PRX_CARDTX_P2 1 2 PCIE_PRX_C_CARDTX_P2 7 +SD_VDD2
HSOP
CR11

CR12

CR14 0.1U_0402_10V7K~D
1 2 PCIE_PRX_C_CARDTX_N2 8 13
C 2 2 9 PCIE_PRX_CARDTX_N2
CR13 0.1U_0402_10V7K~D HSON NC 0802-12 JCARD C
22 SD_LN1_P_R @ RR12 1 2 0_0402_5% SD_LN1_P
NC SD_D2 1
5 23 SD_LN1_M_R @ RR13 1 2 0_0402_5% SD_LN1_M SD_D3 2 DAT2
7 CLK_PCIE_CD REFCLKP NC 3 CD/DAT3/RSV
SD_CMD
6 24 SD_REG2_R @ RR14 1 2 0_0402_5% SD_REG2 4 CMD
7 CLK_PCIE_CD# REFCLKN NC VSS1

1U_0603_10V6K~D
5
25 SD_LN0_M_R @ RR15 1 2 0_0402_5% SD_LN0_M SD_CLK 6 VDD/VDD1
NC 2 CLK
7
VSS2

CR6
CR_RST# 1 26 SD_LN0_P_R @ RR16 1 2 0_0402_5% SD_LN0_P SD_CD# 8
PERST# NC SD_RCLK_P 9 CARD DETECT
1 SD_RCLK_M 10 DAT0/RCLK+/DAT
2 SP7_SDWP 11 DAT1/RCLK-
7 CDCLK_REQ# CLK_REQ# RTS5249 (SD4.0) 12 WRITE PROTEC
SD_LN0_P 13 VSS3
1 2 28 33 SD_LN0_M 14 D0+
+3VALW GPIO GND D0-
RR9 10K_0402_5%~D 15
16 VSS4
RTS5249-GR_QFN32_4X4 SD_LN1_M 17 VDD2 20
AV12 @ RR11 1 2 0_0402_5% DV12S SD_LN1_P 18 D1- GND1 21
If GPIO not use for LED function, D1+ GND2
19 22
must be pull-high (Layout guide) RTS5249 VSS5 GND3
GND4
23

T-SOL_156-2001302603
CONN@

+3VS_CR
+5VALW +3VALW +3VALW +3VS_CR
0802-12
U720
1 1 1 7 @ R1380 1 2 0_0603_5% 1
2 VIN VOUT 8
C1301 C1297 VIN VOUT C1298
B B
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 3 6 C1300 1 2 2200P_0402_25V7K~D 0.1U_0402_10V7K~D
2 2 7 CR_PWREN ON CT 2
+5VALW 4 5
VBIAS GND 9
GND
TPS22965DSGR_SON8_2X2

+3VS
5

1
P

17,24,25,33,8 PLT_RST# IN1 4 CR_RST#

2 O
25,5 MPCIE_RST# IN2
G

1
3

U678
A SN74AHC1G08DCKR_SC70-5 @ A
R1208
100K_0402_5%~D
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P23-Card Reader
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: Wednesday, August 14, 2013 Sheet 23 of 49
5 4 3 2 1
 5 4 3 2 1

Sensor Fussion CS & Non-CS option

+3VNS_PWR

follow intel suggestion CS@ D86 R1234 1 2 10K_0402_5%~D JTMS

SDMK0340L-7-F_SOD323-2~D R1235 1 2 10K_0402_5%~D JTDO
+3VNS_PWR 2 1 R1236 1 2 10K_0402_5%~D JNTRST
8 SENSOR_STANDBY#
R1237 1 2 10K_0402_5%~D JTDI
CS@ D87
SDMK0340L-7-F_SOD323-2~D
Sensor_I2C_SCL R854 1 2 2.2K_0402_5%~D 2 1 PA0_WAKUP
19 ACCEL_INT1
Sensor_I2C_SDA R855 1 2 2.2K_0402_5%~D R1099 1 2 10K_0402_5%~D JTCK
D D

1
CS@
SENSOR_DFU_EN# @ R1220 1 2 100K_0402_5%~D R537
ACCEL_INT1 Non-CS@ R1230 1 2 0_0402_5%~D PA0_WAKUP 1M_0402_5%~D Sensor_RST# Sensor_RST# 5
ALS_INT#_HUB @ R1143 1 2 100K_0402_5%~D

2
SML1ALERT# R1229 1 2 10K_0402_5%~D PB13 @ R1367 1 2 0_0402_5%~D
PC0 @ R1135 1 2 0_0402_5%
PC2_1 @ R1136 1 2 0_0402_5%~D SENSOR_INT# 8
PA12 @ R1251 1 2 1.5K_0402_5%~D SMBALERT# 7 Note :
follow intel suggestion
Sensor_ALERT# @ R1158 1 2 0_0402_5% SML1ALERT#
Sensor Part Number
SML1ALERT# 7 CS@: SA00005P23L
PA12 R1223 1 2 1.5K_0402_5%~D PB5
Non-CS@: SA00005P250 P/N:STM32F103RCY6TRC28
9 USB20_N5 @ R1221 1 2 0_0402_5% PA11
9 USB20_P5 @ R1222 1 2 0_0402_5% PA12

+3VNS_PWR
C979
0802-12 1 2

0.1U_0402_10V7K~D RESET# 26
PT Phase change to SA00005P280 (USB)

G6

G8
H1
A8
A1
U636 +3VNS_PWR
PA0_WAKUP F6 E8 PC0

VDD_4
VDD_3
VDD_2
VDD_1
VDDA
ALS_INT#_HUB E6 PA0-WKUP PC0 F8 SBD_WAKE# TP@ T252
TP@T252
19 ALS_INT#_HUB PA1 PC1

2
GYRO_INT# H8 D6 PC2_1 @ R1090 @
19 GYRO_INT# G7 PA2 PC2 H6 Sensor_ALERT# 0_0402_5%~D R1003
H7 PA3 PC4 H5 1 2 Sensor_RST# 100K_0402_5%~D
MAG_DRDY E5 PA4 PC5 E1 DMIC_SW_HUB 22
19 MAG_DRDY GYRO_DRDY G5 PA5 PC6 E2

1
19 GYRO_DRDY G4 PA6 PC7 E3
ACCEL_INT2 E4 PA7 PC8 D1
19 ACCEL_INT2 D2 PA8 PC9 A2
@ T260 CONSOLE_TX
@ T261 CONSOLE_RX D3 PA9 PC10 B3
C 1 0.1U_0402_10V7K~D C
PA11 C1 PA10 PC11 C4 SPARE1
PA12 C2 PA11 PC12 C8 +3VNS_PWR C1152
JTMS D4 PA12 PC13 B8 SOSCI
26 JTMS PA13 PC14 2
JTCK B2 B7 SOSCO follow intel suggestion
26 JTCK PA14 PC15

2
26 JTDI JTDI C3
H4 PA15 A3 SPARE2 @
Connect to mSATA card for PB0 PD2
BOOT1 F4 R1092
Debug/Programing used H3 PB1 0_0402_5%~D
JTDO A4 PB2 C7 RESET#
26 JTDO

1
JNTRST B4 PB3 NRST A6 BOOT0 +3VNS_PWR
26 JNTRST PB4 BOOT0
PB5 A5 F7 JSNRDG
PB5 Vref+ +3VNS_PWR 0802-12

2
19 Sensor_I2C_SCL Sensor_I2C_SCL B5 C6 +3VALW 1
Sensor_I2C_SDA C5 PB6 Vbat R819 1 2 RESET#
19 Sensor_I2C_SDA PB7 2
D5 0_0402_5% 3 JTMS
8 SLATE_MODE PB8 3
B6 BYPASS/VSS_2
@ 4 JNTRST
I2C0_SCK_SNR G3 PB9 4 5 JTCK
8 I2C0_SCK_SNR

1
I2C0_SDA_SNR F3 PB10 5 6 JTDI
8 I2C0_SDA_SNR PB11 6
8 SENSOR_HUB_I2C_WAKE @ R1252 1 2 0_0402_5% SENSOR_HUB_I2C_WAKE_R G2 D8 HUB_OSC_IN 7 JTDO
PB13 G1 PB12 OSC_IN D7 HUB_OSC_OUT 7 8 Sensor_I2C_SCL
VSS_4
VSS_3

VSS_1

PB13 OSC_OUT 8
VSSA

8 SENSOR_DFU_EN# SENSOR_DFU_EN# F2 9 Sensor_I2C_SDA

F1 PB14 @ R1141 2 1 100K_0402_5%~D RESET# 9 10 SPARE1
33 SENSOR_HUB_WAKE# PB15 10 11 SPARE2
STM32F103RCY6TRC23_WLCSP64 @ R1253 2 1 100K_0402_5%~D SENSOR_HUB_I2C_WAKE_R 11 12
F5
A7
B1
H2
E7

12 13 SENSOR_HUB_I2C_WAKE_R
DFU_ENA : uC DFU mode enable (Active Low) 13 14 CONSOLE_RX
14 15 CONSOLE_TX
15 16
16 SENSOR_EN 30,8
17 SENSOR_DFU_EN#
17 18 I2C0_SCK_SNR
21 18 19 I2C0_SDA_SNR
HUB_OSC_IN Y1 22 GND 19 20
Y2 32.768KHZ_12.5PF_9H03200031 +3VNS_PWR Place close to U636 GND 20
1 2 HUB_OSC_OUT SOSCI 2 1 SOSCO ACES_50696-02001-001
CONN@
1 8MHZ_12PF_7A08000006 1 1 1 1 1 1
C1204 C1205 CH1202 CH1203 C976 C977 C978
B 1U_0402_6.3V6K~D B
2
18P_0402_50V8J~D
2
18P_0402_50V8J~D
2
18P_0402_50V8J~D
2
18P_0402_50V8J~D
2
0.1U_0402_10V7K~D
2
0.1U_0402_10V7K~D
2 0806-19 NC the JSNRDG connector for XB phase

ATMEL TPM +3VS

+3VS
0.1U_0402_10V7K~D

4700P_0402_25V7K~D

1 1 +3VS
5

U698 U652
C1135

C1136

1
P

17,23,25,33,8 PLT_RST# IN1 4 TPM_RESET# 10

2 O 2 2 5 VCC_0 19
8 TPM_RST# IN2 SB3V VCC_1
G

2200P_0402_25V7K~D

2200P_0402_25V7K~D

2200P_0402_25V7K~D

0.1U_0402_10V7K~D
24
VCC_2
1

1 1 1 1
3

SN74AHC1G08DCKR_SC70-5
C1137

C1138

C1139

C1140

R1310
220K_0402_5%~D
LPCPD# 28 12 2 2 2 2
2

LPCPD# V_BAT 13
26 NBO_13 14
17,33,7 LPC_AD0 LAD0 NBO_14
23
17,33,7 LPC_AD1 LAD1
20
17,33,7 LPC_AD2 LAD2
17,33,7 LPC_AD3 17
LAD3 6
CLK_PCI_TPM GPIO6
CLK_PCI_TPM 21 9
7 CLK_PCI_TPM LCLK TESTBI
1

@EMI@ 22 8
17,33,7 LPC_FRAME# LFRAME# TESTI
A MR976 TPM_RESET# 16 +3VS A
33_0402_5%~D 27 LRESET#
33,8 SERIRQ SERIRQ
33,8 PM_CLKRUN# 15 @
CLKRUN# 7 PP R975 1 2 4.7K_0402_5%~D
2

NC_7
1 1 4
@EMI@ 2 ATEST_1 GND_4 11
MC1141 3 ATEST_2 GND_11 18
27P_0402_50V8J~D ATEST_3 GND_18 25
2 GND_25
AT97SC3204-X2A1D-AB TSSOP
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

8 SUS_STAT#
@ R1238 1 2 0_0402_5% LPCPD#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P24-Sensor Fussion / TPM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
R1239 1 2 10K_0402_5%~D A00
+3V_PCH DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 24 of 49
5 4 3 2 1
 A B C D E

Wireless LAN closed to pin 2, 4 closed to pin 64, 66

+1.8VS +3VS_NGFF +3VS_NGFF

+1.8VS
0617-28

22U_0603_6.3V6M~D

0.1U_0402_10V7K~D

22U_0603_6.3V6M~D

0.1U_0402_10V7K~D
R1360 1 2 49.9K_0402_1%~D SDIO_CLK 1 1 1 1

C712

C716
@ R1368
@R1368 1 2 49.9K_0402_1%~D UART1_TXD_NGFF @ @

C715

C713
R1361 1 2 49.9K_0402_1%~D SDIO_CMD @R1369
@ R1369 1 2 49.9K_0402_1%~D UART1_RXD_NGFF

R1362 1 2 150K_0402_5%~D SDIO_D0

@R1370
@ R1370
@R1371
@ R1371
1
1
2
2
49.9K_0402_1%~D
49.9K_0402_1%~D
UART1_RTS#_NGFF
UART1_CTS#_NGFF NGFF(WLAN) 2 2 2 2

R1363 1 2 49.9K_0402_1%~D SDIO_D1

1 1

R1364 1 2 49.9K_0402_1%~D SDIO_D2 +3VS_NGFF

+3VS_NGFF
R1365 1 2 49.9K_0402_1%~D SDIO_D3 R942 1 2 100K_0402_5%~D PCIE_WAKE# JNGFF1
1 2
USB20_P2_R 3 GND 3.3VAUX 4
R1327 1 2 100K_0402_5%~D SDIO_WAKE#_Q USB20_N2_R 5 USB_D+ 3.3VAUX 6
R1339 1 2 100K_0402_5%~D CLK_REQ2# 7 USB_D- LED1# 8 BT_PCMCLK
+3VS GND PCM_CLK
R1328 1 2 10K_0402_5%~D SDIO_RST# SDIO_CLK 9 10 BT_PCMFR1
8 SDIO_CLK SDIO_CMD 11 SIDO_CLK PCM_SYNC 12 BT_PCMIN
8 SDIO_CMD SDIO_D0 13 SDIO_CMD PCM_IN 14 BT_PCMOUT
8 SDIO_D0 SDIO_D1 15 SDO_DAT0 PCM_OUT 16
8 SDIO_D1 SDIO_D2 17 SDO_DAT1 LED2# 18
+3VS 8 SDIO_D2 SDIO_D3 19 SDO_DAT2 GND 20
+1.8VS 8 SDIO_D3 SDIO_WAKE#_Q 21 SDO_DAT3 UART_WAKE# 22 UART1_RXD_NGFF UART_WAKE# 8
SDIO_RST# 23 SDIO_WAKE# UART_RX
SDIO_RESET#
1
+3VS_NGFF +3VS 0802-12
1
C1283 @
0.1U_0402_10V7K~D C1284 @ 24 UART1_TXD_NGFF R1209 1
@R1209
@ 2 0_0402_5%
UART_TX CL_RST# 7

1
2 0.1U_0402_10V7K~D 25 26 UART1_CTS#_NGFF
2 R1137 27 GND UART_CTS 28 UART1_RTS#_NGFF @R1210
@ R1210
+3VS +1.8VS 9 PCIE_PTX_WLANRX_P3 PETP0 UART_RTS
10K_0402_5%~D Q344 29 30 CL_RST#_L 1 2 0_0402_5%~D BT_CS_NOTICE
9 PCIE_PTX_WLANRX_N3 PETN0 RESERVED BT_CS_NOTICE 8

2
31 32 CL_DATA

G
DII-DMN65D8LW-7~D CL_DATA 7
U679 @ 33 GND RESERVED 34 CL_CLK
9 PCIE_PRX_WLANTX_P3 CL_CLK 7

2
B2 C1 WL_OFF#_R 1 3 35 PERP0 RESERVED 36
VCCB VCCA WL_OFF# 8 9 PCIE_PRX_WLANTX_N3 PERN0 COEX3
37 38

S
SDIO_WAKE# A2 D2 SDIO_WAKE#_Q 39 GND COEX2 40
B1 A1 +1.8VS 7 CLK_PCIE2 REFCLKP0 COEX1
@ 41 42 R1255 1
@R1255
@ 2 0_0402_5%~D
7 CLK_PCIE2# REFCLKN0 SUSCLK SUSCLK_R 25,33,8
PLT_RST# R1313 1 2 0_0402_5%~D SDIO_RST#_R A1 D1 SDIO_RST# Prevent Backdriver from +3VS_WLAN to +3VS 43 44 NGFF_RST#
17,23,24,33,8 PLT_RST# B2 A2 GND PERST0#
CLK_REQ2# 45 46 BT_RADIO_DIS#
7 CLK_REQ2# CLKEQ0# W_DISABLE2# BT_RADIO_DIS# 8
MPCIE_RST# R1314 1
@R1314
@ 2 0_0402_5% B1 C2 R1131 1
@R1131
@ 2 0_0402_5% PCIE_WAKE# 47 48 WL_OFF#_R
23,5 MPCIE_RST# GND OE 49 PEWAKE0# W_DISABLE1# 50
51 GND I2C_DATA 52
0802-12 TXB0102YZPR_DSBGA8
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
57 GND RESERVED 58 @R1212
@ R1212 1 2 0_0402_5%~D BT_CS_NOTICE
2 59 RSRVD/PERP1 RESERVED 60 2
61 RSRVD/PERN1 RESERVED 62
+3VS 63 GND RESERVED 64
RESERVED 3.3VAUX +3VS_NGFF
65 66
67 RESERVED 3.3VAUX
+1.8VS GND
1
@EMI@R741 1 2 0_0402_5%~D C1285 @ 69 68
+1.8VS +3VS 0.1U_0402_10V7K~D MTG77 MTG76
1
@EMI@ ML49 C1286 @ 2
WCM2012F2S-900T04_0805 0.1U_0402_10V7K~D U671@ LOTES_APCI0019-P001A01
4 3 USB20_P2_R 1 14 CONN@
9 USB20_P2 4 3 2 VCCA VCCB
UART1_TXD_NGFF 2 13 closed to pin 2, 4 closed to pin 64, 66
1 2 USB20_N2_R UART1_RXD_NGFF 3 A1 B1 12 UART1_TXD 8
9 USB20_N2 1 2 A2 B2 UART1_RXD 8 +1.8VS
UART1_RTS#_NGFF 4 11
UART1_CTS#_NGFF 5 A3 B3 10 UART1_RTS# 8 +3VS_NGFF +3VS_NGFF
6 A4 B4 9 UART1_CTS# 8

禁禁禁 時時時時
@EMI@R742 1 2 0_0402_5%~D NC NC
7 8 0808-26 Modify NGFF2 to full pin NGFF footprint 0617-28
R1188 1
@R1188
@ 2 0_0402_5%
GND OE

22U_0603_6.3V6M~D

0.1U_0402_10V7K~D

22U_0603_6.3V6M~D

0.1U_0402_10V7K~D
1 1 1 1
netin

C717

C725
TXB0104PWR_TSSOP14 @

C718

C714
EMI@ R744 1 2 0_0402_5%~D

@EMI@ ML50 +3VS 2 2 2 2

WCM2012F2S-900T04_0805
4 3 USB20_P6_R +1.8VS
9 USB20_P6 4 3
1

9 USB20_N6
1
1 2
2 USB20_N6_R 1
+1.8VS +3VS
C1287 @ NGFF(WiGig)
0.1U_0402_10V7K~D
C1288 @ 2 +3VS_NGFF
0.1U_0402_10V7K~D U677@ JNGFF2
EMI@ R743 1 2 0_0402_5%~D 2 1 14 1 2
VCCA VCCB USB20_P6_R 3 GND1 3.3VAUX_1 4
BT_PCMCLK 2 13 USB20_N6_R 5 USB_D+ 3.3VAUX_2 6 R1035 1
@R1035
@ 2
BT_PCMFR1 3 A1 B1 12 I2S_CLK 20 7 USB_D- LED1# 8 100K_0402_5%~D
BT_PCMOUT 4 A2 B2 11 I2S_SFRM_OUT 20 +1.8VS 9 GND2 NC5 10
3
5 A3 B3 10 I2S_SDO_OUT 20 11 NC1 NC6 12 3
Pop for SDIO Interface NGFF BT_PCMIN R1036 1
@R1036
@ 2
+3VS_NGFF
6 A4 B4 9 I2S_SDI_IN 20 13 NC2 NC7 14 100K_0402_5%~D
NC NC 15 NC3 NC8 16
@R1215
@ R1215 1 2 0_0402_5%~D SDIO_WAKE# 7 8 R1204 1
@R1204
@ 2 0_0402_5% TP@T289
TP@ T289 17 NC4 LED#2 18
5 NGFF_WAKE# GND OE CV38 1 2 0.1U_0402_10V7K~D PCH_DP_N3_C 19 GND3 GND4 20 PCH_DP_AUXN_C 0.1U_0402_10V7K~D1
0.1U_0402_10V7K~D 2 CV10
5 PCH_DP_N3 DP_ML3n DP_AUXn PCH_DP_AUXN 5
TXB0104PWR_TSSOP14 CV47 1 2 0.1U_0402_10V7K~D PCH_DP_P3_C 21 22 PCH_DP_AUXP_C 0.1U_0402_10V7K~D
0.1U_0402_10V7K~D1 2 CV8
5 PCH_DP_P3 DP_ML3p DP_AUXp PCH_DP_AUXP 5
R1231 1
@R1231
@ 2 0_0402_5% NGFF_WAKE#_R 23 24
CV50 1 2 0.1U_0402_10V7K~D PCH_DP_N2_C 25 GND5 GND6 26 PCH_DP_N1_C 0.1U_0402_10V7K~D 2 1 CV48
5 PCH_DP_N2 DP_ML2n DP_ML1n PCH_DP_N1 5
CV46 1 2 0.1U_0402_10V7K~D PCH_DP_P2_C 27 28 PCH_DP_P1_C 0.1U_0402_10V7K~D 2 1 CV45
5 PCH_DP_P2 DP_ML2p DP_ML1p PCH_DP_P1 5
29 30
Pop for PCIe Interface NGFF 31 GND7 GND8 32 PCH_DP_N0_C 0.1U_0402_10V7K~D 2 1 CV49
5 PCH_DP_HPD DP_HPD DP_ML0n PCH_DP_N0 5
33 34 PCH_DP_P0_C 0.1U_0402_10V7K~D 2 1
0802-12 35 GND9 DP_ML0p 36
CV37 PCH_DP_P0 5
9 PCIE_PTX_DRX_P4 PETP0 GND10
0306-39 37 38 CL_RST#_L
9 PCIE_PTX_DRX_N4 PETN0 RESERVED_1
39 40 CL_DATA
41 GND11 RESERVED_2 42 CL_CLK
9 PCIE_PRX_DTX_P4 PERP0 RESERVED_3
43 44
9 PCIE_PRX_DTX_N4 PERN0 COEX3
45 46
1 2 0_0402_5%~D 47 GND12 COEX2 48
30,8 NGFF_PWREN
@R1233
@ R1233
7 CLK_PCIE3 49 REFCLKP0 COEX1 50 R1256 1
@R1256
@ 2 0_0402_5%~D
0814-30
7 CLK_PCIE3# 51 REFCLKN0 SUSCLK 52 SUSCLK_R 25,33,8
R1243 1 2 0_0402_5%~D NGFF_RST#
R1232 1
@R1232
@ 2 0_0402_5% CLK_REQ3# 53 GND13 PERST0# 54 BT_RADIO_DIS#
Pop for SDIO Interface NGFF 7 CLK_REQ3# PCIE_WAKE# 55 CLKREQ0# W_DISABLE2# 56 WL_OFF#_R
57 PEWAKE0# W_DISABLE1# 58
+3VS 59 GND14 I2C_DATA 60
+3VS 9 PCIE_PTX_DRX_P1 RSRVD/PETP1 I2C_CLK
@U709
@ U709 61 62
9 PCIE_PTX_DRX_N1 RSRVD/PETN1 ALERT
U675 63 64
SN74AHC1G08DCKR_SC70-5 1 5 Q347 65 GND15 RESERVED 66 @ R1241 1
@R1241 2 0_0402_5%~D NGFF_RST#
NC VCC 9 PCIE_PRX_DTX_P1 RSRVD/PERP1 PERST1#
5

NGFF_WAKE#_R 1 3 PCIE_WAKE# 67 68 CLK_REQ1#

C

9 PCIE_PRX_DTX_N1 RSRVD/PERN1 CLKREQ1# CLK_REQ0# 7

MPCIE_RST# 1 69 70
Pop for PCIe Interface NGFF
P

IN1 4 NGFF_RST# 2 71 GND16 PEWake1# 72

PLT_RST# 2 O IN A MMBT3904_SOT23-3
7 CLK_PCIE0 73 REFCLKP1 3.3VAUX_3 74
+3VS_NGFF 0805-14
B
2

IN2 7 CLK_PCIE0# REFCLKN1 3.3VAUX_4

G

75
GND17
1

3 4 R1202 1 2 10K_0402_5%~D
3

GND OUT Y
R1203 1 +3VS 77 76
100K_0402_5%~D SN74AUP1G04DCKR_SOT23-5~D R1340 79 PTH2 PTH1 78
4 +5VALW C1246 100K_0402_5%~D NPTH2 NPTH1 4
2

U676 0.1U_0402_10V7K~D 1 2 CLK_REQ3# JAE_SM3ZS067U215TA

2 CONN@
1 5 R1343
2 OE VCC 100K_0402_5%~D
33,8 WAKE_PCH# 3 A 4 PCIE_WAKE# 1 2 CLK_REQ0#
GND B
1

@ SN74CBTD1G125DCKR_SC70-5
R1338
100K_0402_5%~D
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P25-WLAN / WiGig / BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 25 of 49
A B C D E
 5 4 3 2 1

mSATA Card
+3.3VDX_SSD

JSATA1
1 2
3 1 2 4
5 3 4 6
7 5 6 8
7 8 JTMS 24
9 10 JTDO 24
D
11 9 10 12 D
11 12 JTDI 24
13 14 Connect to Sensor HUB uC JTAG for
13 14 JTCK 24
15 16 JNTRST 24
17 15 16 18 Debug/Programing used
19 17 18 20
19 20 RESET# 24
21 22
21 22 +3VNS_PWR
7 SATA_PRX_DTX_P0 CS54 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P0_C 23 24
CS53 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N0_C 25 23 24 26
7 SATA_PRX_DTX_N0 25 26
27 28
29 27 28 30
CS43 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N0_C 31 29 30 32
7 SATA_PTX_DRX_N0 31 32
7 SATA_PTX_DRX_P0 CS42 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P0_C 33 34
35 33 34 36 @ T242
37 35 36 38 @ T243
39 37 38 40
+3.3VDX_SSD 39 40 +3.3VDX_SSD
41 42
43 41 42 44 DEVSLP0
43 44 DEVSLP0 8
@ T244 45 46
@ T245 47 45 46 48
@ T246 49 47 48 50 @
49 50

4.7U_0603_6.3V6K~D
C719

.1U_0402_16V7K~D
C720

0.01U_0402_16V7K~D
C721

47P_0402_50V8J~D
C722
51 52 1 1 1 1
7 mSATA_DET# 51 52
53 54
GND1 GND2
2 2 2 2
LCN_DAN08-52216-0100
CONN@

PT Change to LTCX004P100
Footprint: CONCR_197BASA36340NNN_52P-T
ST Footprint change to: LCN_DAN08-52216-0100_52P
C C

+3.3VDX_SSD

@
R1366 1 2 10K_0402_5%~D DEVSLP0

+3.3VDX_SSD
+5VALW +3VALW +3VALW +3.3VDX_SSD

U724
0802-12
1 1 1 7 @ R1389 1 2 0_0603_5% 1
2 VIN VOUT 8
C1303 C1299 VIN VOUT C1302
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 3 6 C1304 1 2 2200P_0402_25V7K~D 0.1U_0402_10V7K~D
2 2 8 SSD_PWREN ON CT 2
4 5
+5VALW VBIAS GND 9
GND
TPS22965DSGR_SON8_2X2

B B

ME Decide using 15 pin conn

MB 15 <-------> 15 pin NFC
The I2C address set on the module is 28h

0802-12 +3V_NFC
JNFC1
15
@ R1242 1 2 0_0603_5% 14 15 15. MOD_GND
+3V_PCH 14 14. VDD_IO
13
13 13. MOD_VDD
12 12. SWP_PWR
11 12
11 11. NC/Float
NFC_RST# 10 10. Reset/WakeUp
2 1 100K_0402_5%~D 8 NFC_RST# 9 10
@ R1142 NFC_RST# 9. MOD_GND
8 9
7 SML0CLK 8. I2C_SCL
7 8
7 SML0DATA 7. I2C_SDA
NFC_VDD_SIM 6 7
6. VDD_SIM
5 6
8 NFC_IRQ 5. IRQ
NFC_DET# 4 5 4. MOD_GND
8 NFC_DET# 4
3 3. SWP
3
2

2 2. MOD_GND
NFC_DET# @ R1228 1 2 0_0402_5%~D 1 2 1. MOD_VDD
R1100 1
100K_0402_5%~D 16
17 GND
1

GND
HB_A531515-SCHR21
A CONN@ A
+3V_NFC
@
NFC_VDD_SIM R973 2 1 10K_0402_5%~D +3V_NFC

@ R974 1 2 0_0402_5%
1
0802-12 C1134
0.1U_0402_10V7K~D
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P26-mSATA / NFC Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: Wednesday, August 14, 2013 Sheet 26 of 49
5 4 3 2 1
 A B C D E

close to JUSB1

USB IO Port USB CONN

+5V_USB_P1

ML40 EMI@
2.1A / Channel +5V_USB_P1

SW_USB20_P1 1
1 2
2 USB20_P1_CONN +5VALW +5V_USB_P1 2.0A
JUSB1
US1 USB3TP1_RC_CON 9

47U_1206_6.3V6M~D
SW_USB20_N1 4 3 USB20_N1_CONN 1 12 1 SSTX+

.1U_0402_16V7K~D
1 4 3 IN OUT USB3TN1_RC_CON 8 VBUS 1
SSTX- 1 1
DLW21HN900SQ2L_4P 13 9 USB20_P1_CONN 3
9 USB_OC1# FAULT# STATUS# D+
7 C303 C265
2 11 SW_USB20_N1 USB20_N1_CONN 2 GND1 11
9 USB20_N1 DM_OUT DM_IN D- GND3 2 2
9 USB20_P1 3 10 SW_USB20_P1 USB3RP1_RC_CON 6 12
DP_OUT DP_IN 4 SSRX+ GND4 13
USB_ILIM_SET 4 15 USB3RN1_RC_CON 5 GND2 GND5 14
@ R1216 1 2 100K_0402_5%~D USB1_EN 5 ILIM_SEL ILIM_LO 16 10 SSRX- GND6
EN ILIM_HI 33 USB1_DET# Plug_DET
C623

22.1K_0402_1%~D

48.7K_0402_1%~D
0.1U_0402_10V7K~D ML45 EMI@ USB_CTL1 6 TAIWI_USB022-107CRL-TW
CTL1

1
1 2 USB3TP1_C 1 2 USB3TP1_RC_CON 7 14 CONN@
9 USB3TP1 CTL2 GND

R1117

R1118
R1165 2 1 100K_0402_5%~D 8 17
+5VALW CTL3 GPAD
1 2 USB3TN1_C 4 3 USB3TN1_RC_CON TPS2546RTER_QFN16_3X3
9 USB3TN1
PT phase Change to TAIWI_USB022-107CRL-TW

2
C621 DLW21SN670HQ2L_4P~D
0.1U_0402_10V7K~D
+5VALW
+3VALW
C1289
1 2
1 1

5
0.1U_0402_10V7K~D
1 +5V_USB_P1 C962 C963
For ESD request

P
9 USB1_PWR_EN INA
ML46 EMI@ 4 USB1_EN 10U_0603_6.3V6M~D .1U_0402_16V7K~D
1 2 USB3RN1_RC_CON 2 O MD74 ESD@ 2 2
9 USB3RN1 33 USB1_PWR_EN_EC INB

G
USB20_P1_CONN 1 8
U699 USB20_N1_CONN 2 R- VCC 7

3
4 3 USB3RP1_RC_CON SN74AHC1G32DCKR_SC70-5 USB3TN1_RC_CON 3 R+ GND 6 USB3RN1_RC_CON
9 USB3RP1 T- D-
USB3TP1_RC_CON 4 5 USB3RP1_RC_CON
DLW21SN670HQ2L_4P~D T+ D+
AZ1065-06Q.RDG_MSOP8

R1214 2 1 100K_0402_5%~D
+5VALW
2 @ R1167 2 1 0_0402_5% USB_CTL1 2
33 USB1_CTL1

+5VALW R1213 2 1 100K_0402_5%~D

@ R1166 2 1 0_0402_5% USB_CTL0

33 USB0_CTL1

CTL1 CTL2 CTL3 ILIM_SEL MODE

+5VALW
0 1 1 0 DCP_Auto
@ R1170 1 2 100K_0402_5%~D

USB_ILIM_SET R1164 1 2 100K_0402_5%~D

0 1 1 1 DCP_Auto 33 USB_ILIM_SET

1 1 1 0 SDP

1 1 1 1 CDP close to JUSB2

+5V_USB_P0

+5V_USB_P0
USB CONN 2.0A

47U_1206_6.3V6M~D
+5VALW

.1U_0402_16V7K~D
1 1
ML52 EMI@ +5V_USB_P0 JUSB2
SW_USB20_N0 4 3 USB20_N0_CONN US2 USB3TP0_RC_CON 9 C1109 C1110
3 4 3 1 12 1 SSTX+ 3
IN OUT USB3TN0_RC_CON 8 VBUS 2 2
SW_USB20_P0 1 2 USB20_P0_CONN 13 9 USB20_P0_CONN 3 SSTX-
1 2 8,9 USB_OC0# FAULT# STATUS# D+
7
DLW21HN900SQ2L_4P 2 11 SW_USB20_N0 USB20_N0_CONN 2 GND1 11
9 USB20_N0 DM_OUT DM_IN D- GND3
3 10 SW_USB20_P0 USB3RP0_RC_CON 6 12
9 USB20_P0 DP_OUT DP_IN SSRX+ GND4
4 13
USB_ILIM_SET 4 15 USB3RN0_RC_CON 5 GND2 GND5 14
@ R1217 1 2 100K_0402_5%~D USB0_EN 5 ILIM_SEL ILIM_LO 16 10 SSRX- GND6
EN ILIM_HI 33 USB0_DET# Plug_DET

22.1K_0402_1%~D

48.7K_0402_1%~D
USB_CTL0 6 TAIWI_USB022-107CRL-TW
CTL1

1
C1108 R1168 2 1 100K_0402_5%~D 7 14 CONN@
+5VALW CTL2 GND

R1120

R1119
0.1U_0402_10V7K~D ML53 EMI@ 8 17
USB3TP0 1 2 USB3TP0_C 1 2 USB3TP0_RC_CON CTL3 GPAD
9 USB3TP0
TPS2546RTER_QFN16_3X3 PT phase Change to TAIWI_USB022-107CRL-TW

2
USB3TN0 1 2 USB3TN0_C 4 3 USB3TN0_RC_CON
9 USB3TN0
C1107 DLW21SN670HQ2L_4P~D +5VALW
0.1U_0402_10V7K~D

+3VALW
C1290 For ESD request 1 1
1 2 +5V_USB_P0 C1172 C1173
10U_0603_6.3V6M~D .1U_0402_16V7K~D
5

0.1U_0402_10V7K~D MD82 ESD@ 2 2

1 USB3RN0_RC_CON 1 8
P

8 USB0_PWR_EN INA R- VCC

ML54 EMI@ 4 USB0_EN USB3RP0_RC_CON 2 7
USB3RN0 4 3 USB3RN0_RC_CON 2 O USB3TN0_RC_CON 3 R+ GND 6 USB20_P0_CONN
9 USB3RN0 33 USB0_PWR_EN_EC INB T- D-
G

USB3TP0_RC_CON 4 5 USB20_N0_CONN
U700 T+ D+
3

9 USB3RP0 USB3RP0 1 2 USB3RP0_RC_CON SN74AHC1G32DCKR_SC70-5 AZ1065-06Q.RDG_MSOP8

DLW21SN670HQ2L_4P~D

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P27-USB 3.0 IO CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 27 of 49
A B C D E
 A B C D E F G H

0221-11 unstuff Batman2

+3VS
Batman 2
Vibrator
0225-21

2
@ Q359A

1 Q330 BATMAN_CLK 6 1 1
+3VALW AO3419L_SOT23-3 PCH_SMLCLK 19,32,33,7
20mil DMN66D0LDW-7_SOT363-6~D
3

D
1 MOTOR_P1
MOTOR_P1 19 1 2

5
@ R1350 0_0402_5%~D

G
2

1
@ BATMAN_DATA @ Q359B 3 4
PCH_SMLDATA 19,32,33,7
MOTOR_EN# DH5
33 MOTOR_EN#
1 RB751V-40_SOD323-2 DMN66D0LDW-7_SOT363-6~D
@
C1164

2
0.1U_0402_10V7K~D 1 2
2 @ R1351 0_0402_5%~D +3V_BATMAN

BATMAN_CLK @ R1347 1 2 2.2K_0402_5%~D

+3V_BATMAN BATMAN_DATA @ R1346 1 2 2.2K_0402_5%~D

20mil
MOTOR_N1 19

0.1U_0402_10V7K~D
1

1
+3V_BATMAN @
@

C1294
+3VALW 0_0402_5%~D @ R1349 2 1 0_0402_5%~D +3V_BATMAN
R924 +3VLP 2 @ U714
@ R1348 2 1 0_0402_5%~D
+RTCVCC

2
MOTOR_EN# R923 1 2 10K_0402_5%~D 11
VCC
2 12
INTA NC 1
10 NC 4
2 SQW/INTB NC 5 2
BATMAN_DATA 6 NC 8
@ Y3 SDA NC 9
BATMAN_X1 1 2 BATMAN_X2 BATMAN_CLK 7 NC 13
SCL NC 16
32.768KHZ_7PF_Q13FC1350000200 BATMAN_X1 14 NC
X1 3
1 1 GND
BATMAN_X2 15 17
@ C1295 @ C1296 X2 GND
7P_0402_50V8C~D 7P_0402_50V8C~D
2 2 1337GNLGI8_QFN16_3X3

Power LED Control 0705-6

R1
1.1K +-5% 0402~D
2 1 PWR_LED#
PWR_LED# 20
6

Q366A D
BATT_LED_CTRL# 2
G
1

R36 S
1

100K_0402_5%~D DMN66D0LDW-7_SOT363-6~D

3 3
2

Q366B D
BATT_LED_COLOR_W 5
33 BATT_LED_COLOR_W G
+3VALW
S U5
4

DMN66D0LDW-7_SOT363-6~D
1 5
NC VCC

0705-6 BATT_LED_COLOR_W 2
IN A
R4
1.1K +-5% 0402~D 3 4 BATT_LED_COLOR_W#
2 1 BATT_LOW_LED#_C GND OUT Y
BATT_LOW_LED#_C 20
SN74AUP1G04DCKR_SOT23-5~D
6

Q367A D
BATT_LED_CTRL# 2
33 BATT_LED_CTRL# G
DMN66D0LDW-7_SOT363-6~D
S
1
3

4 Q367B D 4
BATT_LED_COLOR_W# 5
G
DMN66D0LDW-7_SOT363-6~D
S
4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P28-BAT LED
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: Wednesday, August 14, 2013 Sheet 28 of 49
A B C D E F G H
 5 4 3 2 1

0227-30

3V/5V EN +1.05VS EN
D D

D301 DB2J31400L_SOD323-2
1 2 2 1 3VA_EN
33 USBCHG_DET_D R342 2.2K_0402_5% 3VA_EN 37
D302 DB2J31400L_SOD323-2
R501
1 2 2 1 nvPRO@
33 EC_ON R341 2.2K_0402_5% 1 2 EN_+1.05VS
D303 DB2J31400L_SOD323-2 17,30,33,40,8 PM_SLP_S3# EN_+1.05VS 41
1 2 0_0402_5%
33 VCOUT0_PH#
@ D305
2 1 R503
vPRO@
20,30,8 AUDIO_PWREN
1 2
SDMK0340L-7-F_SOD323-2 17,30,33,8 PM_SLP_A#
0_0402_5%
@ D306
2
19,30,5 PCH_ENVDD
1

3
19,30,33 EC_ENVDD
BAT54CW_SOT323-3

vPRO@
D307 10K_0402_1% 2 1 R746 APOWER_OK
+3.3V_M APOWER_OK 33,41,8
3
30,33,8 PM_SLP_SUS#
1 EN_+V5A
EN_+V5A 37
note:Close PU501 PIN1
2
33 5VA_EN
C C
BAT54CW_SOT323-3

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P29-3V/5V/+1.05A EN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 29 of 49
5 4 3 2 1
 A B C D E

MLK IC :
PM_SLP_SUS# : Deep Sx Indication 20m ohm
R1026 2 1 220K_0402_5%~D EC_ENVDD
+LCDVDD When asserted (low), this signal indicates PCH +3V_PCH 500m A
MLK IC : is in Deep Sx state where internal Sus power is
20m ohm +LCDVDD Intel :
0802-12 shut off for enhanced power saving. 0806-21
303m A D93 DB2J31400L_SOD323-2 U715 1 When deasserted (high), this signal indicates exit from
+3V_PCH 532m ohm
Intel : 19,29,5 PCH_ENVDD
2 1
+3VALW
1
VIN1 VOUT1
14 @ R1322 1 2 0_0805_5% C1231
Deep Sx state and Sus power can be applied to PCH 0802-12 1 62m A
2 13 10U_0603_6.3V6M~D U719
44m ohm VIN1 VOUT1
+3VALW 1 14 R1326 1 2 0_0603_5%~D C352
2 VIN1 VOUT1
750m A EC_ENVDD 3
ON1 CT1
12 C1230 1 2 2200P_0402_25V7K~D 2
VIN1 VOUT1
13
2
1U_0402_6.3V6K~D

4 11 PM_SLP_SUS#_R 3 12 C355 1 2 2200P_0402_25V7K~D MLK IC :

19,29,33 EC_ENVDD +5VALW VBIAS GND 29,33,8 PM_SLP_SUS# ON1 CT1
EN_CAM 5 10 C1247 1 2 2200P_0402_25V7K~D +3VS_CAM +3VS_CAM 4 11 20m ohm
8 EN_CAM ON2 CT2 +3VALW VBIAS GND
+3VALW 20m A
@ R1260 1 2 0_0603_5% 6 9 5 10 C1278 1 2 2200P_0402_25V7K~D +3VS_TS
1 +3VALW
7 VIN2 VOUT2 8 1 2 0_0603_5%~D
8 TS_EN ON2 CT2 +3VS_TS Intel : 1
MLK IC : VIN2 VOUT2
R1321
73m ohm

.1U_0402_16V7K~D

10U_0603_6.3V6M~D
1 6 9
20m ohm C617 1 2 .1U_0402_16V7K~D 15
+3VALW
7 VIN2 VOUT2 8 @ R1320 1 2 0_0603_5% ?m A
300m A 0802-12 GPAD 0802-12 1 1 VIN2 VOUT2

C1158

C1159
C1199 1
TPS22966DPUR_SON14_2X3 1U_0402_6.3V6K~D 15
Intel : 0807-25 2 GPAD SIP 0802-12 C1200
41m ohm 2 2 TPS22966DPUR_SON14_2X3 1U_0402_6.3V6K~D
800m A 2
R1162 2 1 100K_0402_5%~D EN_CAM

R290 2 1 100K_0402_5%~D PM_SLP_SUS#_R

MLK IC :
+5VS
MLK IC : +3VS 20m ohm
0802-12 20m ohm ??m A
U717 600m A Intel :
1 14 @ R1331 1 2 0_0603_5% +3VS
+5VALW 1
2 VIN1 VOUT1 13 106m ohm
VIN1 VOUT1 +5VS U716
0802-12 C1256 310m A
3 12 C1163 1 2 2200P_0402_25V7K~D 1 14 @ R1330 1 2 0_0603_5% 1U_0402_6.3V6K~D
17,29,30,33,40,8 PM_SLP_S3# ON1 CT1 +5VALW +3VALW VIN1 VOUT1 2
2 13
4 11 VIN1 VOUT1
+5VALW 0806-21 +5VALW VBIAS GND 1
3 12 C1257 1 2 2200P_0402_25V7K~D
17,29,30,33,40,8 PM_SLP_S3# ON1 CT1
5 10 C1281 1 2 2200P_0402_25V7K~D C1162 MLK IC :
0802-12 20,29,8 AUDIO_PWREN ON2 CT2 10U_0603_6.3V6M~D
1
4 11
R1306 1 2 0_0603_5%~D 6 9 2 C1254
+5VALW VBIAS GND 20m ohm
1 +3VS VIN2 VOUT2
SIP +1.5VS @ R1305 1 2 0.01_0603_1% 7
VIN2 VOUT2
8 +1.5VS_3.3VS_AUDIO 0.1U_0402_10V7K~D 24,8 SENSOR_EN SENSOR_EN 5
ON2 CT2
10 C1248 1 2 2200P_0402_25V7K~D +3VNS_PWR 160m A
C1161 2
0.1U_0402_10V7K~D C1280 1 2 0.1U_0402_10V7K~D 15 6 9
Intel :
2 GPAD +3VALW VIN2 VOUT2 73m ohm
7 8 @ R1319 1 2 0_0603_5%
VIN2 VOUT2
TPS22966DPUR_SON14_2X3 MLK IC : 550m A
15
20m ohm GPAD
30m A R1250 2 1 100K_0402_5%~D SENSOR_EN TPS22966DPUR_SON14_2X3
0802-12

2 2
+3VS_NGFF
+1.05VA +1.05VS

+5VALW nvPRO@ 1
R1355 1 2 0_1206_5% +3VS_NGFF MLK IC :
+1.05VS C1215
+5VALW 0.1U_0402_10V7K~D20m ohm
1
@ D115 U718
0802-12 2 7m A
C1241 U673 vPRO@ 1 MLK IC : BAT54CW_SOT323-3 1 14 @ R1226 1 2 0_0603_5% Intel :
+3VALW VIN1 VOUT1
0.1U_0402_10V7K~D 4 2 C1240 2 2 13
2 5 VIN VCC 10U_0603_6.3V6M~D 5m ohm 25,8 NGFF_PWREN VIN1 VOUT1 2570m ohm
VIN 3414m A
9
VIN VOUT
6
2
1 WLAN_EN 3
ON1 CT1
12 C1202 1 2 2200P_0402_25V7K~D 7m A
10 7 Intel :
11 VIN VOUT 8 3 4 11
+1.05VA VIN VOUT 5m ohm 33 EN_WLANPWR# +5VALW VBIAS GND
12 vPRO@
VIN +3VS_TP
13
VIN BLEED
15 R1190 1 2 0_0402_5%~D 3414m A 8 TP_EN TP_EN 5
ON2 CT2
10 C1292 1 2 2200P_0402_25V7K~D
14 17 C1244 1 2 1000P_0402_25V8J MLK IC :
18 VIN SR vPRO@ 6 9
1 VIN +3VALW VIN2 VOUT2 20m ohm
19 16 7 8 @ R1128 1 2 0_0603_5%
VIN EN PM_SLP_S3# 17,29,30,33,40,8 VIN2 VOUT2
C1243 15m A
0.1U_0402_10V7K~D 3 1 @ C1242 1 2 0.01U_0402_16V7K~D 15
2 GND Delay GPAD
NCP4545IMNTWG_QFN18_3X3~D TPS22966DPUR_SON14_2X3
0802-12

R1174 2 1 100K_0402_5%~D TP_EN

Change circuits design for meet Intel timing, ramp time = 10uS for rising and falling
+3.3V_M

+1.05VA +1.05VDX_MODPHY
MLK IC :
+1.05VA Q360 5m ohm R1390 2 1 220K_0402_5%~D WLAN_EN
Non-vpro-->stuff R1129,
1
B+ SiSA12DN-T1-GE3_POWERPAK8-5 1840m A +5VALW +3VALW unstuff U721,R196,C407,R1379
1 Intel : C1216
B+ 2 nvPRO@ 0.1U_0402_10V7K~D
1
5 3 6m ohm 1 1 R1129 1 2 0_0603_5%~D 2
+3VS
C1228 1840m A
1

3 3
0.1U_0402_10V7K~D 1 C1203 C1219 vPRO@
2 C1209 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D U721 vPRO@
4
4

R1381 Q361 10U_0603_6.3V6M~D 2 2 1 7 R1379 1 2 0.01_0603_1%

+3VALW VIN VOUT +3.3V_M
10K_0402_5%~D 5 2 8
2 VIN VOUT vPRO@
2

3 R1382 1 2 330_0402_5%~D 3 6 C407 1 2 2200P_0402_25V7K~D

1 17,29,33,8 PM_SLP_A# ON CT
MPHY_PWREN# +5VALW 4 5
VBIAS GND 9
GND
1

D 2 6 R1383 1 2 330_0402_5%~D 1
MPHY_PWREN 2 TPS22965DSGR_SON8_2X2
8 MPHY_PWREN
G Q362 SI1553CDL-T1-GE3_SC70-6 C1227
S 0.01U_0402_16V7K~D
3

DII-DMN65D8LW-7~D 2

@ R1169 2 1 100K_0402_5%~D MPHY_PWREN

+1.05VDX_MODPHY +1.5VS +1.05VS +3V_PCH

Discharge

1
@ R300 @ R296 @ R297 @ R298
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%

2
+1.05VDX_MODPHY_D
+3VALW +3VALW

+1.5VS_D

+VCCP_D

+3V_D
U713 @ U710 @

DII-DMN65D8LW-7~D

DII-DMN65D8LW-7~D

DII-DMN65D8LW-7~D

DII-DMN65D8LW-7~D
1 5 1 5
NC VCC NC VCC
4 4
PM_SLP_SUS# 2 PM_SLP_S3# 2 @ Q39 @ Q34 @ Q4 @ Q5
IN A IN A
1

1
D D D D
MPHY_PWREN# 2 RUN_ON# 2 RUN_ON# 2 PM_SLP_SUS 2
3 4 PM_SLP_SUS 3 4 RUN_ON# G G G G
GND OUT Y GND OUT Y
S S S S
3

3
SN74AUP1G04DCKR_SOT23-5~D SN74AUP1G04DCKR_SOT23-5~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P30-DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 30 of 49
A B C D E
 A B C D E

FD1 FD2 FD3 FD4 FD5 FD6

@ @ @ @ @ @
INT_KBD Conn.
1

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
JKB1
10 : Diagnostic
10 12
8 KB_DET# 10 GND
9 11
KSI7 8 9 GND
KSI6 7 8
1 NGFF Screw Hole H26 H15 KSI4 6 7 1
KSI[0..7] KSI2 5 6
KSI[0..7] 33 5
H_3P3 H_3P3 KSI5 4
@ @ KSO[0..16] KSI1 3 4
KSO[0..16] 33
1

1
KSI3 2 3
KSI0 1 2
1
ACES_51522-01001-001
CONN@
PCB Screw Hole
H1 H6 H7 H2 H4 H18 JKB2
KSO5 20 22
H_2P4 H_2P4 H_2P4 H_2P4 H_3P0 H_2P4 KSO4 19 20 GND 21
@ @ @ @ @ @ KSO7 18 19 GND
1

1
KSO6 17 18
KSO8 16 17
0806-17 NC the JKB2 for XB phase KSO3 15 16
KSO1 14 15
0802-14 KSO2 13 14
H19 H20 KSO0 12 13
KSO12 11 12
H_1P6N H_2P4X1P6N KSO16 10 11
@ @ KSO15 9 10
1

KSO13 8 9
KSO14 7 8
KSO9 6 7
KSO11 5 6
KSO10 4 5
3 4
2 3
1 2
1
ACES_50696-02001-001
CONN@

2 PT phase Change to LTCX004HJ00 2

PCB Screw Hole for CPU (NUT)

H9 H10
+3VS +5VS +5VS
H_3P9 H_3P9 Q329
CONN@ CONN@ AO3419L_SOT23-3
1

2
LED2

D
R989 3 1 1 2 CAPS_LED 2 1

2
H11 H12

G
100K_0402_5%~D R943 LTW-C193TS5_WHITE
110_0402_1%

G
1

2
H_3P9 H_3P9 3 1
33 CAPS_LED#
CONN@ CONN@

D
1

1
DII-DMN65D8LW-7~D
Q326 @ C1160
0.1U_0402_10V7K~D
2

0721-10 +5VS_KBL

@ BRK1

2
R950
1

100K_0402_5%~D
NCQF0_MB_SUP_BRK

1
+5VS +5VS_KBL JBL1
20mil
KB_LED_PWM# 1
32 KB_LED_PWM# 2 1 LED Maximum Current is 300mA
3
2 1 R944 1 2 49.9K_0402_1%~D 3 2 3
8 KB_BL_DET 3
F1 4
8/12 confirm link to GND. 0.75A_24V_1812L075-24DR~OK
+5VS_KBL 4

2
5
R945 6 GND
GND
1 1
100K_0402_5%~D ACES_51522-00401-001
C1153 C1059 CONN@

1
1U_0603_10V6K~D 10U_0603_6.3V6M~D

1
2 2 D
Add a diode on +RTCBATT path, same as Murcielago MLK. 2 Q311
33 KB_LED_PWM
G DII-DMN65D8LW-7~D
S

3
RTC Battery
+RTCBATT
PBJ1
+RTCBATT +RTCBATT 1 Intel recommend for EMI Intel recommend for EMI Intel recommend for EMI
+
2
- +0.675VS +0.675VS +VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE B+ B+ B+
JHT_CR2016-L01(JHLF)~D
2

RTC@
RTCR1 1 1 1 1 1 1 1 1 1
+3VLP 1K_0402_5% 0321-53 EMI@ EMI@ EMI@ EMI@ EMI@ EMI@ EMI@ EMI@ EMI@
MC1267 MC1268 MC1269 MC1270 MC1271 MC1272 MC1273 MC1274 MC1275
0705-4 PT Phase change to coin battery 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D
1

2 2 2 2 2 2 2 2 2
W=20mils W=20mils
3

RTCD1
BAT54CW-7-F_SOT323-3

4 Intel recommend for EMI 4

1

W=20mils
+RTCVCC
+3VS +3VS
1
CH95
1U_0402_6.3V6K
2 1 1
EMI@ EMI@
MC1276 MC1277
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
2 2
For XB request, remove JBT1 connector Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title
0721-9 P31-SCREWH/KB/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Friday, August 23, 2013 Sheet 31 of 49
A B C D E
 5 4 3 2 1

+1.05VS_VCCST

1.05VS_PG 17,8

1
+3V_PCH

U672 R1132
1 5 10K_0402_5%~D
NC VCC

2
D D
@ R1353 1 2 0_0402_5% 2
33 1.05VS_PG_EC A 4
3 Y 1.05VS_VCCST_PG 10,17
GND
74AUP1G07GW_TSSOP5

+3VS_TP

Touchpad CONN
1
C1225
1U_0402_6.3V6K~D
+3VS_TP 2

+3VS_TP +1.8VS

1
+3VS +3V_PCH JTP1
R1300 1
100K_0402_5%~D 2 1
2

2
@ Q364 3

G
1

2
3
1

@ 33 TP_DATA 4
C1261 1 3 TP_INT#_R 5 4
+3V_PCH 5 TP_INT# 33 TP_CLK 5
R1289 @ 0.1U_0402_10V7K~D 6

S
2 19 I2C1_SCK_TP 6
10K_0402_5%~D 19 I2C1_SDA_TP 7
DII-DMN65D8LW-7~D TP_INT#_R 8 7
2

@ @ R1290 1 2 0_0402_5%~D 9 8
31 KB_LED_PWM# 9
5

U690 @ R1387 10
+3V_PCH 19,28,33,7 PCH_SMLCLK 10
@ R1291 1 2 0_0402_5%~D 1 @ 1 2 11 13
P

10,43 IMVP_VR_PG IN1 C1262 19,28,33,7 PCH_SMLDATA 11 GND

C 4 DELAY_VR_AND_ALL_SYS KB_INT#_R 12 14 C
2 O 1 2 0_0402_5% 12 GND
33 HWPG IN2
G

@ ACES_51522-01201-001

5
U691 0.1U_0402_10V7K~D
3

CONN@

2
SN74AHC1G08DCKR_SC70-5 1 @ R1292 DE2 DE1

P
IN1 4 ALL_SYS_PCH_PWROK_EC 1 2 +3VS_TP @ESD@ @ESD@
O SYS_PWROK 17,8

PESD5V0U2BT_SOT23-3~D

PESD5V0U2BT_SOT23-3~D
2
33 PCH_PWROK_EC IN2
G 1K_0402_5%~D
3

SN74AHC1G08DCKR_SC70-5

1
R1301

1
100K_0402_5%~D

2
@ R1294 1 2 0_0402_5% @ Q365

2
1
1 3 KB_INT#_R
R1297 33 KB_INT#

S
0802-12 0_0402_5%
@ DII-DMN65D8LW-7~D

2
@ R1295 1 2 0_0402_5%~D @ R1388
PCH_PWROK 8 1 2
@ R1296 1 2 0_0402_5%~D
0_0402_5%

B
System Thermal Sensor B

Fan CONN
+3VALW_EC +3VALW_EC

0621-1
0705-5
1

+3VS +5VS
R940 R947

0.1U_0402_25V6K~D
13.7K_0402_1%~D 12.7K_0402_1%~D

2
2

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D
33 MEM_TEMP0

2
33 VCIN0_PH

C1102
1

+3VALW_EC

R884

R886
R1103
1
R946 R948
100K_0402_1%_TSM0B104F4251RZ 100K_0402_1%_TSM0B104F4251RZ JFAN1

1
2

SDMK0340L-7-F_SOD323-2~D 1
R949 D81 2 1 2 1
13.7K_0402_1%~D 33 ECAGND 33 SYSTEM_FAN_FB 3 2
33 SYSTEM_FAN_PWM 3
4
1

5 4
6 5
33 FAN_TEMP0 7 6
8 7
8
1

9
+3VALW_EC +3VALW_EC GND1 10
R951 GND2
100K_0402_1%_TSM0B104F4251RZ
HB_A510810-SCHR21
2

CONN@
A R933 R937 A
13.7K_0402_1%~D 13.7K_0402_1%~D
2

33 SKIN_TEMP0 33 SKIN_TEMP1
1

R936 R938
100K_0402_1%_TSM0B104F4251RZ 100K_0402_1%_TSM0B104F4251RZ
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P32-TP / FAN/PWERGD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 32 of 49
5 4 3 2 1
 5 4 3 2 1

+3VALW +3VALW_EC L43

FBMA-L11-160808-800LMT_0603 2 1 Win8_INT# Board ID
1 2 +3VALW_EC 1 2 +EC_VCCA C282 1 2 .1U_0402_16V7K~D ECAGND @EMI@ MC105 10P_0402_50V8J~D +3VALW_EC
ECAGND 32
1 1 1 1 2 2

.1U_0402_16V7K~D
C277

.1U_0402_16V7K~D
C276

.1U_0402_16V7K~D
C278

.1U_0402_16V7K~D
C279

1000P_0402_50V7K~D
C280

1000P_0402_50V7K~D
C281
@ R216

2
0_0603_5%
KSI[0..7] +3VLP R219
31 KSI[0..7] 2 2 2 2 1 1 0625-3 Ra
@ R921
KSO[0..16] 0802-12 0_0402_5% Reserve for EMI please close to U34 R225
100K_0402_1%~D
31 KSO[0..16]
1 2
0802-12 AD_BID0

1
0226-24

2
1 @
Pin J6 is VCC_0 : nvPRO@
Power supply for 51ON power management 20K_0402_1% Rb R225 C283

M12
K12

B11
240K_0402_5%~D .1U_0402_16V7K~D

K7
J7

J4
J6
U34 SD034200280 2

1
D D

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
vPRO@ 0706-7
Analog Board ID definition, Solve 8 beep issue
17,41,8 PM_SLP_S0# M2 M9 KB_LED_PWM 31
L2 GA20/GPIO00 INVT_PWM/PWM0/GPIO0F M8 Please see page 4.
8 KB_RST# KBRST#/GPIO01 BEEP#/PWM1/GPIO10 BEEP# 21
M3 M10
24,8 SERIRQ SERIRQ# FANPWM0/GPIO12 AC_PRESENT 8
17,24,7 LPC_FRAME# K4 N10 SYSTEM_FAN_PWM 32
@EMI@ MC284 N3 LFRAME# ACOFF/FANPWM1/GPIO13
17,24,7 LPC_AD3 LAD3
22P_0402_50V8J~D 17,24,7 LPC_AD2 M4 PWM Output
2 1 @ MR226 2 1 33_0402_5%~D K5 LAD2 B13
17,24,7 LPC_AD1 LAD1 BATT_TEMP/AD0/GPI38 MEM_TEMP0 32 +3VALW_EC
N4 A13
17,24,7 LPC_AD0 LAD0 LPC & MISC BATT_OVP/AD1/GPI39 B12
FAN_TEMP0 32
ADP_I/AD2/GPI3A ADP_I 35,36
N5 AD Input A12 AD_BID0
7 CLK_PCI_LPC PCICLK AD3/GPI3B
17,23,24,25,8 PLT_RST# PLT_RST# M5 E7
PCIRST#/GPIO05 AD4/GPI42 SKIN_TEMP0 32
+3VALW_EC R221 2 1 100K_0402_5%~D EC_RST# K13 D7 VCOUT0_PH# @ R922 1 2 10K_0402_5%~D
N6 ECRST# SELIO2#/AD5/GPI43 SKIN_TEMP1 32
8 EC_RUNTIME_SCI# SCI#/GPIO0E
C285 2 1 .1U_0402_16V7K~D 24,8 PM_CLKRUN# M6 24 SENSOR_HUB_WAKE# R232 2 1 10K_0402_5%~D
CLKRUN#/GPIO1D B10
DAC_BRIG/DA0/GPO3C A9 ACOFF LCD_TEST 19 ROTATION_SW# R233 2 1 10K_0402_5%~D
EN_DFAN1/DA1/GPO3D ACOFF 36
DA Output A10
IREF/DA2/GPO3E EC_ENVDD 19,29,30
KSI0 D9 B9 ROTATION_SW#
KSI0/GPIO30 DA3/GPO3F ROTATION_SW# 20
KSI1 E12
+3VNS_PWR KSI2 E13 KSI1/GPIO31
KSI3 D12 KSI2/GPIO32 D6 EAPD#
KSI3/GPIO33 PSCLK1/GPIO4A EAPD# 21
KSI4 D13 E6
KSI4/GPIO34 PSDAT1/GPIO4B PCH_PWROK_EC 32
KSI5 C12 E5
KSI6 C13 KSI5/GPIO35 PSCLK2/GPIO4C D5 EC_SMB_CK4 19
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D EC_SMB_DA4 19
KSI7 D10 A5 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 32
2

@ Q352A KSO0 J13 B5 TP_DATA TP_DATA 32

KSO1 J12 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 2 1 ECAGND
PCH_SMLCLK 6 1 KSO2 H12 KSO1/GPIO21 C286 100P_0402_50V8J~D
I2C0_SCK 8 KSO2/GPIO22
KSO3 H13 B1 EC_BATT_PRS# 35,36 RP21
DMN66D0LDW-7_SOT363-6~D KSO4 H10 KSO3/GPIO23 SDICS#/GPXIOA00 A1 4 5
KSO4/GPIO24 SDICLK/GPXIOA01 1.05VS_PG_EC 32
KSO5 H9 C1 USB1_PWR_EN_EC 3 6
KSO6 G9 KSO5/GPIO25 Int. K/B SDIDO/GPXIOA02 C2
HDA_SDO 7
LID_SW_IN# 2 7
KSO6/GPIO26 Matrix SDIDI/GPXIOD00 VCIN0_PH 32
5

KSO7 G10 SPI Device Interface VOLUME_DOWN_SW# 1 8

KSO7/GPIO27 +3VALW_EC
C KSO8 G13 C
PCH_SMLDATA @ Q352B 3 4 KSO9 G12 KSO8/GPIO28 J2 USB1_PWR_EN_EC 100K_0804_8P4R_5%
I2C0_SDA 8 KSO9/GPIO29 GPIO5C MOSI USB1_PWR_EN_EC 27
KSO10 F13 K2 PM_SLP_A# 17,29,30,8
DMN66D0LDW-7_SOT363-6~D KSO11 F12 KSO10/GPIO2A GPIO5B MISO M1 USB0_PWR_EN_EC RP22
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 USB0_PWR_EN_EC 27
KSO12 F10 N2 LID_SW_IN# VOLUME_UP_SW# 4 5
KSO12/GPIO2C GPIO5A SPICS# LID_SW_IN# 20 +3VALW_EC
KSO13 F9 EC_ON_CTRL# 3 6 +3VLP
KSO14 E10 KSO13/GPIO2D USB0_PWR_EN_EC 2 7
KSO15 E9 KSO14/GPIO2E B6 ACOFF 1 8
KSO15/GPIO2F CIR_RX/GPIO40 MOTOR_EN# 28
KSO16 E8 B7 TABLET_MODE
D8 KSO16/GPIO48 CIR_RLC_TX/GPIO41 B4 TABLET_MODE 21 100K_0804_8P4R_5%
+3VS 8 PCH_SUSWARN# KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 USB0_CTL1 27
A4 BATT_LED_COLOR_W 28
BATT_CHGI_LED#/GPIO52 B3 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 31
19,35,36 EC_SMB_CK1 EC_SMB_CK1 A8 GPIO A3 BATT_LED_CTRL# 28
R976 1 2 4.7K_0402_5%~D PCH_SMLCLK EC_SMB_DA1 A7 SCL0/GPIO44 BATT_LOW_LED#/GPIO54 A2 USB1_DET_EC#
19,35,36 EC_SMB_DA1 SDA0/GPIO45 SUSP_LED#/GPIO55
R977 1 2 4.7K_0402_5%~D PCH_SMLDATA PCH_SMLCLK B8 SM Bus B2
19,28,32,7 PCH_SMLCLK SCL1/GPIO46 SYSON/GPIO56 5VA_EN 29
R978 1 2 4.7K_0402_5%~D TP_DATA 19,28,32,7 PCH_SMLDATA PCH_SMLDATA A6 H5 DSP_PD# 20 ACIN C1116 2 1 100P_0402_50V8J~D
R979 1 2 4.7K_0402_5%~D TP_CLK SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 N1
AC_IN/GPIO59 PM_SLP_S4# 17,42,8
EC_ON C1117 1 2 .1U_0402_16V7K~D

J5 D4
17,29,30,40,8 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# 8
EC_SLP_S5# N9 D1 USB0_DET_EC#
L13 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 D2
7 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXIOA05 VCIN1_PH 35
35 PS_ID K6 E2 H_PROCHOT_EC H_PROCHOT_EC 35
+3VALW_EC N7 LID_SW#/GPIO0A EC_SWI#/GPXIOA06 E4 VCOUT0_PH#
8 EC_WAKE_SCI# SUSP#/GPIO0B ICH_PWROK/GPXIOA07 VCOUT0_PH# 29
M7 GPO E1
32 KB_INT# PBTN_OUT#/GPIO0C BKOFF#/GPXIOA08 BKOFF# 19
N8 GPIO F4
8 SLP_WLAN# EC_PME#/GPIO0D WL_OFF#/GPXIOA09 EN_WLANPWR# 30
@ R604 1 2 10K_0402_5%~D WAKE_PCH# 27 USB_ILIM_SET
K8 F2 PCH_PWR_EN 2 1
PM_SLP_SUS# 29,30,8
M11 EC_THERM#/GPIO11 GPXIOA10 F1 HWPG R1249 43.2K_0402_1%
32 SYSTEM_FAN_FB FAN_SPEED1/FANFB0/GPIO14 GPXIOA11
VOLUME_UP_SW# N11
20 VOLUME_UP_SW# FANFB1/GPIO15
K10
17 EC_TX EC_TX/GPIO16
K9 F5 ACIN ACIN 35,36 AC_IN MEM_TEMP0 C1245 1 2 1000P_0402_25V8J
17 EC_RX N12 EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 G1
21,22 AUD_MUTE_EC# EC_ON EC_ON 29 ALW_PWR_EN VCC_0 power plane
AUD_MUTE# : Internal PU on Codec Chip (+3VS) M13 ON_OFF/GPIO18 ENBKL/GPXIOD02 G5 EC_ON_CTRL# SKIN_TEMP0 C1251 1 2 1000P_0402_25V8J
8 SUSACK# PWR_LED#/GPIO19 GPXIOD03 ON/OFFBTN#
WAKE_PCH# L12 GPI H1
25,8 WAKE_PCH# NUMLED#/GPIO1A GPXIOD04 USB1_CTL1 27
G4 Win8_INT SKIN_TEMP1 C1252 1 2 1000P_0402_25V8J
GPXIOD05 Win8_INT# 19
H4 PBTN_OUT# 8
GPXIOD06 H2 EC_PECI 1 2 FAN_TEMP0 C1253 1 2 1000P_0402_25V8J
+3VALW_EC Deep S3 support VOLUME_DOWN_SW# J1 GPXIOD07 R240 43_0402_5%~D
H_PECI 5
B Default (No Function) 20 VOLUME_DOWN_SW#
1 2 EC_CRY2 K1 XCLKI GPIO5D L1 +V18R B
25,8 SUSCLK_R XCLKO GPIO5E V18R
R229 2 1 1K_0402_5% EC_SMB_CK1 @ R253 1
AGND

R230 2 1 1K_0402_5% EC_SMB_DA1 0_0402_5%

GND
GND
GND
GND
GND
2

R1386 2 1 10K_0402_5%~D EC_SLP_S5# 1 C293

4.7U_0603_6.3V6K~D Only for Debug using
R607 MC654 KB9012BF-A3_LFBGA128 2 @ SW2
J8
J9
N13
J10
G2

A11

100K_0402_5%~D 20P_0402_50V8J~D
2 20mil L44 3 1 PBTN_SW#
1

ECAGND 2 1 4 2
FBMA-L11-160808-800LMT_0603
T3AL-24S-Q-T/R +3VS
D114
1 2 EC_SLP_S5#
17,8 PM_SLP_S5# 0806-15 HW PWR GOOD

1
SDMK0340L-7-F_SOD323-2~D R930
10K_0402_5%~D

2
R935
D83 1 2 +3VALW_EC
BAT54CW_SOT323-3 nvPRO@
3 100K_0402_5%~D USB0_DET_EC# R931 2 1 0_0402_5%~D HWPG
29,41,8 APOWER_OK HWPG 32
1 +3VLP @ R1133 2 1 0_0402_5%
27 USB0_DET# 42 1.2V_DDR_PWROK
H_PROCHOT# Control citcuits need place close to CPU and VR 2

+3VLP @ R934 2 1 0_0402_5%

40 1.8V_DDR_PWROK
1

R1156 100K_0402_5%~D R939 U712 40 1.5VS_PWROK @ R982 2 1 0_0402_5%

+3VS 1 2 100K_0402_5%~D
+3VALW_EC
1 5
NC VCC
43 VR_HOT#
2

USB1_DET_EC#
1 USBCHG_DET_PWR_EN# 2
IN A
2

C655 D104
A R265 @ .1U_0402_16V7K~D 3 3 4 USBCHG_DET_D 29 17,20,8 PBTN_SW# PBTN_SW# @ R987 2 1 0_0402_5% EC_ON_CTRL# A
2 GND OUT Y
0_0402_5% 1
27 USB1_DET# 1
U635 SN74AUP1G04DCKR_SOT23-5~D C1118
1

SN74LVC1G06DCKR_SC70-5 2 .1U_0402_16V7K~D
2
P

4 2 H_PROCHOT_EC BAT54CW_SOT323-3
35,5 H_PROCHOT# Y A
NC

2
1

R608
1
100K_0402_5%~D
Security Classification Compal Secret Data Compal Electronics, Inc.
C656 2011/06/02 2013/10/28 Title
Issued Date Deciphered Date
47P_0402_50V8J~D
P33-EC ENE-KB9012
1

2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 33 of 49
5 4 3 2 1
 5 4 3 2 1

D D

+5VALW
NVDC B+ +5VALW: TDC:3.91A
DC IN CHARGER +3VALW: TDC:2.78A
BQ24715 TPS51285
+3VALW
Page 36 Page 37

+1.8VS: TDC:10.5mA +1.8VS

TLV62150
Page 40
Battery
(2S2P)

C C

+1.5VS: TDC:84.7mA +1.5VS

TLV62150 Page 40

+1.05VA: TDC:3.754A +1.05VA

TPS51362 Page 41

+1.35V_DDR: TDC:4.214A
+1.35V_DDR
+0.675VS: TDC:0.7A
B
G5616 +0.675VS B

Page 42

+VCC_CORE +VCC_CORE
TDC: 9A
TPS51622
Page 43 44

http://eloy-motherboards.blogspot.com

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P29-PWR_Block_Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9261P
Date: Wednesday, August 14, 2013 Sheet 34 of 49

5 4 3 2 1
 A B C D

Note pin definition matching with board file.

Date 12/07

JDCIN1
+3VALW
1 PSID
PSID Part (39.1)
1 2
2 3
3 4 DCIN_GND renew_2012_12_03
4

1
5
5 6 PL101
VIN renew_2013_02_26
L change to 0 PR102
GND1 7 HCB2012KF-121T50_0805
GND2 2.2K_0402_5%
ADPIN 1 2 renew_2013_02_26 PQ101

HCB2012KF-121T50_0805
L change to 0 PR103
PL102

2
33_0402_5%

renew_2012_12_03

1
1 2 1 3 PSID-31 2

0.01U_0402_50V7K

0.01U_0402_50V7K

S
D
1 1
0320 0320 PS_ID 33

100P_0402_50V8J

100P_0402_50V8J
PL104
BLM15AG102SN1D_2P FDV301N-G_SOT23-3

1
PC101

PC102

PC103

PC104
EMI Part (47.1)

G
1
PR104

2
2

2
PR105 10K_0402_1%
100K_0402_1% PSID-2 1 2
+5VALW

1
Renew on 20121212 C
(L chanre 0) PSID-1 2 PQ102
B MMST3904-7-F_SOT323-3

1
E

3
PR106
15K_0402_1% renew_2012_12_03
BATT+ PL105
BATT++ EMI Part (35.33)
Renew to 47.1_ Date 12/07

2
HCB2012KF-121T50_0805
BATT+

1 2 renew_2013-8-13

BATT++

1 0 2
Battery protection: Erp lot6 Circuit
100P_0402_50V8J

100P_0402_50V8J

PL106
1000P_0402_50V7K
1

1
PC106

PC107

PC108

HCB2012KF-121T50_0805
asserts H_PROCHOT# when adaptor is keep DNP in BOM since Dell 45W
0.01UF_0402_25V7K
1

PC105

ESD Part(47.2)
unplugged, keep low for 10ms adaptor has no hiccup mode
2

till SW PROCHOT# is issued by EC

2

@ renew_2012_12_03
PD103 VIN

3.3K_1206_5%~D
2 Renew on 20121212 PESD24VS2UT_SOT23-3~D Renew on 20121212 Other component (37.1) 2

33,35,5 H_PROCHOT#

1
(L chanre 0) (L chanre 0)

PR122
EMI Part (35.33) 33,36 ACIN

1
PR120
Renew to 47.1_ Date 12/07 VIN
2

EC_SMB_CK1 19,33,36 +3VALW 1M_0402_1%

PR109 @ @

3 2
1

1
Note pin definition matching with board file. 100_0402_5%
Date 12/07 JBATT1 1 2 PR123 PR126

2
11 EC_SMB_DA1 19,33,36 1M_0402_1% 10K_0402_1%
GND 10

PQ103B
PR111

2N7002KDWH_SOT363-6
DMN66D0LDW-7_SOT363-6
GND

1
100_0402_5% 0328 5

3
9 1 2 PC115 D @ PR119
9 8 1 2 5

PQ105B

4
8

1
7 CLK_SMB PR113 G 200K_0402_1% @

2N7002KDWH_SOT363-6
7 6 +3VALW

PQ103A
DAT_SMB PR112 100K_0402_1% 1U_0603_10V6K PR121

DMN66D0LDW-7_SOT363-6

2
6 5 BATT_PRS 1 2 1 2 0328 S 1M_0402_1%

4
5

6
4 2

1M_0402_1%
SYS_PRS D
@
4

1
3

PR125
2

PQ105A
100_0402_5% @ PC113

100K_0402_1%

2
3
1

PR124
G @

1
2 1 EC_BATT_PRS# 33,36
PR115
0_0402_5%

0.1U_0402_25V6

2
1 @ PD104 S

1
PESD24VS2UT_SOT23-3~D

2
@
2

Renew on 20121212 renew_2012_12_03

1

(L chanre 0)
ESD Part(47.2)
JBATT battery connector
Renew on 20121218
Adaptor protection: Adaptor protection:
SMART
3

Battery: if battery removed, adaptor only, if CP and IPCC failed, adaptor output 3

Delay adaptor OC H_PROCHOT# then trigger the H_PROCHOT#, =rating 100% and over load 20W
1.GND 2ms while hybrid power
2.GND keep DNP in BOM since battery can not then trigger the H_PROCHOT# by EC
transition be removed by end user
3.BAT_ALERT
4.SYS_PRES 33,36 ADP_I
5.BATT_PRS
6.DAT_SMB 33,35,5 H_PROCHOT#
7.CLK_SMB

1
H_PROCHOT# 33,35,5
8.BATT++ EC_BATT_PRS# PR116
9.BATT++ renew_2012_12_03 10K_0402_1%
renew_2012_12_03
2N7002KW_SOT323-3

PR110

2
1

2N7002KW_SOT323-3
1
PQ106

1 2 2 @ PC114 D
33 VCIN1_PH

PQ104
G 1 2 2
160K_0402_1% G

0.1U_0402_25V6

1
S 1U_0603_10V6K~D
0.01U_0402_16V7K

1
S @ PR118

3
1

100K_0402_1%
110K_0402_1%
PR108

PC112
33 H_PROCHOT_EC

2
PC116

2
@ @
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P35-PWR_DCIN/BATT CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: W ednesday, August 14, 2013 Sheet 35 of 49

A B C D
 5 4 3 2 1

EMI Part (35.33)

Renew to 47.1_ Date 12/07
http://eloy-motherboards.blogspot.com
Renew on 20121213
(Pin1,2 left ,Pin3,4 right)
P1
PL201
PQ201 PR201
VIN HCB2012KF-121T50_0805
1 3 1 4 1 2
D1 D2
2 3

2200P_0402_50V7K
2 4 PL202

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
G S HCB2012KF-121T50_0805
0.01_1206_1%

1
1 2

PC204

PC205
D CSD87312Q3E_SON8-4 D

PC202

PC203
0.1U_0402_25V6

4.02K_0402_1%

2
1

1
PC208

PC209
4.7_0603_5%
PR203
PR202
0.022U_0402_25V7K
2

2
2
Renew on 20121212 CMSRC

CSSN_1
CSSP_1
(L chanre 0)

4.02K_0402_1%
PR206

2
REGN
ACDRV
3.3K_1206_5%~D

PC210 PC211 PC212

VIN

1
1 2 1 2 1 2
1

PR223

RB751V-40_SOD323-2
0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
PR209

100K_0402_1%
Renew on 20130731
for DT mode, Renew on 20121212

2
@ PR238 (L chanre 0)
adaptor loading recovery

499K_0402_1%
2

2
@ 0_0402_5%
1 2 ACOK

PR208

PD201
33,35 ACIN

1
2N7002KW_SOT323-3

CMSRC
PR210

ACDRV
PR226
1 2 VCC 120K_0402_1%
1

D
2
PQ202

33 ACOFF 10_1206_5%

2
1
C G C

1U_0805_25V4Z
PC214
S @
3

2
Renew on 20121212

21
5

1
(L chanre 0) PU201

CMSRC

ACN

PAD
ACOK

ACDRV

ACP
keep DNP in BOM since Dell 45W PC213
1U_0603_10V6K
adaptor has no hiccup mode ACDET 6
ACDET VCC
20 VCC REGN 1 2
1

2
Renew on 20130731 renew_2012_11_30
105K_0402_1%

0.01U_0402_25V7K

Renew on 20121213 7 19 CHG_LX PD202

PR213

33,35 ADP_I IOUT PHASE

1

@ PR239
PC216

BAT54HT1G_SOD323-2
PC220 0_0402_5% renew_2013_02_26
1 2 19,33,35 EC_SMB_DA1
1 2 8 18 CHG_UGATE L change to 0
2
2

1
SDA HIDRV

SIR472DP-T1-GE3_POWERPAK8-5
100P_0402_50V8J @ PR240 PR211
19,33,35 EC_SMB_CK1
1 2 9
SCL BTST
17 BTST 1 2 B+
Renew on 20121212 2.2_0603_5% PC217
Renew on 20121211 (L chanre 0)

PQ203
0_0402_5% B+=6V-8.4V
(Change value according 10 16 REGN CHG_UGATE 4 10U_0805_16V6K

/BATDRV
to TI suggestion) CELL REGN 1 2

LODRV

1
GND
SRN

SRP
PC218 0.047U_0603_25V7M
PC219
Near PL203

3
2
1
CHG_LX 10U_0805_16V6K

11

12

13

14

15
BQ24715RGRR_QFN20_3P5x3P5 1 2
CHG_LGATE

Renew on 20121213

BATDRV
(Pin1,2 left ,Pin3,4 right)

PL203
+VCHGR
PR216
2.2UH_PCMB063T-2R2MS_8A_20%
@ PR224 1 2 1 4
10K_0402_1%
B B
1 2 REGN 2 3

1
PQ205

SI7716ADN-T1-GE3_POWERPAK8-5
Renew on 20121212 Pull high for 3 CELL operation PR220
(L chanre 0) 4.7_1206_5% 0.01_1206_1%
Renew on 20121211

CSON_B
CSOP_B
2N7002KW_SOT323-3
@ (Change value according
PC229

2
1

D to TI suggestion)
1 2 2 4
PQ204
33,35 EC_BATT_PRS# SNUB_CHG
G
0.01UF_0402_25V7K Renew on 20121212

1
S (L chanre 0)
100K_0402_1%

3
1

@ PC221

3
2
1
1000P_0603_50V7K PC227 PC228
PR225

2
Renew on 20121212 1 2 1 2
(L chanre 0)
for LEARN mode disable @ 0.1U_0402_25V6 0.1U_0402_25V6
2

(pulse)
close to IC
PD204
SX34H_SMA2
1 2 EMI Part (35.33)
Renew to 47.1_ Date 12/07
PQ206
+VCHGR AO4407AL_SO8
1 8 BATT+
2 7
3 6
5
10U_0805_16V6K
10U_0805_16V6K

10U_0805_16V6K

4
1
1

1
PC224
PC223

PC225

A A
2
2

PR230
BATDRV 1 2

4.02K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P36-PWR_NVDC_CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 36 of 49

5 4 3 2 1
 5 4 3 2 1

+3VLP

D D

1
PC347 Renew on 20130731

1
1U_0603_10V6K
PR335

2
0_0402_5%
06/05 change to 158K
@

2
PR353 PR316
133K_0402_1% 158K_0402_1%
1 2 1 2

Renew on 20130606 PR352 PR354 Renew on 20130107

191K_0402_1% 100K_0402_1%
1 2 FB_3V 1 2
FB_5V 3&5V_B+
PL304
FBMA-L11-201209-121LMA50T_0805 3&5V_B+
1 2 3/5V_B+

10U_0805_25V6K
B+ Renew on 20121211

PC324
Renew on 20121211 PR311 PR318 (Change value according
(Change value according 3.3K_0402_1% 5.23K_0402_1% to TI suggestion)
2200P_0402_50V7K

10U_0805_25V6K
0.1U_0402_25V6

to suggestion) 1 2 1 2 Renew on 20121219

2
1

Renew on 20121219
PC345

PC343

PC328

B+=6V-8.4V
2

Renew on 20130731 @ PR344

0_0402_5% PU301

1
3VA_EN 1 2 TPS51285BRUKR_QFN20_3X3
29 3VA_EN
21

CS2

VFB2

VREG3

VFB1

CS1
Renew on 20121218 ADD on 20121213 PR348 TP Renew on 20121218
EMI Part(47.1) PQ304 1M_0402_1% @ PR345 0_0402_5%

1
C CSD87330Q3D_SON8-7 1 2 6 20 1 2 PQ305 C
EN_+V5A
+3VALWP EN_+V5A 29

1
2 EN2 EN1 Renew on 20130731 CSD87330Q3D_SON8-7 Renew on 20121211
PR351 2 (Change value according
PL303 8 3VALW_PG 7 19 1 2 to suggestion)
2.2UH_FDSD0630-H-2R2M-P3_8.3A_20% 7 PGOOD VCLK 200_0402_1% PL302
1 2 6 3 7 3.3UH_FDSD0630-H-3R3M-P3_6.6A_20%
+3VALWP 5 LX_3V 8 18 LX_5V 3 6 1 2
Renew on 20121211 4 PR355 SW2 SW1 PC335 5 +5VALWP
(Change value according 2.2_0603_5% PR356 0.1U_0603_50V7K 4
to suggestion) 1 2 BST1_3V1 2 BST_3V 9 17 BST_5V 1 2 BST1_5V 1 2
VBST2 VBST1
1

1
PR312 @ PC318 2.2_0603_5%
150U_B2_6.3VM_R35M

8
4.7_1206_5% 0.1U_0603_50V7K UG_3V 10 16 UG_5V PR313

150U_B2_6.3VM_R35M
1

8
DRVH2 DRVH1

VREG5
1

DRVL2

DRVL1
+
PC326

Renew on 20121213 4.7_1206_5%

VO1
SNUB_3V 2

SNUB_5V 2
VIN
+

PC334
(L change 0)
EMI Part(47.1)

Renew on 20121213
2 (L change 0)

11

12

13

14

15
2
LG_5V

LG_3V
1

1
@ PC333 PC329
680P_0603_50V7K 680P_0603_50V7K
2

2
EMI Part(47.1)
B B
3&5V_B+

1U_0603_10V6K
1

PC342
2
@ PJP304 @ PJP306
1 2 1 2
+3VALWP +3VALW +5VALWP +5VALW
PAD-OPEN 4x4m PAD-OPEN 4x4m

3.3VALWP 5VALWP
TDC 2.78A TDC 3.91A
Peak Current 3.972A Peak Current 5.585A
A
OCP current 4.726A OCP current 6.647A A

Renew on 20121212 Renew on 20121212

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P37-PWR_+3.3/5V_VR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: Wednesday, August 14, 2013 Sheet 37 of 49
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P38-PWR_+3.3V_VR(1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: W ednesday, August 14, 2013 Sheet 38 of 49

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P39-PWR_+3.3V_VR(2/2)
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: Wednesday, August 14, 2013 Sheet 39 of 49

5 4 3 2 1
 A B C D

Renew on 20130731
<Vo=1.5V> VFB=0.8V
@ PR404
0_0402_5%
Vo=VFB*(1+PR407/PR408)=0.8*(1+105K/120K)=1.5V
1 2
17,29,30,33,40,8 PM_SLP_S3#

1
@ PJP409 +1.5VS 1

1 2 +1.5VSP_VIN
TDC 84.7mA
B+ Peak Current 121mA
43x39
OCP setting 1.4A(Fix)

EN_+1.5VSP
10U_0805_16V6K

10U_0805_16V6K
1 1

PC432

PC428
High-Side MOSFET Forward Current Limit
2 2

13

14

15

16

17
PU405
Change 2.2uH after applied.

EN

VOS

PGND

PGND

TP
PL405 PJP410@
1UH_NRS4018T1R0NDGJ_3.2A_30%
12
PVIN SW
1 +1.5VSP_LX 1 2 +1.5VSP 1 2 +1.5VS

22P_0402_50V8J
43x39

100K_0402_1%
4.7_1206_5%

1
11 2

PC429
PVIN SW

1
PR429
PR427

PR422
105K_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M
2
1SNUB_1.5VSP 2

1
10 3

PC426

PC430
TLV62150RGTR_QFN16_3X3
AVIN SW 1.5VSP_FB

2
+1.5VS_FSW

2
Renew on 20130731

1
+1.5VS_SS/TR 9 4
180P_0402_50V8J

SS/TR PG
1

2
PC433

0_0402_5%
PR425

AGND

PR428
120K_0402_1%

680P_0603_50V7K
FSW
DEF

PC427
2 2

FB
2

2
2
@

1
1.5VSP_FB
+1.5VS_FSW
33 1.5VS_PW ROK
EMI Part(47.1)
Need EE conform pin define

Renew on 20130731

@ PR405
0_0402_5%
1 2
17,29,30,33,40,8 PM_SLP_S3#
EN_+1.8VSP

3 3
@ PJP411

1 2
B+
43x39
10U_0805_16V6K

1
13

14

15

16

17

Change 2.2uH after applied.

PC436

PU406
EN

VOS

PGND

PGND

TP

2 PL406 @ PJP412
1UH_NRS4018T1R0NDGJ_3.2A_30%
12 1 +1.8VSP_LX 1 2 +1.8VP 1 2
PVIN SW
+1.8VS

22P_0402_50V8J
43x39
1

1
4.7_1206_5%

1
11 2
PC440
PR433
PVIN SW
PR432

402K_0402_1%

100K_0402_1%

22U_0805_6.3V6M

22U_0805_6.3V6M
2

1
1SNUB_1.8VSP 2

1
10 3

PR437

PC441

PC434
TLV62150RGTR_QFN16_3X3
AVIN SW FB_+1.8VSP <Vo=1.8V> VFB=0.8V
Vo=VFB*(1+PR419/PR420)=0.8*(1+402K/324K)=1.8V

2
@

2
1

+1.8VS_SS/TR 9 4 FSW _+1.8VS

SS/TR PG
PR438
180P_0402_50V8J

AGND

Renew on 20130731 324K_0402_1%

680P_0603_50V7K

+1.8V_DDR
FSW
DEF
1
PC437

PC439
FB

2
1

TDC 10.5mA
2

PR434
2

4
0_0402_5% Peak Current 15mA 4
@
OCP setting 1.4A(Fix)
2
FSW_+1.8VS

FB_+1.8VSP

EMI Part(47.1)
High-Side MOSFET Forward Current Limit
33 1.8V_DDR_PW ROK

Need EE conform pin define

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P40-PWR_+1.5VS/+1.8VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: W ednesday, August 14, 2013 Sheet 40 of 49
A B C D
 5 4 3 2 1

D D

EN_+1.05VS
29 EN_+1.05VS

0.1U_0402_10V7K
1

PC501
1.05V_VREF 2
24

25

26

27

28

29
REFIN2

REFIN

EN
RA

TP
VREF
23 1
GSNS PGOOD APOW ER_OK 29,33,8

C 22 2 PM_SLP_S0# 17,33,8
C
PC502 VSNS LP#
1000P_0402_50V7K
1 2 SLEW 21 3
SLEW MODE
Renew on 20130731
@ PR505 1 2 TRIP 20 4
0_0402_5% TRIP NC PC503
PR506
1 2
+5VALW @ PR508 0_0402_5%
19 5 BST_+1.05VS1 2 1 2 +1.05VA
GND BST PL502 @
PJP501
PC504 5.1_0603_5% .1U_0603_25V7K 0.68UH_PCMC063T-R68MN_15.5A_20%
1 2 1U_0603_10V6K 18 6 SW _+1.05VS 1 2 +1.05VSP 1 2
V5 SW 1 2

JUMP_43X118

1
1 2 +1.05VS_B+ 17 7
B+ PL501 VIN SW
HCB2012KF-121T50_0805 PR507

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
16 8 4.7_1206_5%
VIN SW

PC505

PC506

PC507

PC508
2
2200P_0402_50V7K

2
<BOM Structure> 15 9 SNUB_+1.05V
10U_0805_16V6K

10U_0805_16V6K

0.1U_0402_25V6

VIN SW
1

PGND

PGND

PGND

PGND

PGND
@
PC511

1
PC509
PC513

PC510

PC512

EMI Part (35.33)

Renew to 47.1_ Date 12/10
2

TPS51362RVER_QFN28_4P5X3P5 1000P_0402_50V7K Renew on 20121211

14

13

12

11

10

2
PU501 (Remove @ according to TI suggestion)

B B

EMI Part (35.33)

Renew to 47.1_ Date 12/10
EMI Part (47.1)

+1.05VA +1.05V_M +1.05VA

TDC 3.754A
Peak Current 5.363A
OCP setting 8A(Fix)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P41-PWR_+1.05VA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: W ednesday, August 14, 2013 Sheet 41 of 49

5 4 3 2 1
 5 4 3 2 1

DDR controller(35.3), Support component(35.4)

+0.675VS
PL601
TDC 0.7A
HCB2012KF-121T50_0805
renew_2012_12_03 1
EMI Part(47.1) Peak Current 1A
2
OCP setting 1.2A
@
PJP601
D B+ Renew on 20121213
(Pin1 in ,Pin2 out)
D
1 2 +1.2V_B+
1 2 @
PJP604 Renew on 20121211
JUMP_43X79 Renew on 20121212 2 1 +1.35VP (Change Net name according
B+=6V-8.4V Renew on 20121212 (L chanre 0) VLDOIN_+1.2V +1.35VP to GM suggestion)

10U_0805_16V6K

2200P_0402_50V7K
(Pin1 left ,Pin2 right) PC605 PR601

0.1U_0402_25V6
0.22U_0603_10V7K 2.2_0603_5% 43x39

1
1 2 1 2 BOOT_+1.2V

PC603

PC604
PC602

2
@ PJP603
DH_+1.2V +0.6VSP 1 2

43x39
EMI Part(47.1) SW _+1.2V +0.675VS

10U_0805_16V6K

10U_0805_16V6K
5

1
MDV1528URH_PDFN33-8-5

PC606

PC607
16

17

18

19

20
3.3x3.3 mm
PU601

2
DH

VLDOIN
LX

BST

VTT
21

PQ601
4 PAD
DL_+1.2V 15 1
Renew on 20121213 DL VTTGND
(Pin1 in ,Pin2 out)
PL602 14 2
PJP602

1
2
3
+1.35V_DDR 2.2UH_PCMB063T-2R2MS_8A_20% PR604 PGND VTTSNS
C 2 1 +1.35VP 1 2 7.15K_0402_1% C
2 1 1 2 CS_+1.2V 13 G5616ARZ1U_TQFN20_3X3 3
1 CS GND

5
MDV1524URH_PDFN33-8-5
@
4.7_1206_5%

JUMP_43X118 1U_0603_10V6K PC609

PR605

3.3x3.3 mm
1 2 12 4 VTTREF_+1.2V 1 2
PR606 PC608 VPP VTTREF
5.1_0603_5%

PQ602
330U_B_2.5VM_R9M

330U_B2_2.5VM_R9M

1SNUB_+1.2V 2

4 1 2 VDD_+1.2V 11 5 0.033U_0402_16V7K
1 1 VCC VDDQSNS
+ + +5VALW

VDDQSET
PC610

PC611

PGOOD
1

TON
1
2
3
2 @ 2 PC612

S5

S3
680P_0603_50V7K

1U_0603_10V6K
PC613

+5VALW

2
Renew on 20121210(Change CPN)

10

+1.35VP
PR608
2

+1.2V_FB 1 2
Renew on 20121212
(L chanre 0) 8.06K_0402_1%

+1.2V_TON
EMI Part(47.1) 1 2

33 1.2V_DDR_PW ROK PC614

100P_0402_50V8J
+1.35V_DDR

1
10K_0402_1%
TDC 4.214A Renew on 20121212 PC615

PR610
PR611 (L chanre 0) @ .1U_0402_16V7K

2
B
Peak Current 6.02A 1M_0402_1% B
+1.2V_B+ 1 2
OCP setting 6.48A

2
Renew on 20121206
@ PR613
Renew on 20121213 1 2 S5_+1.2V
17,33,8 PM_SLP_S4#

S3_+1.2V
0_0402_5%

1
Renew on 20130731 PC616
@ .1U_0402_16V7K
VFB = 0.75V

2
Vo=0.75(1+PR608/PR610)=0.75(1+ 8.06/10) = 1.35V
Renew on 20130731
@ PR615
1 2
5 SM_PG_CTRL
0_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P42-PWR_+1.2V_DDR/+0.6VS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: W ednesday, August 14, 2013 Sheet 42 of 49
5 4 3 2 1
 5 4 3 2 1

Renew on 20130604
PL703 (remove jump)
FBMA-L11-453215800LMA90T_2P
1 2
B+ CPU_B+

10U_0805_16V6K

10U_0805_16V6K

10U_0805_16V6K

10U_0805_16V6K
renew_2012_12_03

15U_B2_25VM_R100M
1
EMI Part(47.1)

1
+

PC705
PC701

PC702

PC703

PC704
2

2
2 change to SGA00007G00
(Modify on 20121206_D2 to B2)
D Renew on 20121221 D

Renew on 20121213
VREF (Change value according
to TI suggestion) Renew on 20121213
100K_0402_1%_NCP15WF104F03RC (Change value according

1
IMON to TI suggestion)
Acoustic(37.2)

1
4700P_0603_50V7K

9.31K_0402_1%
PH701
1

1
75_0402_1%

75_0402_1%

1.3M_0402_1%
PR701

PC707

348K_0402_1%

PR704

PR745

PR706
PR703
2

2
@

2
@ DC load line: 2m-OHM
2

2
0.1U_0402_25V6
Renew on 20121210
TDC: 9A

2
(Change value according

renew_2012_12_03
1
10K_0402_1%

to TI suggestion)
1 IccMax: 25A
PR709

SLEWA OCP-I B-RAMP F-IMAX O-USR

OCP: 34A

1
PC709

1
39K_0402_1%

150K_0402_1%

150K_0402_1%

150K_0402_1%
PR711

PR712

PR713
Swithing Freq : 1MHz
2
1
39K_0402_5%

PR710
2
PR714

2
2
Renew on 20121212
2

20121221 (according to documen

t"503160_503160_SB_ULT_PDDG_1.1")
CPU_B+ CPU_B+
1 2

PR717 EMI Part(47.1)

10K_0402_1%
PC710
16

15

14

13

12

11

10

PU701 1000P_0402_50V7Krenew_2012_12_03
1 2
VBAT

THERM
SLEWA

B-RAMP

F-IMAX
IMON

OCP-I

O-USR

C B value: 3435K C
PC725
CSP1 17 8 0.1U_0402_25V6 PH702
CSP1 VR_ON VR_ON 10 PR702
1 2 10K_0402_1%_TSM0A103F34D1RZ
CSN1 18 7 SKIP# renew_2012_12_03 1 2 CSP1
CSN1 SKIP#

0.1U_0402_25V6
PC726

0.082U_0402_16V7K
19 6 PWM1 2200P_0402_50V7K 2.4K_0402_1%
CSN2 PWM1

1
1 2
20 5 +5VS
CSP2 PWM2

1PC708
PR721 @ @

1 PC718
21 4 1 2
+3VS

(Change value according

PU3 N/C 75_0402_1% Renew on 20130731 @PR720
@ PR720

2
22 3 IMVP_VR_PG 10,32 75_0402_1%
N/C PGOOD

1
14K_0402_1%

3.01K_0402_1%
to TI suggestion)
Need EE conform pin define @PR718
@ PR718

Renew on 20121210
2

1
PR707
23 2 SKIP# 1 2 SKIP#1

2
11 VSSSENSE GFB VDD

PR708
@ PR723
@PR723
VR_HOT#

24
ALERT#

1 VR_SVID_DAT 1 2 0_0402_5%
DROOP

+3VS

2
VFB VDIO
COMP

10 VCCSENSE
VREF

Renew on 20121210
VCLK
GND

PAD

2
V5A

1.91K_0402_1% (Add @ on PC718 and

2
TPS51622RSM_QFN32_4X4 change value on 708
according to TI suggestion)
25

26

27

28

29

30

31

32

33

CSN1
PR725

1
Renew on 20121210 CSD97374CQ4M_SON8_3P5X4P5
DROOP (Add @ according to TI suggestion) 1 2 PC713
+3VS
1U_0603_10V6K

COMP 2.2U_0603_10V7K

2
1
PC715

@ PC714 1_0603_5%
1 2 1 2 PC711 PR715 PU702
PR726 VR_SVID_ALRT# 0.1U_0402_25V6 0_0603_5% 5 1 PL701 +VCC_CORE
2

100P_0402_50V8J 3.3K_0402_1% VREF 1 2 1 2 6 VIN SKIP# 2 2 3

Renew on 20121210 VR_SVID_CLK BOOT_R VDD 3
PGND1
1
0.33U_0603_10V7K

PR727 (Change Value according to TI suggestion) 7 4 LX_DGPU 1 4

8 BOOT VSW
PC717

1 2 VR_HOT# 33 PWM1
9 PWM
2

10K_0402_1% Need EE conform pin define PGND2 0.15UH_MMD06CZER15MG_37A_20%

PR744
B PC724 B
1 2 1 2
1 2 1 2
4.7K_0402_1% 1500P_0402_7K PR731 PR719
1 2 PC712 4.7_1206_5%
renew_2012_12_03 +5VALW 680P_0603_50V7K Renew on 20121213
10_0603_1%
1

PC720 EMI Part(47.1)

1U_0603_10V6K
2

+1.05VS_VCCST

renew_2012_12_03
130_0402_1%
1

1
56_0402_1%

110_0402_1%

PC721
PR735

PR736

PR737

0.1U_0402_25V6
2

@
2

VR_SVID_CLK
10 VR_SVID_CLK
10 VR_SVID_ALRT# VR_SVID_ALRT#

VR_SVID_DAT
10 VR_SVID_DAT

from processor

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P43-PWR_CPU_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: Wednesday, August 14, 2013 Sheet 43 of 49

5 4 3 2 1
 5 4 3 2 1

for VCORE:1 phase ---> reserved 30pcs, 15-pcs is OK after fine-tune

D D

+VCC_CORE

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC801 PC802 PC803 PC804 PC805 PC806 PC807 PC808 PC809 PC810
@ @ @ @

2
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC811 PC812 PC813 PC814 PC815 PC816 PC817 PC818 PC819 PC820
@ @ @ @
2

2
C C
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PC821 PC822 PC823 PC824 PC825 PC826 PC827 PC828 PC829 PC830
@ @ @ @ @
2

2
H0.85

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P44-PWR_PROCESSOR_DECOUPLING
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-A161P
Date: Wednesday, August 14, 2013 Sheet 44 of 49

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Title
P45-LED converter TPS61181A

Size Document Number Rev

A00

Date: Wednesday, August 14, 2013 Sheet 45 of 49

5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.

X XX XXX XX'XX/XX Compal_XX XXXXX Change PRXX from Xohm to XXKohm.

D D

36 20121008 Compal_Power create one more input cap for TPS51362 Vin add PC513_10U_0805_16V6K for TPS51362's input

34 20121012 Compal_HW create one more resistor for TPS62130 enable pin add PR342_2.2K_0402_5%

34 design change, delete PU301~PU305, TPS62130 and related components,

create PU301, TPS51225 for 3.3V and 5V power rails
35 20121018 Compal_Power

36

36 20121018 Compal_Power design change, delete PU401, PU402, TPS62140 and TPS62150
and related components,
create PU401and PU402, SY8003D for 1.5V and 1.8V power rails

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P46-PWR_PIR-1
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: Wednesday, August 14, 2013 Sheet 46 of 49

5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 2

Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
D D
X XX XXX XX'XX/XX Compal_XX XXXXX Change PRXX from Xohm to XXKohm.

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P47-PWR_PIR-2
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-A161P
Date: Wednesday, August 14, 2013 Sheet 47 of 49

5 4 3 2 1
 A B C D E

+3V_PCH +3VS

2.2K 2.2K @0-ohm 10K 10K

SMBUS Address [0x9a]

+3VS
AP2 SMBCLK PCH_SMBCLK
DMN66D0
1 AH1 SMBDATA PCH_SMBDATA XDP 1

DMN66D0
+3V_PCH @0-ohm

499 499

PCH AN1 SML0CLK

AK1 SML0DATA NFC [0x28]
+3VS
+3V_PCH

2.2K 2.2K 4.7K 4.7K

+3VNS_PWR
@0-ohm
PCH_SMLCLK PCH_SMLDATA
+3VS 0-ohm
2 AU3 SML1CLK 2.2K 2.2K 2

DMN66D0 ALS
AH3 SML1DATA [0x29]
DMN66D0
0-ohm
@0-ohm @0-ohm

NC mos
@ @0-ohm
DMN66D0
+3VNS_PWR @0-ohm
DMN66D0
@
Magnetic 0x3C
G3 B5
Acceleration 0x32
+3VNS_PWR +3VS I2C0_SCK_SNR
@0-ohm
e-Compass +
I2C0_SDA_SNR F3 C5
Sensor HUB Accelerometer
CS@ 2.2K CS@ 2.2K @ 2.2K
@ 2.2K
[0xBA]
I2C
I2C0_SCK @ 0-ohm +3VS Gyro Sensor
F3

F2 I2C0_SDA
[0xD2]
3 3
@ 0-ohm 4.7K 4.7K
B8 A6

@ 0-ohm
I2C0_SCK_DSP 27
B8 PCH_SMLCLK 13
I2C0_SDA_DSP26 ALS 5505
+3VS_TP +3VS_TS A6 PCH_SMLDATA 12 Keyboard
@ 0-ohm

4.7K 4.7K @ 4.7K @ 4.7K E5 EC_SMB_CK4 11

PCH D5 EC_SMB_DA4 10 Panel

I2C1_SCK @ 0-ohm +3VALW_EC

F1 I2C1_SCK_TP KBC
G4 I2C1_SDA I2C1_SDA_TP
Touch Pad 9

@ 0-ohm 1K 1K 8 Charger [0x12]

@ 0-ohm
I2C1_SCK_TS 100-ohm
A8 EC_SMB_CK1 7
Touch Panel BATTERY
4
I2C1_SDA_TS
A7 EC_SMB_DA1 6 CONN
[0x16] 4

@ 0-ohm
100-ohm

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P48-SMBus Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A00
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, August 14, 2013 Sheet 48 of 49
A B C D E
 5 4 3 2 1

[AC in] [Battery only, AC absent] Discrete Power On Sequence

Vin
EC pay attention timing [AC in] [Battery only, AC absent]
ACIN Ta
B+
ITEM Measure Point Time ITEM Measure Point Time
B+ Tb Ta VIN To ACIN To
+3VLP Tc Tb VIN To B+ To
+3VLP Tc
1ns < Th < 4s Tc B+ To +3VLP Tc B+ To +3VLP
EC Input PBTN_SW#
EC Output EC_ON Td Td +3VLP To EC_ON Th PBTN_SW# Low pluse width N/A
EC Output EC_ON Td Te EC_ON To +3VALW Td PBTN_SW# To EC_ON
Tf To Te EC_ON To +3VALW
D
Te
Tg To Tf To D

Th PBTN_SW# Low pluse width Tg To

+3VALW Te
+3VALW
1ns < Th < 4s
EC Input PBTN_SW#

ITEM Measure Point Time

T1 PM_SLP_SUS# To +1.05VA
T2 PM_SLP_SUS# To +3V_PCH
EC Output PM_SLP_SUS#
T1 T3 PM_SLP_SUS# To +5VA
+1.05VA T4 PM_SLP_SUS# To +5VDX_WALKPORT
T2
T5 +3V_PCH To PCH_DPWROK
+3V_PCH
T3 T6 +3V_PCH To PCH_RSMRST# >10ms
+5VA T7 PCH_RSMRST# To PCH_SUS_PWR_DN <200ms
T4
T8 PCH_RSMRST# To AC_PRESENT 0~90ms
+5VDX_WALKPORT
T5 T9 PBTN_OUT# To Low pluse width
20 mS EC Output PCH_DPWROK T10 PCH_RSMRST# To SUSCLK >100ms
T6
T11 SUSCLK To PM_SLP_S5#
EC Output PCH_RSMRST#
T7 T12 PM_SLP_S5# To PM_SLP_S4# <30us
EC Input PCH_SUS_PWR_DN T13 PM_SLP_S4# To SYSON
T8 < 90ms
T14 PM_SLP_S4# To +1.2V_DDR
0 mS EC Output AC_PRESENT
20 mS T15 +1.2V_DDR To 1.2V_DDR_PWROK <10ms
16ms < T9 < 4s
110 mS EC Output PBTN_OUT# T16 PM_SLP_S4# To +1.8V_DDR
C Minimum duration of PWRBTN # assertion = 16mS after SUSCLK stable C
T10 T17 +1.8V_DDR To 1.8V_DDR_PWROK <10ms
PCH Output SUSCLK T18 PM_SLP_S4# To PM_SLP_S3# <30us
T11
T19 PM_SLP_S3# To SUSP#
PCH Output PM_SLP_S5#
30us < T12 T20 PM_SLP_S3# To +5VS
PCH Output PM_SLP_S4# T21 PM_SLP_S3# To +3VDX
T13
<10 mS after SLP_S5 T22 PM_SLP_S3# To +3VS
EC Output SYSON
T14 T23 PM_SLP_S3# To +1.8VS
+1.2V_DDR T24 +1.8VS To ALL_VS_PG
T15
T25 PM_SLP_S3# To +1.5VS
1.2V_DDR_PWROK
T16 T26 +1.5VS To 1.5VS_PWROK
+1.8V_DDR T27 PM_SLP_S3# To +1.05VS
T17
T28 +1.05VS To 1.05VS_PG >1ms
1.8V_DDR_PWROK
T29 PM_SLP_S3# To MPHY_PWREN
T18 30us < T T30 MPHY_PWREN To +1.05VDX_MODPHY
PCH Output PM_SLP_S3# T31 ALL_VS_PG To HWPG
T19
10~20 mS after SLP_S3 T32 HWPG To PCH_PWROK >5ms
EC Output SUSP#
T20 T33 1.05VS_PG To 1.05VS_VCCST_PG
+5VS T34 1.05VS_VCCST_PG To VR_ON <0.1us
T21
T35 VR_ON To +VCC_CORE <2.5ms
+3VDX
T22 T36 +VCC_CORE To IMVP_VR_PG <7.5ms
+3VS T37 PCH_PWROK To SM_PG_CTRL
T23
T38 SM_PG_CTRL To +0.6VS <35us
+1.8VS
T24 T39 HWPG To PCH_PWROK_EC 5~99ms
ALL_VS_PG T40 PCH_PWROK_EC To SYS_PWROK
T25
T41 SYS_PWROK To PCH_PLTRST# >1.06ms
+1.5VS
T26 T42 HWPG To PCH_PLTRST# >5~99ms
B 1.5VS_PWROK B
T27
+1.05VS
T28
1.05VS_PG
T29
PCH Output MPHY_PWREN
T30
+1.05VDX_MODPHY
T31
EC Input HWPG
T32 0ms < T
PCH Input PCH_PWROK
T33
PCH Input 1.05VS_VCCST_PG
T34
PCH Output VR_ON
T35
+VCC_CORE
T36
IMVP_VR_PG

PCH Output SM_PG_CTRL

T37

T38
http://eloy-motherboards.blogspot.com
+0.6VS
T39 5~99ms
80 mS after HWPG
EC Output PCH_PWROK_EC
T40 0ms < T
PCH Input SYS_PWROK
T41
PCH Output PCH_PLTRST#
T42 5~99ms < T
PCH Output PCH_PLTRST#
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/08/25 Deciphered Date 2012/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P49-Power Sequence
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A00
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, August 14, 2013 Sheet 49 of 49
5 4 3 2 1