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Generalized Discontinuous DC-link Balancing

Modulation Strategy for Three-level Inverters


Lars Hellet , Stig Munk-Nielsent and Prasad Enjetit
t Aalborg University, Institute of Energy Technology $Texas A / M University, Department of Electrical Engineering
Pontoppidanstraede 101, DK-9220 Aalborg East, Denmark College Station, TX 77840 USA
Phone +45 9635 9287 Email : 1hQiet.auc.dk www.iet.auc.dk Email : enjeti@ee.tamu.edu

Abstract- T h i s p a p e r presents a new generalized dis-


continuous space-vector m o d u l a t i o n a p p r o a c h applicable t o
N e u t r a l Point C l a m p e d ( N P C ) inverters. B y t h e proposed
m o d u l a t i o n s c h e m e t h e DC-link voltage c a n b e actively
controlled t o m a i n t a i n a s t a b l e n e u t r a l point even if un-
balanced loading of t h e DC-link capacitors o c c u r d u e t o
e.g. nonlinear loads containing even harmonics. T h e maxi-
m u m u n b a l a n c e for which t h e m o d u l a t i o n scheme a r e a b l e
t o c o m p e n s a t e is theoretically investigated a n d found t o b e
a function of b o t h load angle,,modulation index a n d o u t p u t
power level. T h e p r o p o s e d m o d u l a t i o n m e t h o d is c o m p a r e d
t o conventional m o d u l a t i o n schemes w i t h regard t o b o t h
switching losses a n d wave f o r m quality. For t h e s a m e num-
b e r of switchings, t h e p r o p o s e d m o d u l a t i o n scheme offers
u p t o 25% lower switching losses t h a n conventional mod-
ulation schemes while m a i n t a i n i n g t h e s a m e o u t p u t wave A
form quality. T h e functionality of t h e m o d u l a t i o n scheme
is validated by simulation results.

VDC
I. INTRODUCTION
Since the introduction of the Neutral Point Clamped
(NPC) inverter [l],c.f. Fig. l a , this inverter has mainly
been applied for high voltage- and low switching frequency
power conversion applications. However, progressing ad-
C
vance in computational power processors and in solid state
switching devices, such as the IGBT, makes the NPC in-
Fig. 1. Three-level NPC inverter topologies. a ) Conventional NPC
verter applicable also in high switching frequency applica- inverter [l]. b) Modified NPC-inverter [IS].
tion [2, 31. Considering low switching frequency applica-
tions (fsw < 1 kHz), a lot of research have been concerned
about calculating optimal switching patterns to eliminate
low order harmonics in the output voltage [4, 5 , 61. As Several methods have been proposed t o solve the voltage
the switching frequency increases, research on harmonic unbalance problem, among these, the use of separate DC
voltage elimination recedes while problems like reduction voltage sources [ll]and active voltage regulators [la]. Un-
of switching losses becomes more urgent [7]. A simple fortunately, these solutions clearly add t o the complexity
method t o reduce the switching losses of a three-level con- of the system and is not suitable in many applications
verter is t o employ the discontinuous modulation schemes
[13]. In [14] and [15],two different voltage balancing tech-
niques were proposed, where the redundancy of the switch
known from conventional two-level voltage source invert-
ers (VSI) [8]. However, a non-modified adoption of these state vectors were attributed t o stabilize the DC-link volt-
discontinuous two-level VSI modulation schemes is only age within each switching period. However, these methods
functional when the voltage-levels in the three-level con- are incapable of adopting the features of the discontinuous
verter is built from separate DC-sources [9]. When series modulation schemes. This paper presents a new gener-
capacitors are used t o divide the DC-link voltage, three- alized discontinuous DC-link balancing modulation strat-
level inverters (and multi-level inverters in general) have egy for NPC-inverters. The proposed modulation scheme
a DC-link voltage unbalance problem due t o the following is based on the space-vector approach and provides the
reasons: following features:
Unequal capacitor values due t o manufacture toler- Discontinuous modulation with the clamping period
ances. centered a t the peak of t h e phase current.
Unequal loading of the capacitors due to unintended DC-link voltage balancing, even with unequal loading
switching delays. of the DC-link capacitors or different capacitor values.
Unequal loading of the capacitors due t o e.g. non-linear No need for additional hardware t o perform the DC-link
loads containing even order harmonics [lo]. balancing.

0-7803-7156-9/02/$10.000 2002 IEEE - 359 - PCC-Osaka 2002


Fig. 2. Switch combinations for the three-level inverter.

The paper first reviews the topologies of NPC-type in-


vert.ers and then summarizes the space-vector analysis ap-
plied for three-level inverters. Then the proposed modu-
lation scheme is presented and compared t o conventional
schemes, both with regards t o switching losses and wave
form quality. The proposed modulation scheme is vali-
dated, by simulation results.
v .++
11. NEUTRAL POINT CLAMPED VSI
A . C o n f i g u r a t i o n s of t h e NPC i n v e r t e r
Fig. l a shows the conventional three-level NPC in-
verter proposed by [l].In the conventional NPC inverter
topology, each of the switches SlA..S4C and the diodes V..+
+-i
D 1 A . . D 2 C only have t o block half the DC-link voltage.
Hence, the conventional NPC is well suited for high vol- Fig. 3. The space vector hexagon for the three-level VSI
tage applications. A topology derived from the conven-
tional NPC inverter is shown in Fig l b and was pro-
posed by [16]. Compared t o the conventional NPC in- the same output voltage (provided that the neutral point
verter, the salient features of this topology are: Lower voltage is balanced) but with regards to the current flow-
conducting losses in the high modulation range, due to ing to/from the neutral point these two switch states be-
the fact that only one semiconductor device provides the haves in the opposite manner. Hence, the selection among
path to the upper and lower DC-bus bar. Secondly, in- the redundant switch states has a vital influence on the
telligent half bridge modules like the Skiip-pack modules neutral point potential and can actively be used to con-
from SEMIKRON are directly applicable to this configu- trol/reestablish the neutral point voltage.
ration. Although the modified NPC inverter only switches
half the DC-link voltage (if modulated properly), the up- 111. VECTORANALYSIS OF THE SWITCHING
per and lower switches still need t o have the ability t o COMBINATIONS
block the total DC-link voltage. Hence this topology is For the purpose of space vector modulation, the output
not suited in high voltage applications. The modulation
voltage references vi,v;j and I J and
~ the output currents
scheme proposed in this paper is directly applicable for i ~ iB, and ic are transformed into the complex space
both types of inverters in Fig. 1.
vector plane by the following trarisformation:
B. V a r i a t i o n of t h e neutral p o i n t potential
According t o Fig. l a an excessive high voltage may
be applied to the switching devices if the neutral point
N varies from the center potential of the DC-link. Fur-
r, = 2 (iA + iB . e j . 9 + ic .e j . q 1 (2)

ther, both NPC type inverters in Fig. l may be unable to Applying (1) on the switch combinations in Fig. 2, the
synthesize the reference voltage if too large neutral point well known space vector hexagon in Fig. 3 is obtained.
voltage variations occur. By inspection of Fig. 1 it ap-
pears that the NPC inverter has 27 legal switching states. A . S e c t o r location
These switching states are summarized in Fig. 2 and it As indicated in Fig. 3 the space vector hexagon is
appears that with regards to output voltage, several of divided in six main sectors (O..V) and 24 sub sectors
these switch states are redundant (in pairs). For instance, (Oa..Vd). The first step in the space vector approach
the switch combinations V O - - and V+OO produce exactly is to determine the sector location. Due t o the symmetry

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Solving for the voltage reference vector located in sector
Xb gives:
61b = 2 - fi . M . cos(&) - M . sin(&)
62b = fi.M . COS(A,)- M . sin(A,) - 1 (8)
636 = 2 . M .sin(&)
Solving for the voltage reference vector located in sector
X, gives:
61, = 1 - 2 . M .sin(A,)

Fig. 4. The space vector hexagon for the three-level VSI.


6zc = 2 . M . s i n ( As 3
-- +l (9)

= 2.M.sin A + -
( s 3 -1

And finally, solving for the voltage reference vector located


of the six main sectors, it is convenient to define the angle in sector X d gives:
A, of the rotating voltage reference vector as:
61d = 2 . M.sin(A,) -1
A, = mod (w,t + -76r' 7-)
3
r
(3)
62d = 2 - fi.M . cos(A,) - M . sin(A,) (10)
where w,t = 0 is defined as the positive zero crossing of 63d = J?;. M . C O ~ ( A ,-) M . sin(A,)
the phase A reference voltage (v: = . sin(w,t)). By
this, the angle A, is in the interval: A, E [O..;]. This is The duty-cycle expressions in (7) to (10) are a t any instant
illustrated in Fig. 4. Due to the angle definition in (3) it of time limited by the following constraint:
is only necessary t o monitor the six main sectors 0-V and
then identify whether the sector location is a, b, c or d.
Defining the modulation index M as:
Iv. VECTOR SEQUENCES
(4) In the two-level inverter, the redundant switching states
woo0 and ~ 1 1 1 have
, been used t o develop several discon-
the sector location can be determined, simply by applying
tinuous modulation schemes, providing a switching loss
the law of sines. By this, the following constrains are
reduction of 50% compared t o conventional modulation
obtained :
schemes [17]. However, these discontinuous modulation
schemes can not be applied directly to the capacitor split
three level inverter because they do not provide any con-
trol of the DC-link neutral potential. Hence, in order t o
be applied t o the NPC inverter, the discontinuous modu-
lation schemes of the two-level inverter has to be modified.

A . Discontinuous modulation scheme


In the explanation of the generalized discontinuous
modulation scheme, Fig. 5 is used as an illustration. In
8. Vector time intervals
Fig. 5 the voltage reference vector : fI is located in sec-
z ' l
With reference to Fig. 4, the reference voltage vector tor Oc a t an angle A,, c.f. (3). The current vector L, is
can be obtained by applying the three adjacent stationary lagging the voltage reference vector by the angle 4, where
vectors for an angle dependent time duration. In general 4, is considered positive when lagging the voltage vector
the following matrix equation has to be solved: and negative when leading the voltage vector. To realize
the voltage reference vector, it appears that five different
switching states form the three adjacent stationary vec-
(6) tors, This redundancy can be used to avoid switchings of
1 1 1
one phase leg. Actually, in the present case, 1 21can be
v2
where VI, and If3 are the three adjacent stationary synthesized by either (12) or (13):
vectors, c.f. Fig 4. Based on the sector identification, the
on-time ratios 6 1 . . 3 can be calculated. Solving (6) for the v+o- -+ Ut00 -+ v++o + v+oo --+ v+o- (12)
voltage reference vector located in sector X, gives: v+o- -+ voo- --+ vo-- -+voo- -+ vo-- (13)
61, = 2 . sin (' -A,) In (12), no switchings occur in phase leg A while phase
leg C is clamped during the sequence in (13). Regarding
= 2.M.sin(As) (7) switching losses, the switching sequence, clamping the leg
63, = 1- 61 - 62 carrying the highest current should be chosen. For this

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39 Diode 3 Level Three-phase
Rectifier Inverter linear load
Fig. 6. Definitions of the currents and voltages used for DC-link
balancing. '

TABLE I1
DEFINITION
OF THE SIGN OPERATOR n

I
Even Sec.
Odd Sec.
II a
-Sign(?',)
Sign(P,)
I b
Sign(P,)
-Sign(P,)
1
I C

Sign(P,)
-Sign(P,)
1
I d
Sign(P,)
-Sign(Po)
1
I

interval where phase leg A should be clamped. Generaliz-


ing the above description to an arbitrary voltage reference
location. Table I is obtained.

B. DC-link balancing considerations


So far, the modulation strategy '3ffers no ability for com-
pensating a DC-link voltage unbalance, and since no re-
dundant switch states are used within a switching period,
DC-link balancing can not be obtained by adjusting the
on-times for such redundant switch states. Using Fig. 6,
DC-link voltage balance is obtained when the following
condition is satisfied:
1 1
(IC1)To + 2(Id)To = (IC2)To - Z ( ' d ) T o
b)

Fig. 5. Definitions of clamping interval angle $2 and DC-link bal-


.u- (14)
ancing angle &. a) in the complex space vector domain. b) in (1d)To = ( ( I C 2 ) T o -- ( I C 1 ) T o )
the time domain.
where I c l and I c ~are the DC-link currents originating
from the linear balanced load of the three level converter
purpose, the angle 4; is introduced, c.f. Fig 5 and defined and Id represents the unbalanced loading of the inverter.
as : The notation ( X ) T o indicates tha,t the quantity is aver-

q!J;= { dS if - : < 4 s < 5


-c if q!Js <
2 if 4s > 5
-:
aged over a fundamental having the time period To. From
(14) it appears that an unbalance may be compensated by
adjusting the ratio between ( 1 ~ 1and ) ~( ~
I c 2 ) ~For
~ . this
purpose, the angle n . q!Jc is introduced, c.f. Fig 5, where
The angle 4; determines the angular rotation of the phase the sign operator n is defined in accordance with Table I1
clamping interval. In Fig. 5 the shaded area illustrates the and 4c is defined in the interval ,$c E Further [-$. $I.
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4 , ,
(SVM [Id])

. .. (GDSVM. kf= U3)

(GDSVM, kf= 1)
..<
1 5 ’
-1.5 -I -0.5 0 0.5 1 1.5
Load angle @sLrad]
Fig. 8. Normalized switching losses versus load angle bs

for the fundamental component of the output current, the

-
switching losses of the NPC inverter can be analytically
modeled as:
Modulation index (M) 0 -1 Load angle (9,)[rad]
Fig. 7. DC-link load unbalance for which the modulation scheme is
able to compensate.
where is, is the current through the switching device a t
the angle 4; defined in (14) is modified by: the switching instant and tonand t,ff are the turn-on and
turn-off times of the switching device. Normalizing (17)
to the peak output current, the half of the DC-link voltage
the turn-on and turn-off times and the half of the switch-
From Fig. 5, Table I and Table I1 it appears that by ing frequency, the normalized switching losses becomes:
increasing/decreasing the angle &, the load on capacitor
C1 can be increased/decreased. Hence, the angle & can
be used to compensate unbalanced loading of the DC-link.
To evaluate the ability of the proposed DC-link balancing
Fig. 8 compares the switching losses of the generalized dis-
technique, the current through capacitor C1 and C, have
continuous modulation scheme and the conventional mod-
to be calculated: (Eq. (16) is only formulated for sector
ulation scheme [14] when operated a t the same switching
Oa and in (16) it is provided that the modulation index is
below 0.5.) frequency ( k f = 1). Since the discontinuous modulation
scheme only involves $ times the number of switchings
of the conventional modulation method, it might be more
fair to compare the modulation schemes for the same num-
ber of switchings (kf = $).

B. W a v e form quality
When modulating the three-level converter in order to
synthesize a desired output voltage, harmonics are intro-
Extending 16 t o arbitrary values of the modulation index
duced a t integer multiples of the switching frequency and
M , and calculating for & = the maximum unbal-
a t the side bands of all these frequencies. The harmonic
ance, for which the modulation scheme is able t o com-
content depends on the chosen modulation scheme and
pensate may be calculated. Fig. 7 shows the ability of
since this undesired frequency content causes torque rip-
the proposed modulation scheme to compensate DC-link
ple and additional copper losses in e.g. a motor load, it
unbalances. In Fig. 7 the unbalanced current I d is normal-
is convenient t o have a method t o compare the harmonic
ized to the output current I , originating from the linear
behavior of different modulation schemes. In general, har-
loading of the inverter and plotted against the modulation
monic analysis can be done by either FFT or harmonic dis-
index M and load angle qbs. From Fig. 7 it appears that
tortion factor (HDF). For a quantitative analysis, HDF is
the maximum load unbalance which can be actively com-
most suitable and hence the proposed modulation scheme
pensated is when the load angle is zero, e.g. a resistive
is evaluated with regards to the HDF [18].
load and the modulation index is about 0.52.

V. PERFORMANCE
EVALUATION In the Nth carrier cycle the harmonic flux 4 is calcu-
lated by:
The performance evaluation of the proposed modulation
scheme addresses the two important modulation scheme
characteristics - switching losses and wave form quality.

A . Switching loss considerations where v, is a stationary output voltage vector. To gen-


Assuming the switching devices of the NPC inverter eralize the performance characterization, the per carrier
to have linear current and voltage turn-on and turn-off harmonic flux error $J in (19), is normalized t o the prod-
characteristics with respect t o time and accounting only uct of the nominal output voltage amplitude 1@, and half

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TABLE 111 TABLE IV
TESTSETUP CONDITIONS (NPC INVERTER) TESTSETUP CONDITIONS (INDUCTION MOTOR)

Switching frequency fgw 2.0 [kHz] Nom. power P,, 22.0 [kW]
DC-link capacitors C1 Cz 10.0 [mF] Nom. Cos(+)
DC-link inductor Lf 50 [PF] Pole pair N 2
Load resistor Rl 20 101 Stator resistance R, 0.100 [Q]
Input voltage (1-1) V, 400 [VI Rotor resistance R, 0486 [Q]
Modulation index M 0.8 Leakage inductance L, 1.E817 [mH]
Input frequency fi 50 [Hzl Leakage inductance L, 1,211 [mH]
Output frequency fo 40 [Hz] Mag. inductance L, 27.'336 [mH]

341diode 3-level
8

R 4

0 Modulator
0 0.2 0.4 0.6 0.8 I Fig. 10. The test setup used to validate the proposed modulation
Modulation index M scheme.
Fig. 9. Harmonic flux distortion of the conventional modulation
scheme (SVM) and of the generalized discontinuous modulation
scheme (GDSVM).
the voltage V,N, the lower midd1.e plot shows the current
through the resistor Rl and the lower plot shows the volt-
ages across capacitor C1 and capacitor C,.
the switching period. That is:
$ 2 Applying the proposed modulation technique for DC-
12, (20)
link balancing, the voltage in the center-point N can be
- TslJ?sl
The normalized per-carrier cycle RMS value of the har- reestablished. Fig l l b shows the effects of an unbalanced
monic flux $ J R M S , ~can now be calculated by: loading, similar t o the case in Fig. l l a , where the pro-
posed balancing technique is applied. Fig. 12 shows
a zoom of figure l l b . Fig. l;!a shows the phase cur-
rent and the phase-neutral voltage before the unbalance
is introduced and it appears that the voltage is clamped
where 12,; is the complex conjugate of &. Due to the symmetrical in the vicinity of the peak phase current. Fig.
six fold symmetry of the space-vector modulation, the per 12b shows the phase current and t,he phase-to-neutral volt-
fundamental RMS harmonic flux may be calculated by: age after the DC-link neutral has been restored. From Fig.
12b it appears that in order t o compensate the unbalanced
load of the DC-link, the modulator adjusts the clamping
interval of the upper and lower switches.
Defining the HDF as the square of the per fundamental VII. C O N C L ~ J S I O N
RMS harmonic flux, Fig. 9 is obtained. From Fig. 9
it appears that for the same number of switchings (kf = This paper has presented a new generalized discontin-
$), the proposed modulation scheme produces almost the uous modulation scheme with th,e capability of balancing
same HDF as the conventional modulation. the DC-link neutral point, even if an unbalanced loading of
the two DC-link capacitors for sc'me r e s o n occurs. Com-
VI. RESULTS pared to conventional modulation schemes, the proposed
A . Test setup strategy reduces the switching losses by up to 25% while
maintaining the same output voltage quality. The func-
Fig. 10 illustrates the test setup used t o validate the tionality of the proposed modula.tion scheme is validated
proposed modulation scheme and Table I11 and Table IV by simulation results.
lists the characteristics of the test setup.
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1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.05 1.1 1.15 1.2 1.25 1.3 1.35

."" -400 ' I


1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.05 1.1 1.15 1.2 1.25 1.3 1.35

-L 350
-B 300
%

0
I

3 250
z
.e

Q 200
1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.05 1.1 1.15 1.2 1.25 1.3 1.35

!
1.05 1.1 1.15 1.2
Time [SI
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: : :y .-6
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1.1 1.15 Time [SI


1.2 1.25

b)
1.3 1.35

Fig. 11. Simulation results. a) Simulation results without DC-link compensation. b) Simulation results with the DC-link balancing
technique applied.

: a : 5 1
W
0
-1 -50 -1 -50

1.05 1.06 1.07 1.08 1.09 1.1 1.35 1.36 1.37 1.38 1.39 1.4

-400 I
-400 I J
1.05 1.06 1.07 1.08 1.09 1.1 1.35 1.36 1.37 1.38 1.39 1.4
Time [SI Time [SI
a) b)

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