EE 5323 VLSI Design I

Fall 2018
Class webpage: moodle.umn.edu
UNITE video access: www.unite.umn.edu

Class lecture 3:35 – 4:25pm Mon Wed Fri Keller 3-230

Instructor Prof. Chris H. Kim (www.umn.edu/~chriskim/) Office: Keller 4-161

Email: chriskim@umn.edu Ph: (612) 625-2346
Office hrs: Mon 2-3pm, Fri 2-3pm, or by appointment

TA Luke Everson Office: Keller 2-120 (VLSI Lab)

Email: evers193@umn.edu
Office hrs: Tues 12:30-1:30pm, Thurs 3-4pm, or by appointment

Objectives
This class is intended to be an introduction to the design of digital Very Large Scale Integrated
(VLSI) circuits. It is the first part of a two-semester sequence: this part focuses on the transistor-
level and logic-level aspects, while the second part, EE 5324, concentrates on designing circuits
that implement various functionalities (adders, multipliers, memories, etc). The main objective of
the two-semester sequence is to provide the student with the capability of designing digital VLSI
circuits. The term-long project involves heavy use of Cadence schematic and layout tools which
are the de-facto design software in the semiconductor industry.

Prerequisites
The prerequisites to this class are EE2301 (the first class on digital logic design) and EE3115 (the
first class on analog and digital circuits), or equivalent. Students are expected to have a working
knowledge of digital logic design and basic CMOS devices and circuits.

Electronic communication
Students should monitor their email regularly and check the class web page for any important
announcements, homework, handouts, etc.

Course text
The instructor will use his own lecture notes derived from many sources, so a textbook is not
needed. The following references will be used for some images/illustrations.
N. H. E. Weste and D. Harris, CMOS VLSI Design, 4th ed., Addison Wesley, Reading, MA,
2011.
J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, 2nd ed., Prentice
Hall, New York, NY, 2003.

Grading (tentative)
Your course grade will be based on the following components:
20% for midterm (October 24 or 26).
30% for final exam (tentative date: Dec 12th Wed).
30% for project.
20% for homework.

Course topics
CMOS device physics and models
Basics of CMOS circuits: basic gates, combinational and sequential logic
Essentials of semiconductor processing
CMOS layout design
Delay calculation and optimization; logical effort
Designing wires
Dynamic CMOS circuits
Designing pipeline circuits using flip-flops and latches
Timing issues in digital circuits
Design for controlling power dissipation
Design issues for supply nets and clock nets

Policies
• Within this course, a student responsible for scholastic dishonesty will be given zero points for
the assignment they copied, and the final grade will be reduced by one letter grade (e.g. B to
C). Additionally, the incident will be reported to OSCAI (http://www.oscai.umn.edu). Examples
of scholastic dishonesty include, but are not limited to: copying someone else’s schematic or
layout, sharing simulation data, sharing or copying assignments with friends, copying from
other sources such as the solution manual, and working on the exam after the exam is over. A
good rule of thumb: If you think you might be engaging in scholastic dishonesty, then you are.
• No late assignments will be accepted.
• Regrade requests or petitions must be made within 1 week of receiving the assignment or
exam sheets
• No “Incomplete” grades will be given for the class, except under extreme circumstances.
• At the end of the semester, I will not respond to questions such as what the grading cut offs
were, how much you missed the next grade by, how the grades were curved, etc. If you feel
that there was a human error while calculating or entering your letter grade, please send the
instructor a formal request by email.
• Students with disabilities that affect their ability to fully participate in class or meet all course
requirements are encouraged to bring this to the attention of the instructor so that appropriate
accommodations may be arranged. Further information is available from disability services, 14
Johnston Hall, 612-624-4037
• Streaming video archives of class meetings are available to students registered in the on-
campus section of this course on a TEN-DAY delay for the length of the semester (UNITE will
not make media available to students enrolled in on-campus sections for any reason past the
last day of finals, including when assigned an Incomplete by the instructor). This ten-day delay
is lifted one week prior scheduled exams and one week prior to finals as long as students are
also enrolled in the course through UNITE Distributed Learning. If there are no UNITE
enrollments, the ten-day delay will only be lifted the week prior to finals week. Access these
videos through the UNITE Media Portal with your University of Minnesota Internet I.D. and
password (this is what you use to access your University of Minnesota email account). DO
NOT ask the instructor or teaching assistants for technical or troubleshooting assistance with
these streaming video archives – use the UNITE Troubleshooting FAQ or “Submit a Trouble
Report to UNITE” link found on all pages within the UNITE Media Portal.