Baker Ch.

2 The Well Introduction to VLSI

 Chapter 2
– The Well
• Cross Sections
• Patterning
• Design Rules
• Resistance
• PN Junction
• Diffusion Capacitance

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 1
 Baker Ch. 2 The Well Introduction to VLSI

 Cross Sections  DESCRIPTION

– Substrate
• Epi  epitaxial layer (p-), expensive
• p+ Boron doping substrate
• Body of NMOS

– PWell
• No PWell, unless expensive process
• Twin tub/moat
– Old nomenclature, do not use

– NWell
• n- Phosphoros doping
• Isolation by parasitic diode
• Can be used as a resistor
– Current flows where?
– What potential problem?

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 2
 Baker Ch. 2 The Well Introduction to VLSI

 Generic Patterning  DESCRIPTION

– A,B) Starting material
• P-type Si, ~500um thick
– C) Grow oxide
• Thermal process, SiO2 result
• Dry Oxide, less defects, longer
• Wet Oxide, more defects, shorter
• Consumes Si
– D) Deposit photoresist (PR)
• Spin on viscous liquid ~1um
• Soft bake to harden
– E,F) Align mask
• Mask was made from layout tool
– G) Expose PR
• Light will make PR more acidic/basic
• Over/Under expose feature size
• Hard bake
– H) Develop PR
• Neutralize expose PR
– I) Etch underlying layer
• Acid etch, H2SO4 or similar
– J) Remove PR
• Clean up, do not leave residue

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 3
 Baker Ch. 2 The Well Introduction to VLSI

 Nwell Patterning  DESCRIPTION

– Deposit PR
– Expose PR
• Nwell layout from tool  mask
– Develop PR
– Implant Nwell
• N- Phosphoros
• Depth of implant set by energy
– Diffuse dopant material
• Diffusion coefficient
• Gaussian profile  rectangular
– Remove PR
– Nwell formed

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 4
 Baker Ch. 2 The Well Introduction to VLSI

 Design Rules  DESCRIPTION

– DESIGN RULE CHECK
• DRC
– NWELL-NWELL SPACING
• INTERLAYER
• ISOLATION DRIVEN
– NWELL WIDTH, LENGTH
• INTERLAYER
• PR, IMPLANT DRIVEN
– Bipolar parasitcs formed
• NPN, weak beta
• Depends on what node for activity?

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 5
 Baker Ch. 2 The Well Introduction to VLSI

 Resistance  DESCRIPTION
– R = r L / A = r L / (W * t) = rS L / W
– SHEET RESISTANCE
• LUMP THICKNESS INTO VALUE
• NEED SEPARATE MONITOR
– NUMBER OF SQUARES
• CURRENT DIRECTION
• SQUARES=L / W

– TAP
• N+ to Nwell
• P+ to Psub

– DIFFUSION
• N+ in Psub
• P+ in NWell

– Contact to Nwell
• Not as shown, but close
• Nwell must enclose tap
• Metal is really conact / LI layer

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 6
 Baker Ch. 2 The Well Introduction to VLSI

 PN Junction  DESCRIPTION
– USES
• ISOLATION
• ACTIVE DIODE
– CONDUCTION, VALENCE BANDS
• SEPARATED BY BANDGAP
– OFFSET IN BANDS PRODUCE Vbi
– FORWARD BIAS, OVERCOME Vbi

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 7
 Baker Ch. 2 The Well Introduction to VLSI

 Depl, Diffusion Capacitance  DESCRIPTION

– DEPLETION REGION ISOLATION

• AKA JUNCTION ISOLATION
• NO CURRENT CONDUCTION
• WIDTH OF DEPL LAYER VS. BIAS
• LOWER DOPING, LARGER Wdepl

– UNDERSTAND CAPACITANCE
• FUNDAMENTAL
• REPEATED IN ALL DEVICES

t C= e A / t
– SIDEWALL VS. BOTTOM WALL
• DIFFERENT PHYSICS, MODEL
• DOPING, ISOLATION DIFFERENT

– ZERO BIAS DEPL IN MODELS (CJ0)

• CAP EXISTS AT ZERO BIAS
• CAP INCREASES W/INCR FB

– DIFFUSION CAP
RB FB
• PRESENT IN FORWARD BIAS (FB)
t t • OP POINT FOR DIODE USUALLY RB

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 8
 Baker Ch. 2 The Well Introduction to VLSI

•When p-type and n-type materials are joined, diffusion
occurs.
Excess holes in p-type region diffuse to n-type, and
excess electrons in n-type diffuse to p-type region
•The exposed ionic cores in the p-type region (negative,
Na) must be matched by the exposed ionic cores in the
n-type region (positive, Nd), leaving a net charge-
neutral device:
q A xp NA = q A xn ND

•This diffusion is opposed by the resulting electric field •If A is the same on both sides, then
of the uncovered ionic charges. The positive ion cores xpNA = xnND
in the n-type region oppose the diffusion of the p-type meaning the depletion depth is greater for a more
carriers from the p-type region, and vice-versa. lightly doped region

•The ionic charge results in an E-field, which causes a

built-in potential to form. This Vbi will oppose the
diffusion and it will match the -qVbi in the band
diagrams.

t
C= e A / t
Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor 9