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Course Syllabus

Computer Architecture and Engineering

Author: V.Sh. Melikyan, Sci.D., Professor


Reviewers: V.M. Movsisyan, Ph.D., Associate Professor
A.K. Tumanyan

Introduction:
The course program on “Computer Architecture and Engineering” is assigned for undergraduate
education of EDA specialization and is taught in the 5th semester (3 year’s 2nd semester).

Objective:
The main objectives of the course are organization of modern computers; Virtual memory (paged and
segmented) and multilevel cache memory organization; organization of instruction pipelining. The course
also focuses on the study of methods input/output organization.

Class Hours:
The course duration is 82 hours, lectures volume is 64 hours and laboratory works are 18 hours.

Homework and Exam:


Grades will be assigned on:
 Lectures (60 scores)
 Laboratory Works (20 scores)
 Practice classes (20 scores)
 Final exam.

Prerequisites:
The course program is compiled taking into account that the following courses had been studied in
advance:
 Introduction to Programming
 Computer Organization
 Physical Fundamentals of Microelectronics or Solid State Electronics.
Understanding of the course is the basis for further specialized subjects destined by the educational plan
of Electronic Design Automation specialization.

Reference Materials:
To study the course the necessary list of references is given below.
1. W. Stallings. Computer Organization and Architecture. 10th Edition. Pearson; 2015
2. J. Hennessy, D. Patterson. Computer architecture: A Quantitative Approach. Elsevier India; 2014
3. D. Patterson, J. Hennessy. Computer Organization and Design, 5th Edition: The
Hardware/Software Interface. Morgan Kaufmann; 2013
4. A.Tanenbaum. Structured Computer Organization. Prentice Hall India;2013
5. W. Stallings. Computer Organization and Architecture. Designing and Performance. PE; 2013
6. D. Harris, S. Harris. Digital Design and Computer Architecture. 2nd Edition. Morgan Kaufmann.
2012

Grading:
This course will be graded according to Professor’s discretion.

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Developed by: Vazgen Melikyan
Course Syllabus

Lectures (64 hours):


Topic 1 (2 hours) – Introduction
 General information about computers. Classification. Generalized structural scheme of computer
- basic components of computer and their functionality. Metrics of performance. Amdahl’s law.

Topic 2 (4 hours) - Instruction Set Architecture (ISA)


 ISA classification. Evolution of instruction sets. Basic ISA classes. Data representation, integer
and floating-point number representation. Types and sizes of operands. Instruction formats: 1-
address, 2-address,3-address ISA. Load-store ISA. Stack machines. Classification of operations.
Modes of operands addressing. Instructions classification. Branch instructions. Procedure call
and return.

Topic 3 (4 hours) – Arithmetic Logic Units (ALU)


 The structure of execution unit. Addition/subtraction of integer numbers. Integer multiplication
(unsigned and signed). Integer division: restoring and nonrestoring division. Signed and
unsigned integer division. Arithmetic unit for signed division. Floating point arithmetic. Steps in
addition/subtraction of floating points numbers. Floating point multiplication and division. Logical
operations, shift operations. MMX and SSE instructions.

Topic 4 (8 hours) - Basic Structural Organization of a Processor. Instruction Pipelining


 Central processor: structure, datapath and control, instruction execution stages.
Instruction Level Parallelism (ILP). Instruction pipelining. Pipelines and measures of performance.
Pipeline complications: dependences. Data and control hazards.
Resolving data hazards: register renaming. Methods of resolving control hazards. Prediction of
static and dynamic branch. Branch predictors and branch target buffers. Control hazard avoiding
through software techniques: predication. Hardware support for the greater ILP degree
achievement. Execution of out-of-order instruction (re-order buffer, speculation).
Functions of OS. Classification of interrupts and exceptions. Interrupts handling (hardware and
software).

Topic 5 (6 hours) - Memory Organization


Memory hierarchy – motivation, definitions. Improving performance. Types of storage devices and
their characteristics. Static and dynamic random access memory (SRAM and DRAM).
Classification. Characteristics and perspectives. ROM purpose and classification. Flash-memory.
Associative memory.
Motivation for caches. The principle of locality. Methods of cache memory organization: direct-
mapped, fully-associative and set-associative. Cache write policy. Cache performance. Reducing
cache misses. Reducing cache penalty. Multilevel cache memory organization. Trace cache.
Virtual memory. Organization of paged virtual memory. Page table format. Translation look-aside
buffer (TLB). Segmented virtual memory organization. Memory protection. Examples of virtual
memory organization.

Topic 6 (8 hours) - Contemporary Processors


 CISC and RISC architectures. Superscalar processors. Pentium 4 processor structure. Hyper-
threading. Multiprocessors. IA-64 architecture. Itanium 2 processor structure. EPIC conception:
predication, data and control speculation, software pipelining of cycles (SWP).

Topic 7 (4 hours) - Input/Output Organization

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Copyright © 2017 Synopsys, Inc. All rights reserved.
Developed by: Vazgen Melikyan
Course Syllabus

 Structure of I/O devices. Functions of controller. I/O addressing techniques: isolated input/output.
Memory mapped I/O. Methods of execution of input/output operations: program-controlled I/O.
Input/output for interruption. Direct memory access. Methods of connectivity of I/O devices. I/O
channels. Generalized scheme of a computer .

Topic 8 (8 hours) – OpenSPARC: UltraSPARC Architecture


 University roots. Generations of SPARC. Chip multi-threading. Features of ultrasparc
architecture. Instruction execution. Data formats. Integer data formats. Signed integer data types.
Unsigned integer data types. Floating-point data formats. Floating point, double precision. Quad
precision. SIMD data formats. The ordering of bytes in memory. Big endian replacement. Big-
endian addressing convention. Little-endian addressing convention. Instruction categories.
Registers. Three overlapping windows. Control transfer instruction (CTI). Branch prediction.
Delayed branches. ASI register. Program counters (PC, NPC). Tick compare (TICK_CMPRP).
The modes of operating of virtual processor. ASIs categories. Chip multithreading (CMT). Classes
of CMT registers. Strand interrupt. disabling and parking virtual processors. Strand running
register (STRAND_RUNNING). Parking and unparking virtual processors. Traps. Register
window traps. OpenSPARC execution modes. Basic principles. Privileged mode constraints.
Translation management. Hypervisor support.

Topic 9 (12 hours) – OpenSPARC T1: Overview


 Chip multithreading (CMT), OpenSPARC T1 chip block diagram. SPARC T1 core structure and
pipeline. Icache and ITLB. Thread selection policy, thread scheduling, rollback mechanism. Load
store unit , D Cache and DTLB. Execution unit structure. Shared FPU structure and pipeline.
Floating point instructions. Trap logic unit functions.
Memory organization and memory management unit. Virtual, real and physical address spaces.
The structure of TLB, translation storage buffer. CPU – Cache Crossbar(CCX) overview, PCX and
CPX interfaces and arbiters. L2 cache, L2-cache instruction descriptions . J-Bus interface
instructions.

Topic 10 (8 hours) – OpenSPARC T2: Overview


 OpenSPARC T2 chip goals, T2 chip block diagram, OpenSPARC T1 to T2 core changes.
OpenSPARC T2 core block diagram and pipeline structure. Instruction fetch unit. Fetch thread
pick mechanism, address generation, redirection sources. Execution unit structure. Floating point
and graphics unit. Types of speculation. Architecture memory models: vrtual address translation.
Conceptual view of the MMU. Hyperprivileged memory management: partition ID, real address
translation.TSB organization.

Laboratory Works (18 hours):


Topic 1 (1 hour) – Study of the Operation of Simple RISC Processor and its Sequence of Instruction
Execution.
Topic 2 (1 hour) – Study of the Function of Simple RISC Processor and the Execution of Load and Store
Instructions
Topic 3 (1 hour) – Multiplication of Integer Numbers
Topic 4 (1 hour) – Division of Integer Numbers
Topic 5 (1 hour) – Study of Processor Operation Algorithm Using Subroutines (Tasks) and Simulation
Topic 6 (1 hour) – Study of Instruction Fetch and Prediction for the Next Instruction Address Using BTB
Topic 7 (1 hour) –Checking Prediction Accuracy and Next PC Formation
Topic 8 (1 hour) – Correction of Branch Prediction History.

OpenSPARC Laboratory Works:


Topic 1 (1 hour) – Adder
Topic 2 (1 hour) – Sum Predictor

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Copyright © 2017 Synopsys, Inc. All rights reserved.
Developed by: Vazgen Melikyan
Course Syllabus

Topic 3 (1 hour) – Addition and Subtraction


Topic 4 (1 hour) – OR Block
Topic 5 (1 hour) – Equality Checker
Topic 6 (1 hour) – Comparator
Topic 7 (1 hour) – Bypass Logic
Topic 8 (1 hour) – Logic Function
Topic 9 (1 hour) – Shifting
Topic 10 (1 hour) – Round Robin Scheduler.

Synopsys University Courseware


Copyright © 2017 Synopsys, Inc. All rights reserved.
Developed by: Vazgen Melikyan