Interpolation, Decimation & Filters

DAC5688
Inverse SINC Filter
CLK & PLL

Offset

Interpolation

Quadrature Modulator
Corretion (QMC)
Complex Mixer
Input FIFO /
Demux

Mixer & NCO QMC DAC

 DAC5688 – Interpolation * RBW 50 kHz Marker 3 [T1 ] * RBW 50 kHz Marker 3 [T1 ]
VBW 200 kHz -18.48 dBm VBW 200 kHz -25.83 dBm
Ref 5 dBm Att 30 dB SWT 400 ms 274.038461538 MHz Ref 5 dBm Att 30 dB SWT 400 ms 525.641025641 MHz
1 1
Marker 1 [T1 ] Marker 1 [T1 ]
0 2.80 dBm 0 2.91 dBm
23.557692308 MHz A 24.038461538 MHz A
Marker 2 [T1 ] Marker 2 [T1 ]
1 AP -10 -16.36 dBm 1 AP -10 -24.38 dBm
CLRWR 2 CLRWR
3 224.358974359 MHz 475.961538462 MHz

-20 -20 2
3

-30 -30

-40 -40

-50 -50

-60 -60

-70 -70

-80 -80

-90
1) INT=1 -90
2) INT=2
Start 0 Hz 100 MHz/ Stop 1 GHz Start 0 Hz 100 MHz/ Stop 1 GHz

* RBW
VBW
50 kHz
200 kHz
Marker 2 [T1 ]
-33.31 dBm
Fout=25MHz
Ref 5 dBm Att 30 dB SWT 400 ms 975.961538462 MHz
1

Span: 0Hz – 1GHz

Marker 1 [T1 ]
0 2.94 dBm
24.038461538 MHz A

1 AP -10
CLRWR

-20
1) Fdac=250Msps, Fdata=250Msps, INT=1
-30 2
2) Fdac=500Msps, Fdata=250Msps, INT=2
-40

-50 3) Fdac=1000Msps, Fdata=250Msps, INT=4

-60

-70

-80

-90
3) INT=4
Start 0 Hz 100 MHz/ Stop 1 GHz
ADS62Pxx – dual 12/14bit up to 125Msps
1. Offset Correction
2. Gain Correction
3. User programmable Filter
4. Decimation Filter

1 2 3 4
DAC8580 – Integrated Filter
• Relaxed analog filter requirements
• Relaxed computational burden on the processor
• Relaxed burden on the DAC8580 output buffer
ADS1281 – Integrated Filter
• Three cascaded filter stage
– Variable decimation, 5th order sinc
– Fixed decimation FIR LPF, with selectable phase
– Programmable High Pass Filter
• Adjustable: resolution vs. data rate