IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO.
6, DECEMBER 2007
A New Carrier-Based PWM Providing
Common-Mode-Current Reduction and DC-Bus
Balancing for Three-Level Inverters
Arnaud Videt, Philippe Le Moigne, Member, IEEE, Nadir Idir, Member, IEEE,
Philippe Baudesson, and Xavier Cimetière
Abstract—Adjustable-speed drives involve common-mode volt-
ages, which generate common-mode currents flowing to the
ground through stray capacitances of electric machines. These
currents are known to provoke premature motor-bearing fail-
ures, as well as electromagnetic interferences disturbing neigh-
bor electronic devices. Furthermore, high-voltage applications
involve high levels of these conducted emissions, which must be
lowered by using bulky and expensive filters. This paper aims
at elaborating a new pulsewidth-modulation (PWM) strategy in
order to reduce the common-mode currents generated by three-
level neutral-point-clamped inverters. The proposed strategy also
provides the ability to balance the neutral point of the dc-bus
capacitors. Experimental results both in time and frequency do-
mains confirm that the new PWM improves the electromagnetic-
compatibility behavior of the drive compared with conventional
strategies.
Index Terms—Common-mode currents, electromagnetic
compatibility (EMC), neutral-point-clamped (NPC) inverters,
pulsewidth modulation (PWM), variable-speed drives.
I. I NTRODUCTION
T HE STATOR iron and windings of electric machines are
close metallic elements between which stray capacitances
naturally exist [1]. Furthermore, the stator is connected to
the ground; so fast commutations (high dν/dt) on the phases
result in high-frequency leakage currents flowing through the
stray capacitances into the ground conductor. These common-
mode currents eventually come back to the inputs of the mo-
tor drive through the electrical network. They may generate
electromagnetic interferences (EMIs) that cause malfunctions
in the surrounding electronic equipment and are responsible for
premature deterioration of the motor bearings [2]. Moreover,
these conducted emissions are all the more important as the
commutations perform high-voltage transitions.
Therefore, research has focused on the reduction of common-
mode conducted emissions by using either passive or active
filters [3]–[5], designing converters with low dν/dt transitions
(e.g., using soft switching or snubbers [6]), or developing new
Manuscript received February 26, 2007; revised June 27, 2007.
A. Videt, P. Le Moigne, and X. Cimetière are with the Laboratoire
d’Electrotechnique et d’Electronique de Puissance, Ecole Centrale de Lille,
59651 Lille, France (e-mail: videt.arnaud@ec-lille.fr).
N. Idir is with the Laboratoire d’Electrotechnique et d’Electronique de
Puissance, University of Lille, 59655 Lille, France.
P. Baudesson is with Schneider Toshiba Inverter Europe, 27120 Pacy-sur-
Eure, France.
Digital Object Identifier 10.1109/TIE.2007.907001
0278-0046/$25.00 © 2007 IEEE
3001
pulsewidth-modulation (PWM) strategies for classical hard-
switched two-level and multilevel inverters [1], [7]–[11]. Since
industrial application requires low-cost and easy-to-implement
solutions, the work on PWM strategies is promising because no
additional component is needed.
Moreover, multilevel voltage-source inverters are interest-
ing for high-power applications because they allow reduced
voltage constraints on the switches, as well as lowered total
harmonic distortion (THD) of the output voltages. Furthermore,
their reduced step-voltage variations involve less EMI than the
conventional two-level inverters.
This paper focuses on the three-level neutral-point-clamped
(NPC) inverter and proposes a new PWM strategy [13] which
is able to reduce the generated common-mode currents. The
basic control principles of the three-phase NPC inverter are
introduced, and the link between the PWM strategy and the
common-mode voltage is clarified. Two solutions for the re-
duction of common-mode currents are presented and combined
into the proposed PWM: the Flat-Top technique and the double-
commutation mechanism. Compared with previous strategies,
the new method provides several degrees of freedom which
are used to ensure the real synchronism of the double com-
mutations by controlling their nature and avoiding dead-time
effects.
A very important issue in using an NPC inverter is the ability
to control the midpoint voltage of the dc-bus capacitors [12].
This paper shows that the degrees of freedom of the new PWM
still permit this regulation in addition to the electromagnetic-
compatibility (EMC) improvement of the drive. The maximum
balancing capacity is also compared with conventional PWM
through simulation.
The proposed strategy has been implemented into a
20-kVA NPC prototype with a new carrier-based modulator.
Time- and frequency-domain experimental results confirm the
best EMC performances of the new PWM compared with
conventional strategies. The dc-bus balancing ability is also
verified.
II. C ONVENTIONAL C ARRIER -B ASED C ONTROL OF
AN NPC C ONVERTER
A. General Overview
The three-phase three-level NPC inverter is shown in Fig. 1.
The dc bus (E) is distributed on the two capacitors (C), and
3002
Fig. 1. NPC inverter feeding a motor.
Fig. 2. Vectorial representation of the inverter-switching states.
their respective voltages are noted us1 and us2 (normally us1 =
−us2 = E/2). Therefore, the output voltage (VAO , VBO , or
VCO ) between one phase (A, B, or C) and the midpoint of
the dc-bus capacitors (O) can either be −E/2, 0, or +E/2
according to the configuration of the switches. This corresponds
to three possible states symbolized as −1, 0, and +1. Thus, the
whole system has 27 possible states (33 ) which are represented
in a well-known vectorial diagram (Fig. 2). In this figure, the
phase-to-neutral voltages of the load (VAN , VBN , VCN ), defined
by (1), can be deduced from the position of the states by
projection on the axes A, B, and C.
Given a reference vector (V ref ), the goal of the PWM
strategy is to build up this vector by using neighbor states
from the figure (such as the ones circled around V ref ). It
can be noticed that this diagram contains redundant states, as
some vectors can be obtained with different combinations of
states (near the center of the figure): This provides a degree of
freedom about the choice of the states.
One important quantity is the common-mode voltage (VCM )
defined in (2). It is directly linked to the states of the three
∗
legs; thus, its normalized value (VCM ) is reported between
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 6, DECEMBER 2007
Fig. 3. Conventional modulator: (a) Natural and (b) Flat-Top modulations.
∗
brackets next to these states in Fig. 2 (VCM is an integer between
−3 and +3)
VAN = (2 × VAO − VBO − VCO )/3
VBN = (2 × VBO − VAO − VCO )/3
VCN = (2 × VCO − VAO − VBO )/3 (1)
VCM = (VAO + VBO + VCO )/3
VCM ∗ = VCM × 6/E. (2)
B. Action of the Homopolar Component
This section describes the classical principles of carrier-
based modulation of three-level inverters. In particular, the
influence of the homopolar component is underlined.
The most widespread modulator uses two triangle carriers
in phase (one positive and one negative), of unit amplitude, as
shown in the example of Fig. 3(a). The mean values (during one
switching period) of the output voltages (VAO , VBO , VCO ) are
controlled by the normalized input quantities (hAO , hBO , hCO )
[(3)]. Indeed, their comparison with the carriers (below the
lower one, between the two carriers, or above the upper one) im-
poses the output states of the legs (−1, 0, or +1, respectively),
which sets their voltage levels and duty cycles.
However, the interesting values to be controlled are the load
voltages (VAN , VBN , VCN ). Therefore, let (hAN , hBN , hCN ) be
VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING
the normalized reference voltages of the load defined by (4).
They are imposed and cannot be modified.
From (1) and (2) come (5) which links the three-phase
voltage systems of both the load and the inverter with the mean
common-mode voltage. Considering the normalized quantities,
this corresponds to the introduction of an average homopolar
component (hNO ) according to (6). The latter is a degree of
freedom that can control the mean value of the common-mode
voltage (during one switching period) without deteriorating the
three-phase voltage system of the load
∀k ∈ {A, B, C} : hkO = VkO × 2/E (3)
∀k ∈ {A, B, C} : hkN = VkN ref ×2/E (4)
∀k ∈ {A, B, C} : VkN ref = VkO ref −VCM ref
(5)
∀k ∈ {A, B, C} : hNO = VCM ref × 2/E
hkO = hkN + hNO . (6)
The simplest method permanently sets hNO to zero (natural
modulation), as shown in Fig. 3(a). However, nonzero values
may be valuable for two main reasons.
1) Overmodulation possibility: The optimal dc-bus utiliza-
tion (maximum output voltages) can only be reached
by using the homopolar component and permits a 15%
voltage gain upon the natural modulation.
2) Switching-loss reduction by Flat Top: The homopolar
component can be adjusted so that one of the input
quantities (hAO , hBO , hCO ) is held at a particular value
(−1, 0, or +1) during the whole switching period. This
leads the corresponding leg to be blocked to a single state,
as Fig. 3(b) shows for the same reference system as the
previous example: hAO is now held at level +1; therefore,
leg A does not switch anymore. This technique is named
“Flat Top” and allows a reduction of the switching losses,
as well as optimal dc-bus utilization [14].
These principles can be applied to all inverters (any number
of legs and levels) with well-known adapted modulations [15].
A specificity of an NPC inverter is the midpoint balancing of
the dc-bus capacitors and is discussed in the following section.
C. Midpoint Balancing
The use of an NPC converter must comply with the require-
ment of midpoint-balancing ability. Indeed, a voltage imbalance
on the dc-bus capacitors would induce a voltage increase on
some switches, which could reach dangerous levels. Normally,
the us1 and us2 voltages (Fig. 1) should be equal to E/2
and −E/2, respectively; thus, their sum ∆us [(7)] should be
null. However, under particular control and load conditions,
∆us might drift from zero and diverge [16] (∆us actually
characterizes the dc-bus imbalance). Therefore, a solution to
bring it back to zero must be provided, which can be obtained
with appropriate control of the PWM [17].
Since the voltage references (hAN , hBN , hCN ) cannot be
modified, the homopolar component hNO is the degree of
3003
Fig. 4. Common-mode current generated by one commutation (time: 1 µs/div,
voltage: 50 V/div, current: 0.5 A/div).
freedom that permits the control of the dc bus. Indeed, ∆us
is linked to the i0 current (Fig. 1) by (8). The mean value of
this current i0 (during one switching period “Ts”) can be deter-
mined from the phase currents (iA , iB , iC ) and the normalized
quantities of the modulator according to (9) [18]. Since the
voltage references as well as the phase currents are imposed
and constant during a switching period, it appears clearly that
the homopolar component hNO has a direct influence on i0 and
thereby on ∆us.
In conclusion, the homopolar component hNO influences the
NPC converter in different ways such as the Flat-Top possibility
or the dc-bus balancing. Therefore, compromises have to be
found [19], [20]
∆us = us1 + us2 (7)
i0 = −C · d∆us/dt (8)
i0 Ts = |hAO | · iA + |hBO | · iB + |hCO | · iC
i0 Ts = |hAN + hNO | · iA + |hBN + hNO | · iB
+ |hCN + hNO | · iC . (9)
III. P ROPOSED PWM S TRATEGY
A. EMI Problem
The common-mode path is mainly capacitive; therefore,
common-mode currents (ICM in Fig. 1) will appear in response
to fast variations of the common-mode voltage. Since the PWM
strategy determines the sequence of states of the inverter, it is
obvious that it will also determine the common-mode-voltage
sequence (Fig. 2) and will thereby have a direct influence on
the common-mode currents.
In conventional strategies, the commutations are isolated,
i.e., there is no synchronization of any couple of commutations.
Therefore, according to (2), each commutation will lead to
a “one-level” variation of the common-mode voltage, and a
common-mode-current response will appear. Indeed, Fig. 4
3004 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 6, DECEMBER 2007

shows one commutation and its associated common-mode-

current response. Since stray inductive elements also exist
along the common-mode path, ICM runs into oscillations—at
1.8 MHz in this example.
Thus, in order to reduce the common-mode currents, PWM
strategies should limit the number of transitions in the generated
common-mode voltage.

B. Flat-Top Solution
As long as conventional strategies are considered, there
are as many common-mode-current pulses as commutations.
Consequently, the only solution is to limit the number of
commutations, which means the use of the Flat-Top technique.
Indeed, PWM strategies can be classified as continuous
(CPWM) or discontinuous (DPWM) modulations, depending
on the hNO (t) characteristic [21]. In practice, during one
switching period, the three legs of the inverter are switch-
ing in CPWM, whereas only two are switching in DPWM,
in which the Flat-Top technique is applied. Moreover, each
switching leg performs two commutations per switching period.
Therefore, CPWM strategies involve six commutations per Fig. 5. Proposed PWM: (a) Vectorial principle and (b) VCM ∗ waveform.
switching period, whereas DPWM perform only four. There-
fore, the Flat-Top technique limits the number of common-
mode-voltage transitions to four per switching period instead
of six.
However, building up any reference vector requires at least
two switching legs. Therefore, conventional PWM cannot re-
duce the common-mode current below four pulses per switch-
ing period.

C. Double-Commutation Solution
∗
In order to reduce further the variations of VCM , noncon-
ventional techniques must be applied so that some unavoidable
commutations occur without variation of the common-mode
voltage. This result can only be obtained by doing simultaneous
commutations instead of isolated single ones. Indeed, according
∗
to (2), VCM may remain constant if two commutations on
different legs happen exactly at the same moment in opposite
directions (i.e., the output voltage of one leg is increasing by
one step, whereas the other one is decreasing by one step)
[13]. Therefore, it is theoretically possible to perform harmless
commutations by applying this technique.
Most methods previously proposed in literature use double
commutations to reduce the common-mode currents. The most
ambitious approach is the Zero Common Mode (ZCM) strategy
[8], which uses only the seven vectors of Fig. 2 in which the
common-mode voltage is null. Therefore, there are, theoreti-
cally, neither common-mode-voltage variations nor common-
mode-current pulses anymore. However, this perfect result is
not clear when real phenomena such as dead times are taken
into account [22], and this method suffers some drawbacks
concerning the THD of the output voltages [23], the utilization
of the dc bus, or the midpoint balancing.
Very similar methods have been developed for two-level [1],
[10] and other multilevel [9], [11] inverters and have likewise
drawbacks.
Fig. 6. THD∗ of the phase-to-phase voltages for different PWM strategies.
D. Proposed PWM: Combining Both Solutions
The proposed PWM uses the Flat-Top technique as well as
the double-commutation mechanism once per switching period.
Therefore, from six initial transitions on the common-mode
voltage per switching period, two are saved by the Flat-Top
method, and two more are saved by the double commutation.
Only two transitions remain; thus, the number of common-
mode-current pulses is limited to two per switching period.
Fig. 5(a) shows the principle of the new PWM. While con-
ventional modulations use states located on small equilateral
triangles (circled in Fig. 2), the ones used in this strategy have
the same area but have a different shape. This leads to a higher
THD on the output voltages than conventional modulations
but still lower than with two-level inverters or three-level ones
controlled with special strategies such as the ZCM. Indeed,
Fig. 6 compares different strategies based on their THD∗ [(10)]
(Uk is the kth harmonic of one phase-to-phase voltage). In the
VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING 3005

Fig. 7. Definition of specific areas to characterize the location of V ref .

new PWM, the exact curve actually depends on the choice of

the triangles; therefore, this result is a representative solution
that is obtained with simple choices. It illustrates the interesting
compromise behavior of the new PWM


100
THD∗ = Uk2 . (10)
E
k≥2

In the specific triangles used by the new PWM, the states

located at the ends of the large side generate the same common-
mode voltage [VCM ∗ = 0 in the example of Fig. 5(a)]. There-
fore, during the transition between these states, the double
commutation occurs, and the common-mode voltage remains
constant. Moreover, it can be noticed that the leg A is blocked
at the state +1 in the example of Fig. 5(a) (Flat Top). Thus, by
applying the states of the triangles in a circular sequence, only
two common-mode-voltage variations remain, as shown from
the waveform of Fig. 5(b) for one switching period (Ts).

E. Degrees of Freedom Provided by the Method

Triangles like the one shown in Fig. 5(a) can be found
anywhere in the vectorial diagram, with the same specific
shape and special features. Moreover, their different possible
orientations involve overlaps so that different triangles may
surround a single reference vector V ref . Indeed, depending
on the location of V ref among the areas defined in Fig. 7,
either two [Fig. 8(a)] or three [Fig. 8(b)] surrounding triangles
are suitable to build it up, as summarized in the first column of
Table I. This choice is free and is thereby a degree of freedom.
Furthermore, the orientation of the large side of the triangle is
determined by the blocked leg [13]. Consequently, this degree
of freedom is directly related to the choice of the homopolar Fig. 8. Degree of freedom: Choice of the triangle and its sequence of states.
component hNO . In the external and intermediate areas, each
leg has only one possible blocking level; thus, the number of TABLE I
possible values for hNO is equal to the number of triangles. NUMBER OF AVAILABLE TRIANGLES
In the internal area, however, a single leg might be blockable
to two different levels (with two different values for hNO ): this
leads to the same triangle but with a different sequence of states,
as shown in the example of Fig. 8(c). As a result, the number
of possible values for hNO ranges from two to five in the first
column of Table II.
The new PWM provides a second, and independent, degree As it has been stated earlier, the usefulness of the PWM
of freedom: the direction of the circular sequence of states. depends on both its performance in reducing common-mode
Indeed, the triangle of Fig. 5(a) is shown running a clockwise currents and its ability to balance the dc bus. Compared with
direction, but the opposite direction could as well be chosen. previous strategies, the degrees of freedom described above
3006 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 6, DECEMBER 2007
TABLE II
NUMBER OF AVAILABLE VALUES FOR THE HOMOPOLAR COMPONENT
Fig. 9. Real behavior of the commutations.
can be used to ensure the maximum effectiveness of the EMI
reduction and to control the dc-bus midpoint voltage.
IV. E FFECTIVENESS OF THE EMI R EDUCTION
A. Analysis of the Commutations
Strategies based upon double commutations assume that the
synchronism of the simultaneous commutations is accurate
enough to ensure an effective reduction of the common-mode
currents. However, the real behavior of the double commu-
tations strongly depends on their nature: diode-to-transistor
(D–T) or transistor-to-diode (T–D) [24]. This distinction im-
plies two main differences.
1) Real moment of the commutation: Given an elementary
cell switching from T2 to T1 [Fig. 9(a)], a T–D commu-
tation occurs as soon as T2 is off, whereas a D–T one
happens only after the dead time (T1 is on) [Fig. 9(b)].
2) Waveform of the voltage transition: D–T commutations
always involve high dν/dt variations, which are nearly
independent of the phase current. On the contrary, the
dν/dt of T–D commutations depends on the value of the
current and may significantly be reduced when operating
under low current [Fig. 9(b)].
B. EMC Constraints
PWM strategies can easily provide synchronous logic com-
mand orders so as to perform double commutations. However,
the phenomena described above must be taken into account
to find out whether a given double commutation is effective
or not.
1) Ensuring the synchronism: Considering several mega-
hertz oscillations on ICM (Fig. 4), a good elimination
can only be achieved if the duration between the two
supposedly simultaneous pulses is inferior to a few dozen
nanoseconds. Yet, typical dead times are much longer;
thus, the simultaneous commutations must not be shifted
by a dead-time effect. This problem can be solved by
making sure that simultaneous commutations are of the
same nature in order to avoid dead-time effects. This
condition is the first EMC constraint.
2) Optimizing the waveform compensation: The double
commutation is all the more effective as the common-
mode voltage does not vary at all during the process, i.e.,
the two voltage transitions on different legs are exactly
symmetrical, and, i.e., the simultaneous commutations
have got identical waveforms. Therefore, it seems ap-
propriate to ensure that all simultaneous commutations
are D–T. Furthermore, D–T commutations are the most
harmful ones (high dν/dt); for that reason, compensating
them in priority is natural. This is the second EMC
constraint.
C. Control of the New PWM to Meet the EMC Constraints
The very specificity of the new PWM is its ability to comply
with the mentioned EMC constraints—thanks to its degrees of
freedom [13].
1) First EMC constraint: The condition of performing simul-
taneous commutations of the same nature can be refor-
mulated as follows: “The currents in the two switching
legs must have opposite signs.” This constraint prohibits
the blocking of one leg; thus, the number of available
triangles drops down according to the second column of
Table I. Therefore, the number of available values for
hNO is also reduced, as shown in the second column of
Table II (the indeterminations of the tables depend on
the current/voltage phase difference and are not presented
here). Still, there is always at least one remaining choice;
consequently, the EMC constraint can always be satisfied.
Hence, all double commutations of the new PWM are
systematically controlled and perfectly synchronized.
2) Second EMC constraint: The second degree of freedom
is able to set the nature of all double commutations to
D–T. Indeed, the nature of a transition between two states
can be easily changed by switching the direction of the
circular sequence inside the chosen triangle. Moreover,
this degree of freedom has no influence on the choice of
the triangle; therefore, it is always possible to satisfy both
EMC constraints.
Thus, unlike previous modulations, it has been proven that
the proposed PWM is able to maximize the effectiveness of
all its double commutations, owing to an appropriate use of its
internal degrees of freedom. It requires only the signs of the out-
put currents, which are measured in motor-drive applications.
VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING
Fig. 10. Normalized balancing capacity according to the strategy.
V. M IDPOINT B ALANCING OF THE DC B US
A. Balancing Capacity
The ability to prevent the dc-bus midpoint from drifting
is a crucial issue for the safety of the structure. This is the
reason why particular emphasis will be put on the maximum
action that the PWM can provide to vary the dc-bus imbalance
[characterized by ∆us according to (7)]. From now on, this
maximum action will be referred to as the balancing capacity.
Assuming that the dc-bus imbalance (∆us) is initially posi-
tive, the maximum action is reached when the i0 current (Fig. 1)
is systematically chosen as great as possible (this way, d∆us/dt
is minimal [(8)] so as to bring ∆us back to zero as fast as possi-
ble). During the whole voltage-supply period “T0” (i.e., during
one complete revolution of the reference vector in Fig. 2),
the mean value i0 T0 is thereby maximal. According to (8),
it is representative of the fastest possible variation of ∆us
(in volts per second).
Thus, the balancing capacity is defined by i0 max T0 when,
for each switching period, the homopolar component hNO is
chosen so as to maximize i0 Ts in (9). Moreover, in order to
avoid any user-dependent quantity, the normalized balancing
capacity (i0 ∗ max T0 ) is introduced in (11) where Ik is the
rms value of the phase currents.
This is an objective criterion for comparing the balancing
performance of different strategies, with no dependence on any
external quantity such as the currents or the capacitances of the
dc bus
 √ 
i0 ∗ max T0 = i0 max T0 / Ik· 2 . (11)
B. DC-Bus-Control Method to Reach the Balancing Capacity
In order to fully exploit the balancing capacity of a strategy,
it is necessary to determine, for each switching period, the
value of the homopolar component hNO which maximizes (or
minimizes) i0 Ts in (9).
Whichever modulation is used, the value of hNO happens
to determine the distribution of the redundant states of Fig. 2
during the switching period. Moreover, given a pair of re-
dundant states located on the internal hexagon of the figure,
these two states, respectively, involve opposite values of i0
3007
[25]. Therefore, the maximization (or minimization) of this
particular i0 is obtained for a 100% distribution of one of these
two states. Furthermore, this extreme distribution is attained
in a Flat-Top situation. Likewise, it can be verified that the
maximum (or minimum) value of i0 Ts is always obtained
for a Flat-Top situation. Since there are only a few discrete
values of hNO involving a blocked leg (Flat-Top), it is possible
to calculate all corresponding values of i0 [with (9)] and then
select the adequate value of hNO (maximum or minimum
calculated i0 ).
As a consequence, even though CPWM strategies provide
infinite available values for hNO , their balancing capacity is the
same as DPWM strategies.
The presented method is quite straightforward, and a softer
regulation using intermediate values of hNO (CPWM only)
might look even more attractive. However, the necessity of
performing such an emergency balancing is likely to remain
occasional because the NPC inverter benefits from a natural
balancing phenomenon [26].
C. Comparison Between the Different Strategies
According to Table II, the first EMC constraint of the
new PWM reduces the number of available values for the
homopolar component hNO . To appreciate the consequence
of this reduction, Fig. 10 shows simulation results that are
calculated in ideal conditions (balanced sinusoidal output
currents) in order to compare different strategies. It repre-
sents the normalized balancing capacity of a conventional
DPWM (i0 ∗ max T0 Conv_DPWM : superior meshed surface)
and of the new modulation with the first EMC constraint
(i0 ∗ max T0 New_PWM : inferior grayed surface). It appears
that this constraint lowers the balancing capacity of the mod-
ulation, depending on the modulation depth and the phase
difference between the currents and voltages of the load.
For a better visualization, the relative degradation “D” [(12)]
between these two surfaces is shown in Fig. 11. It shows that
the worst case (impossible dc-bus balancing) is obtained at
the maximum modulation depth when the phase difference is
inferior to 30◦ (i.e., the power factor is above 0.866). Since the
nominal working point of induction motors tends to get close to
these values, this degradation of the balancing capacity may be
3008 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 6, DECEMBER 2007

Fig. 11. Degradation of the balancing capacity with the new PWM.

Fig. 13. (a) NPC inverter and (b) its control card.

Fig. 12. Example of the new carrier-based modulator.

worrying and may call for a compromise solution depending on

the working point. Still, the proposed PWM is able to perform Fig. 14. Experimental setup.
the dc-bus balancing in most situations, which is an advantage
for an EMI-reducing modulation Fig. 12 shows the generation of the correct sequence of states
within one switching period (for the example of Fig. 7 in case
i0 ∗ max Conv _DPWM −i ∗ max New_PWM the leg A is blocked at state +1 and runs a clockwise direction).
T0 0 T0
D = 100× ∗ Conv_DPWM
. Furthermore, it can be noticed that double commutations occur
i max
0 T0
(12) on discontinuities of the carriers.

VI. I MPLEMENTATION AND E XPERIMENTS
A. Carrier-Based Modulator
In order to comply with the low-cost and easy-to-implement
industrial requirements, a new carrier-based modulator has been
developed for the new PWM. It uses the principles described in
Section II-B, except that there are now four sawtooth carriers
(two increasing ones and two decreasing ones). The choice of
the blocked leg (i.e., the choice of the triangle: first degree
of freedom) is realized through the choice of the homopolar
component hNO just like any other DPWM. The two switching
legs must be compared with oppositely oriented carriers (one
increasing and one decreasing), and the choice of these orienta-
tions will determine the direction of the circular sequence inside
the triangle (second degree of freedom).
B. Experimental Setup
The proposed carrier-based modulation has been im-
plemented into a Texas Instruments DSP (TMS320F2812)
controlling a 20-kVA NPC prototype using insulated gate bipo-
lar transistors at a switching frequency of 20 kHz (Fig. 13).
The inverter is connected to a 300-V dc-bus (E) and feeds a
3-kW induction motor (Fig. 14). A line impedance stabilization
network protected by an EMC filter is located on the dc bus in
order to confine the conducted emissions.
C. Results
All double commutations of the new PWM behave like
the example of Fig. 15. The accuracy of their synchronism
and waveform compensation results in an almost constant
VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING
Fig. 15. Behavior of the double commutations (time: 80 ns/div, voltage:
50 V/div).
Fig. 16. Comparative oscilloscope diagrams: (a) Conventional DPWM and
(b) proposed PWM (time: 20 µs/div, voltage: 300 V/div, current: 0.5 A/div).
common-mode voltage [in this example, the leg C is blocked
(Flat-Top); thus, “VAO + VBO ” is an image of the common-
mode voltage (2)].
In the range of four switching periods, Fig. 16 compares a
conventional DPWM strategy (a) with the new PWM (b). The
synchronization of two commutations (b) effectively eliminates
two common-mode-current pulses (a) per switching period.
It can also be noticed that the VAO + VBO waveform (still
3009
Fig. 17. Importance of the EMC constraints: Proposed PWM without meeting
the (a) first or the (b) second constraint (time: 20 µs/div, voltage: 300 V/div,
current: 0.5 A/div).
Fig. 18. Peak-spectrum analysis of the common-mode current.
representative of VCM since the leg C is blocked for both
working points) complies with Fig. 5(b).
The importance of the EMC constraints is shown in Fig. 17.
If the first constraint is not met (a), then a thin common-
mode-voltage pulse (dead-time effect) provokes a significant
response on ICM . If the second constraint is not met (b), then
the efficiency of the EMI reduction is lowered.
When both constraints are met, the rms value of the common-
mode current is greatly reduced, with a roughly 40% gain of the
proposed PWM upon the conventional DPWM.
Frequency-domain measurements have been carried out with
a peak-spectrum analyzer (Fig. 18) and also confirm the EMC
improvement of the new PWM.
3010 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 6, DECEMBER 2007
Fig. 19. Example of the dc-bus balancing with the new PWM (time:
100 ms/div, voltages: 20 V/div (us1 and us2) and 10 V/div (∆us),
current: 2 A/div).
In order to investigate the dc-bus-balancing ability of the new
PWM, a simple hysteresis method has been used, and Fig. 19
shows the experimental results obtained for a unit modulation
depth with a 55◦ phase difference. The ∆us (Fig. 1) triangle-
shape waveform illustrates the effect of the balancing: it varies
around zero, between the hysteresis thresholds (dotted lines)
with a 20-V span (H).
VII. C ONCLUSION
This paper proposes a new carrier-based PWM which re-
duces the common-mode currents generated by the three-level
NPC inverters in motor-drive applications. It is shown that the
method provides several degrees of freedom which can maxi-
mize the EMI behavior of the drive by controlling the nature
of the double commutations and avoiding dead-time effects.
The crucial issue of the dc-bus balancing is also worked out
through a theoretical approach which can be applied to any kind
of modulation. Experimental results validate the theory and
confirm that the proposed PWM improves the EMC behavior of
the drive while still providing the dc-bus midpoint balancing.
The new PWM has been the subject of a patent submission
in 2006 [27] by Schneider Electric, the industrial partner of the
project.
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VIDET et al.: CARRIER-BASED PWM PROVIDING COMMON-MODE CURRENTS REDUCTION AND DC-BUS BALANCING 3011

Arnaud Videt received the M.S. degree in electri-
cal engineering from the University of Lille, Lille,
France, in 2005. He is currently working toward
the Ph.D. degree in electrical engineering at the
Laboratoire d’Electrotechnique et d’Electronique de
Puissance, Ecole Centrale de Lille, Lille.
His main research interests include power elec-
tronics and electromagnetic compatibility for motor-
drive applications.
digital electronics and power electronics for adjustable-speed drives.
Philippe Baudesson received the Ph.D. degree in
electrical engineering, focusing on power electron-
ics, from the Institut National Polytechnique de
Toulouse, Toulouse, France, in 2000.
He has been a Research Engineer with Alstom
Technology and Schneider Electric. He is currently
with Schneider Toshiba Inverter Europe, Pacy-sur-
Eure, France, where he is in charge of the Electronic
R&D Department and takes part in drive design and
follows anticipation actions for the improvement of
variable speed drives. His research interests include

Philippe Le Moigne (M’93) received the Engineer-

ing degree from the Institut Industriel du Nord, Lille,
France, in 1986 and the Ph.D. degree in electri-
cal engineering from the University of Lille, Lille,
in 1990.
He is currently a Professor with the Laboratoire
d’Electrotechnique et d’Electronique de Puissance,
Ecole Centrale de Lille, Lille, where he is also the
Head of the Power Electronics Department. His ma-
jor fields of interest include hard switched power
converters and supercapacitors, especially the con-
trol of multilevel topologies for medium- and high-power applications with the
aim of high power quality and high efficiency.

Nadir Idir (M’01) received the Ph.D. degree from
the University of Lille, Lille, France, in 1993.
Since 1994, he has been an Associate Professor
with the University of Lille. He is currently with
the Laboratoire d’Electrotechnique et d’Electronique
de Puissance, University of Lille. His main research
interests include power electronics and electromag-
netic compatibility for power converters.
Xavier Cimetière received the Engineering degree
from Ecole Centrale de Lille, Lille, France.
Since 1992, he has been a Research Engineer with
the Laboratoire d’Electrotechnique et d’Electronique
de Puissance, Ecole Centrale de Lille, Lille. His
research interests include power electronics and the
control of electric machines.