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37’2009 (-----)
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Abstract - This paper describes a Web-based digital logic circuits simulator. System is realised in Java programming language and can be
executed as a standalone Java application or Java applet. Simulator can be used in educational purposes like an appendix of standard
learning methods or like a part of distance learning systems on Internet. System support composite model, i.e. it is possible to evolve
independence composition with arbitrary number of input and output, which is composed of basic digital logic elements, and use altogether.
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Tel.:+381631045301; е-mail:jovanovic@vpskp.edu.rs
Paleta Sistem Konekcija Port Kompozicija
Editor
IN Entitet OUT
Modified class named ActiveEntity should has all Fig. 5. Control part
attributes of class Entity, but it should define others
possibilities. Following command buttons are available:
Class ActiveEntity has to be subclass of class Entity, Connection; enable connection of basic logic elements
and since Java does not support concept of multi Input; defines input values
inheritance, in order to embed facilities of executing Output; defines output values
independent activities into class ActiveEntity, it has to NOT element; enables insertion on white drawing area
implement interface Runnable (Listing 1.) logic element which simulate operation NOT logic
gate.
SIMULATOR CAPABILITY OR element; enables insertion logic element which
simulate operation OR logic gate.
Visual simulator contains series control buttons. User NOR element; enables insertion logic element which
can edit arbitrary switch circuit and control simulation simulate operation NOR logic gate.
process. AND element; enables insertion logic element which
After starting the software system, one can use basic simulate operation AND logic gate.
system window (figure 4.). This window contains two parts. NAND element; enables insertion logic element which
First part is palette of command buttons, and the second is simulate operation NAND logic gate.
white drawing area. Half-adder; enables insertion logic element which
The three basic logic gates are the NOT gate, the AND simulate half-adder operation.
gate, and the OR gate. These are symbolized as in figures 4 Full-Adder; enables insertion logic element which
and 5. User can combine these basic gates as building simulate full-adder operation.
blocks for more complex circuits. User can build his Composition; enables insertion on white drawing area
circuits using an on-line logic circuit simulator. User can composition with arbitrary number of input and output
open a new browser window and go to the page [1] to run afterward defined
the simulator. To use the simulator user can click and drag Displacement component; this button enables
logic gates and other elements onto the page and connect operating mode of displacement element over drawing
them to form circuits. area.
Delete; this button deletes all elements on drawing area
and set initially system state.
Info; this button gives basic system information.
Help; this button gives basic information about
working with system.
Desktop
a. b.
Fig. 7. Connection drawing is optimized
CONCLUSIONS REFERENCES
In this paper, we have described digital logic circuits
simulator, which is realised in Java programming language. [1] A software demo:
System enables arbitrary switch circuit design using basic http://weblab.vpskp.edu.yu/osovi/logicsim/index.htm
logic circuits and simulation of designed module. [2] http://www.tetzl.de/java_logic_simulator.html
Environment is interactive, topologies are arbitrary, so that [3] (SirSim)C. B. McDonald and R.E. Bryant. Symbolic
it is possible to fabricate and execute many laboratory timing simulation using cluster scheduling. In
exercises. System enables students in introductory courses Proceedings of the 37th conference on Design
automation, 2000, pp. 254-259.
to design and simulate logic circuits. Simulator is Web-
[4] Silos User’s Manual Version 2002.1. By Simucad Inc.,
based and can be used as a part of distance learning system 2002.0
or electronic classroom. [5] ModelSim SE, PSL Assertions Guide. Version 5. 8 Beta.
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[6] N.Jovanović, R.Popović, Z.Jovanović, Defining a
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[7] N.Jovanović, R.Popović, Z.Jovanović, Modeling
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[8] N.Jovanović, R.Popović, Z.Jovanović, Modeling
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