DLD Assignment 2

NAME:-PARLA SURENDRA MANI KUMAR
ENROLL NO:- 16116043
1) Source code :-
module vga_top(
input clk,
input reset,
input [11:0] sw,
output reg [3:0] vgaRed,
output reg [3:0] vgaGreen,
output reg [3:0] vgaBlue,
output Hsync,
output Vsync
);
reg hvedio_on;
reg [9:0]x;
reg [9:0]y;
VGA VGA(clk,reset,Hsync,Vsync,hvedio_on,x,y);
always@(posedge clk,posedge reset)
begin
if(reset == 1 || hvedio_on == 0)
begin
vgaRed = 0;
vgaGreen = 0;
vgaBlue = 0;
end
else
begin
assign vgaRed = sw[3:0];
end
end
endmodule
//vga module code
`timescale 1ps / 1ps
module VGA(
input clk_100,
input reset,
output reg hsync ,
output reg vsync ,
output reg hvedio_on,
output reg [9:0]x,
output reg [9:0]y
);
reg [1:0] count;
reg clk_25;
initial begin
count = 0;
end
always@(posedge clk_100 , posedge reset )
if(reset==1 || count == 3)
count = 0;
else
count = count + 1;
always@(posedge clk_100)
begin
case(count)
2'b00:
clk_25 <= 1;
2'b01:
clk_25 = 1;
2'b10:
clk_25 = 0;
2'b11:
clk_25 = 0;
endcase
end
localparam HD = 640, // horizontal display area
HF = 48 , // h. front (left) border
HB = 16 , // h. back (right) border
HR = 96 , // h. retrace
VD = 480, // vertical display area
VF = 10,// v. front (top) border
VB = 33, // v. back (bottom) border
VR = 2;
always @(posedge clk_25 or posedge reset)
begin
if (reset)
begin
x <= 0;
y <= 0;
end
else
begin
if (x < (HD + HF + HR + HB - 1))
x <= x + 1;
else
begin
x <= 0;
if (y < (VD + VF + VB + VR -1))
y <= y + 1;
else
y <= 0;
end
end
end
begin
assign hsync = (x >= HD + HF + HB ) ? 1:0;
assign vsync = (y >= VD + VF + VB ) ? 1:0;
assign hvedio_on = (( x < HF + HD && x > HF) && (y > VF && y < VF + VD)) ? 1:0;
end
endmodule
TESTBENCH:-
`timescale 1ns / 1ps
module test();
reg clk;
reg reset;
wire hsync;
wire vsync;
wire hvedio_on;
wire [9:0]x;
wire [9:0]y;
integer k = 0;
initial begin
reset = 0;
clk = 1;
k = 0;
while(k<10000000)
begin
#0.05 clk = ~clk ;
k = k+1;
end
end
VGA VGA(clk , reset , hsync , vsync , hvedio_on , x,y);
Endmodule
TIMING DIAGRAMS:-
CONSTRAINT FILE:-
##clocksignal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]

set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
##VGA Connector
set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]

set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
set_property PACKAGE_PIN P19 [get_ports Hsync]
set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
set_property PACKAGE_PIN R19 [get_ports Vsync]
set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
2)
In this question we have to make some changes in the vga_top module code
of (1) and the rest code part will be same.
Code:-
module vga_top(
input clk,
input reset,
input [11:0] sw,
output Hsync,
output Vsync
);
reg hvedio_on;
reg [9:0]x;
reg [9:0]y;
localparam r = 30,
cx = 399,
cy = 263;
begin
if(reset == 1 || hvedio_on == 0 || ((x-cx)*(x-cx) + (y-cy)*(y-cy)) > r*r )
begin
vgaRed = 0;
vgaGreen = 0;
vgaBlue = 0;
end
else
begin
end
end
endmodule
NOTE:-The circle equation will be added as a condition

Family of circles code:-
module vga_top(
input clk,
input reset,
input [11:0] sw,
input [3:0] sel,
output Hsync,
output Vsync
);
reg hvedio_on;
reg [9:0]x;
reg [9:0]y;
localparam
cx = 399,
cy = 263;
reg [8:0] r;
begin
if(reset == 1 || hvedio_on == 0 || ((x-cx)*(x-cx) + (y-cy)*(y-cy)) > r*r )
begin
vgaRed = 0;
vgaGreen = 0;
vgaBlue = 0;
end
else
begin
end
end
begin
case(sel)
4'b0000: r = 30;
4'b0001: r = 50;
4'b0010: r = 100;
4'b1111: r = 150;
default: r = 200;
endcase
end
endmodule
3)
Sourcecode:-
module vga_test(
input clk,
input reset,
output[11:0] rgb,
output h_sync,
output v_sync
);
reg[11:0] rgb_reg;
wire[9:0] x;
wire[9:0] y;
wire video_on;
wire[11:0] rgb_image;
vga_sync vs( clk,reset,x,y,h_sync,v_sync,video_on);
image_memory im_mem(x, y,rgb_image);
assign rgb = video_on?rgb_image:12'd0;
endmodule
module image_memory(
input[9:0] x,
input[9:0] y,
output [11:0] rgb
);
localparam rows = 10'd480;
localparam columns = 10'd640 ;
reg[11:0] rgb_values [0:rows * columns-1];
initial begin
$readmemb("C:\Users\lenovo\Downloads\image.txt", rgb_values);
end
assign rgb = rgb_values[y*rows + x];
endmodule
module vga_sync(
input clk_100,
input reset,
output reg [9:0]x,
output reg [9:0]y,
output reg hsync ,
output reg vsync ,
output reg hvedio_on );

reg [1:0] count;
reg clk_25;
initial begin
count = 0;
end
count = 0;
else
count = count + 1;
begin
case(count)
2'b00:
clk_25 <= 1;
2'b01:
clk_25 = 1;
2'b10:
clk_25 = 0;
2'b11:
clk_25 = 0;
endcase
end

VR = 2;
begin
if (reset)
begin
x <= 0;
y <= 0;
end
else
begin
if (x < (HD + HF + HR + HB - 1))
x <= x + 1;
else
begin
x <= 0;
if (y < (VD + VF + VB + VR -1))
y <= y + 1;
else
y <= 0;
end
end
end
begin
end
endmodule
TESTBENCH:-
module testbench( );
reg clk;
reg reset;
initial begin
clk = 0;
reset = 0;
#5 reset = ~reset;
#5 reset = ~reset;
end
always #5 clk = ~clk;
wire h_sync,v_sync;
wire[11:0] rgb;
vga_test vt(.clk, reset, h_sync, v_sync,rgb);
endmodule
RTL Analysis:-
CONSTRAINT FILE:-
##VGA Connector
set_property PACKAGE_PIN G19 [get_ports {rgb[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {rgb[0]}]
set_property PACKAGE_PIN H19 [get_ports { rgb [1]}]
set_property IOSTANDARD LVCMOS33 [get_ports { rgb [1]}]
set_property PACKAGE_PIN J19 [get_ports { rgb [2]}]
set_property PACKAGE_PIN N19 [get_ports { rgb [3]}]
set_property PACKAGE_PIN N18 [get_ports { rgb [4]}]
set_property PACKAGE_PIN L18 [get_ports { rgb [5]}]
set_property PACKAGE_PIN K18 [get_ports {rgb[6]}]
set_property PACKAGE_PIN H17 [get_ports { rgb [9]}]
set_property PACKAGE_PIN G17 [get_ports { rgb [10]}]
set_property PACKAGE_PIN D17 [get_ports { rgb [11]}]
set_property IOSTANDARD LVCMOS33 [get_ports rgb [11]}]

4)source code:-
module ps2_rx(
input wire clk,reset,
input wire ps2d,ps2c,rx_en,
output wire [7:0] scan_code,
output reg rx_done
);
localparam
idle = 1'b0,
rx = 1'b1;
reg state_reg,state_next;
reg [7:0] f_reg;
reg [7:0] f_nxt;
reg f_reg_value;
reg f_nxt_value;
reg neg_edge;
begin
if(reset)
begin
f_reg <= 0;
f_reg_value <= 0;
end
else
begin
f_reg <= f_nxt;
f_reg_value <= f_nxt_value;
end
assign f_nxt = {ps2c,f_reg[7:1]};
assign f_nxt_value = (f_reg == 8'b11111111)? 1'b1:(f_reg == 8'b00000000)?

1'b0:f_reg_value;
assign neg_edge = f_reg_value & ~f_nxt_value;
end
reg [3:0] n_reg, n_next;
reg [10:0] d_reg, d_next;
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
d_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
d_reg <= d_next;
end
// FSMD next state logic

always @*
begin
state_next = state_reg;
rx_done = 1'b0;
n_next = n_reg;
d_next = d_reg;
case (state_reg)
idle:
if (neg_edge & rx_en)
begin
n_next = 4'b1010;
state_next = rx;
end
rx:
begin
if (neg_edge)
begin
d_next = {ps2d, d_reg[10:1]};
n_next = n_reg - 1;
end
if (n_reg==0)
begin
rx_done = 1'b1;
state_next = idle;
end
end
endcase
end
assign scan_code = d_reg[8:1];

endmodule
module ignore_break(
input reset,
input rx_done,
input [7:0] scan_code,
output [7:0]scan_out
);
localparam normal_state = 2'd0;
localparam ignore_state = 2'd1;
localparam ignore_state2 = 2'd2;
reg[1:0] state,state_next;
//we will check for every posedge done_tick

always@( posedge rx_done or posedge reset)begin
if(reset) state <= normal_state;
else state <= state_next;
end
always@(*) begin
state_next <= normal_state;
case(state)
normal_state:begin
if(scan_code == 8'hF0)begin
state_next <= ignore_state;
end
else state_next <= normal_state;
end
ignore_state:begin
state_next <= ignore_state2;
end
ignore_state:begin
end
endcase
end
assign scan_out = ((state == normal_state)&rx_done)?scan_code:8'd0;

endmodule
module sw(
input clk,
input rst,
input stp,
input srt,
output reg [3:0] msec,
output reg [3:0] sec0,
output reg [3:0] sec1,
output reg [3:0] min
);
reg [31:0]count = 0;
reg [1:0]state = S0;
reg en = 0;
integer timer = 49;
localparam
S0 = 2'b00,
S1 = 2'b01,
S2 = 2'b10,
S3 = 2'b11;
always@(posedge clk,posedge rst,posedge stp,posedge srt)
begin
case(state)
S0: begin
count = 0;
en = 0;
msec = 0;
sec0 = 0;
sec1 = 0;
min = 0;
if(srt==1)begin
state = S1;
en = 1;
end
end
S1: begin
en = 1;
if(stp==1) begin
en =0;
state = S2;
end
end
S2: begin
en = 0;
if(srt == 1)begin
en = 1;
state = S1;
end
if(rst == 1)begin
en = 0;
state = S0;
count = 0;
end
end
endcase
end
always @ (posedge clk or posedge rst)
begin
if(rst)
count <= 0;
else if(count == timer)
count <= 0;
else if(en)
count <= count + 1;
end
assign click = ((count == timer)?1'b1:1'b0);

always@(posedge clk)
begin
if(rst)
begin
msec <= 0;
sec0 <= 0;
sec1 <= 0;
min <= 0;
end
if (click)
begin
if(msec == 9)
begin //if_1
msec <= 0;
if (sec0== 9) //xx99
begin // if_2
sec0<= 0;
if (sec1 == 5) //x599 - the two digit seconds digits
begin //if_3
sec1 <= 0;
if(min == 9) //9599 - The minute digit
min <= 0;
else
min <= min + 1;
end
else //else_3
sec1 <= sec1 + 1;
end
else //else_2
sec0<= sec0+ 1;
end
else //else_1
msec <= msec + 1;
end
end
endmodule
module testbench_ps2_rx(
);
reg ps2c;
reg ps2d;
reg reset;
wire[7:0] scan_code;
wire done_tick;
initial begin
reset = 0;
#5 reset = 1;
#5 reset = 0;
end
initial begin
ps2c = 1;ps2d = 0;
#15 ps2c = 0; //idle to start_reciving
#5 ps2c = 1; ps2d = 0; //start_bit
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 1; //d0
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 0; //d1
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 0; //d2
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 0; //d3
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 0; //d4
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 1; //d5
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 0; //d6
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 0; //d7
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 1; //parity_bit
#5 ps2c = 0;
#5 ps2c = 1; ps2d = 1; //end_bit
#5 ps2c = 0;
#5 ps2c = 1;
end
ps2_rx ps2( reset,ps2c, ps2d, scan_code,done_tick);

endmodule
RTL Analysis:-
CONSTRAINT FILE:-
## Clock signal
set_property PACKAGE_PIN W5 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]
## buttons
set_property PACKAGE_PIN U18 [get_ports {reset}]
set_property IOSTANDARD LVCMOS33 [get_ports {reset}]
##USB HID (PS/2)
set_property PACKAGE_PIN C17 [get_ports {ps2c}]
set_property IOSTANDARD LVCMOS33 [get_ports {ps2c}]
set_property PULLUP true [get_ports {ps2c}]
set_property PACKAGE_PIN B17 [get_ports {ps2d}]
set_property IOSTANDARD LVCMOS33 [get_ports {ps2d}]
set_property PULLUP true [get_ports {ps2d}]
##leds
set_property PACKAGE_PIN U16 [get_ports {d0}]
set_property IOSTANDARD LVCMOS33 [get_ports {d0}]

set_property PACKAGE_PIN E19 [get_ports {d1}]
set_property PACKAGE_PIN U19 [get_ports {d2}]
set_property PACKAGE_PIN V19 [get_ports {d3}]
5) module VGA(
input clk_100,
input reset,
output reg hsync ,
output reg vsync ,
output reg hvedio_on,
output reg [9:0]x,
output reg [9:0]y
);
reg [1:0] count;
reg clk_25;
initial begin
count = 0;
end
count = 0;
else
count = count + 1;
begin
case(count)
2'b00:
clk_25 <= 1;
2'b01:
clk_25 = 1;
2'b10:
clk_25 = 0;
2'b11:
clk_25 = 0;
endcase
end
VR = 2;
begin
if (reset)
begin
x <= 0;
y <= 0;
end
else
begin
if (x < (HD + HF + HR + HB - 1))
x <= x + 1;
else
begin
x <= 0;
if (y < (VD + VF + VB + VR -1))
y <= y + 1;
else
y <= 0;
end
end
end
begin
end
endmodule
module ps2_rx(
input wire clk,reset,
input wire ps2d,ps2c,rx_en,
output wire [7:0] scan_code,
output reg rx_done
);
localparam
idle = 1'b0,
rx = 1'b1;
reg state_reg,state_next;
reg [7:0] f_reg;
reg [7:0] f_nxt;
reg f_reg_value;
reg f_nxt_value;
reg neg_edge;
begin
if(reset)
begin
f_reg <= 0;
f_reg_value <= 0;
end
else
begin
f_reg <= f_nxt;
f_reg_value <= f_nxt_value;
end
assign f_nxt = {ps2c,f_reg[7:1]};
assign f_nxt_value = (f_reg == 8'b11111111)? 1'b1:(f_reg == 8'b00000000)?

1'b0:f_reg_value;
assign neg_edge = f_reg_value & ~f_nxt_value;
end
reg [3:0] n_reg, n_next;
reg [10:0] d_reg, d_next;
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
d_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
d_reg <= d_next;
end
// FSMD next state logic

always @*
begin
state_next = state_reg;
rx_done = 1'b0;
n_next = n_reg;
d_next = d_reg;
case (state_reg)
idle:
if (neg_edge & rx_en)
begin
n_next = 4'b1010;
state_next = rx;
end
rx:
begin
if (neg_edge)
begin
d_next = {ps2d, d_reg[10:1]};
n_next = n_reg - 1;
end
if (n_reg==0)
begin
rx_done = 1'b1;
state_next = idle;
end
end
endcase
end
assign scan_code = d_reg[8:1];

endmodule
module ignore_break(
input reset,
input rx_done,
input [7:0] scan_code,
output [7:0]scan_out
);
localparam normal_state = 2'd0;
localparam ignore_state = 2'd1;
localparam ignore_state2 = 2'd2;
reg[1:0] state,state_next;
//we will check for every posedge done_tick

always@( posedge rx_done or posedge reset)begin
if(reset) state <= normal_state;
else state <= state_next;
end
always@(*) begin
case(state)
normal_state:begin
if(scan_code == 8'hF0)begin
state_next <= ignore_state;
end
else state_next <= normal_state;
end
ignore_state:begin
state_next <= ignore_state2;
end
ignore_state:begin
end
endcase
end
assign scan_out = ((state == normal_state)&rx_done)?scan_code:8'd0;

CONSTRAINT FILE:-
##VGA Connector
set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]

set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
set_property PACKAGE_PIN C17 [get_ports ps2c]
set_property IOSTANDARD LVCMOS33 [get_ports ps2c]
set_property PULLUP true [get_ports ps2c]
set_property PACKAGE_PIN B17 [get_ports ps2d]
set_property IOSTANDARD LVCMOS33 [get_ports ps2d]
set_property PULLUP true [get_ports ps2d]
##Buttons
set_property PACKAGE_PIN U18 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
6)
Sourcecode:-
module multiplier(
input [31:0]in1,
input [31:0]in2,
output reg [31:0]out
);
reg [47:0]mantisa;
reg [23:0]man1;
reg [23:0]man2;
reg [7:0] expo;
reg [1:0]temp;
always@(*) begin
out[31] = in1[31]^in2[31];
expo = in1[30:23] + in2[30:23] - 127;
man1 = {1'b1,in1[22:0]};
man2 = {1'b1,in2[22:0]};
mantisa = man1*man2;
temp = mantisa[47:46];
case(temp)
2'b11:begin
expo = expo + 1;
out[22:0] = mantisa[46:24];
end
2'b10:begin
expo = expo + 1;
out[22:0] = mantisa[46:24];
end
2'b01:out[22:0] = mantisa[45:23];
endcase
out[30:23] = expo;
end
endmodule
TESTBENCH:-
module testbench();
reg [31:0]in1;
reg [31:0]in2;
wire [31:0]out;
initial begin
in1 = 32'b11000001100101000000000000000000;
in2 = 32'b01000001000110000000000000000000;
end
multiplier multi(in1,in2,out);
endmodule
Calculations:-
In1 = -18.5 , in2 = 9.5 .So, output should be -175.75
IEEE Format:-
In1 = 11000001100101000000000000000000
In2 = 01000001000110000000000000000000
Out= 11000011001011111100000000000000
RTL Analysis:-
7) module lock(input wire a,b,reset,clk, output reg led);

reg p,q;
reg[2:0] state;
reg [2:0] state_next;
reg [5:0] check;
always@(posedge a or posedge b)
state_next=state+1;
always@(posedge a,posedge clk)

if(a)p=1;
else p=0;
always@(posedge b,posedge clk)
if(b) q=1;
else q=0;
always@(posedge clk or posedge reset)
if(reset)begin
state<=0;
state_next<=0;
end
else begin
case(state_next)
3'b001:
if(q) check[5]=1;
else check[5]=0;
3'b010:
if(q) check[4]=1;
else check[4]=0;
3'b011:
if(q) check[3]=1;
else check[3]=0;
3'b100:
if(q) check[2]=1;
else check[2]=0;
3'b101:
if(q) check[1]=1;
else check[1]=0;
3'b110:
if(q) check[0]=1;
else check[0]=0;
default :xxxxx;
endcase
end
always@(posedge clk)
if(state_next==3'b110&&check==6'b011001)
led=1;
else led=0;
endmodule
LCD interface:-
module PmodCLP(
btnr,CLK, JA, JB );
input btnr; // use BTNR as reset input
input CLK; // 100 MHz clock input
output [7:0] JA;
output [6:4] JB;
wire [7:0] JA;
wire [6:4] JB;
parameter [3:0] stFunctionSet = 0,
stDisplayCtrlSet = 1,
stDisplayClear = 2,
stPowerOn_Delay = 3,
stFunctionSet_Delay = 4,
stDisplayCtrlSet_Delay = 5,
stDisplayClear_Delay = 6,
stInitDne = 7,
stActWr = 8,
stCharDelay = 9;
reg [6:0] clkCount = 7'b0000000;
reg [20:0] count = 21'b000000000000000000000; // 21 bit count variable for timing delays
wire delayOK; // High when count has reached the right delay time
reg oneUSClk; // Signal is treated as a 1 MHz clock
reg [3:0] stCur = stPowerOn_Delay; // LCD control state machine
reg [3:0] stNext;
wire writeDone; // Command set finish
parameter [9:0] LCD_CMDS[0:23] = {
{2'b00, 8'h3C}, // 0, Function Set
{2'b00, 8'h0C}, // 1, Display ON, Cursor OFF, Blink OFF
{2'b00, 8'h01}, // 2, Clear Display
{2'b00, 8'h02}, // 3, Return Home
{2'b10, 8'h48}, // 4, H
{2'b10, 8'h65}, // 5, e
{2'b10, 8'h6C}, // 6, l
{2'b10, 8'h6C}, // 7, l
{2'b10, 8'h6F}, // 8, o
{2'b10, 8'h20}, // 9, blank
{2'b10, 8'h46}, // 10, F
{2'b10, 8'h72}, // 11, r
{2'b10, 8'h6F}, // 12, o
{2'b10, 8'h6D}, // 13, m
{2'b10, 8'h20}, // 14, blank

{2'b10, 8'h44}, // 15, D
{2'b10, 8'h69}, // 16, i
{2'b10, 8'h67}, // 17, g
{2'b10, 8'h69}, // 18, i
{2'b10, 8'h6C}, // 19, l
{2'b10, 8'h65}, // 20, e
{2'b10, 8'h6E}, // 21, n
{2'b10, 8'h74}, // 22, t
{2'b00, 8'h18} // 23, Shift left
};
reg [4:0] lcd_cmd_ptr;
always @(posedge CLK) begin
if(clkCount == 7'b1100100) begin
clkCount <= 7'b0000000;
oneUSClk <= ~oneUSClk;
end
else begin
clkCount <= clkCount + 1'b1;
end
end
always @(posedge oneUSClk) begin
if(delayOK == 1'b1) begin
count <= 21'b000000000000000000000;
end
else begin
count <= count + 1'b1;
end
end
assign delayOK = (
((stCur == stPowerOn_Delay) && (count == 21'b111101000010010000000)) || // 2000000 -> 20 ms
((stCur == stFunctionSet_Delay) && (count == 21'b000000000111110100000)) || // 4000 -> 40 us
((stCur == stDisplayCtrlSet_Delay) && (count == 21'b000000000111110100000)) || // 4000 -> 40 us
((stCur == stDisplayClear_Delay) && (count == 21'b000100111000100000000)) || // 160000 -> 1.6 ms
((stCur == stCharDelay) && (count == 21'b000111111011110100000)) // 260000 -> 2.6 ms - Max
Delay for character writes and shifts
) ? 1'b1 : 1'b0;
assign writeDone = (lcd_cmd_ptr == 5'd23) ? 1'b1 : 1'b0;
if((stNext == stInitDne || stNext == stDisplayCtrlSet || stNext == stDisplayClear) && writeDone ==
1'b0) begin
lcd_cmd_ptr <= lcd_cmd_ptr + 1'b1;
end
else if(stCur == stPowerOn_Delay || stNext == stPowerOn_Delay) begin
lcd_cmd_ptr <= 5'b00000;
end
else begin
lcd_cmd_ptr <= lcd_cmd_ptr;
end
end
if(btnr == 1'b1) begin
stCur <= stPowerOn_Delay;
end
else begin
stCur <= stNext;
end
end
always @(stCur or delayOK or writeDone or lcd_cmd_ptr) begin
case (stCur)
stPowerOn_Delay : begin
stNext <= stFunctionSet;
end
else begin
stNext <= stPowerOn_Delay;
end
end
stFunctionSet : begin
stNext <= stFunctionSet_Delay;
end
stFunctionSet_Delay : begin
stNext <= stDisplayCtrlSet;
end
else begin
stNext <= stFunctionSet_Delay;
end
end
stDisplayCtrlSet : begin
stNext <= stDisplayCtrlSet_Delay;
end
stDisplayCtrlSet_Delay : begin
stNext <= stDisplayClear;
end
else begin
stNext <= stDisplayCtrlSet_Delay;
end
end
stDisplayClear : begin
stNext <= stDisplayClear_Delay;
end
stDisplayClear_Delay : begin
stNext <= stInitDne;
end
else begin
stNext <= stDisplayClear_Delay;
end
end
stInitDne : begin
stNext <= stActWr;
end
stActWr : begin
stNext <= stCharDelay;
end
stCharDelay : begin
stNext <= stInitDne;
end
else begin
stNext <= stCharDelay;
end
end
default : stNext <= stPowerOn_Delay;
endcase
end
assign JB[4] = LCD_CMDS[lcd_cmd_ptr][9];
assign JB[5] = LCD_CMDS[lcd_cmd_ptr][8];
assign JA = LCD_CMDS[lcd_cmd_ptr][7:0];
assign JB[6] = (stCur == stFunctionSet || stCur == stDisplayCtrlSet || stCur == stDisplayClear || stCur ==
stActWr) ? 1'b1 : 1'b0;
endmodule

DLD Assignment 2

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DLD Assignment 2

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NAME:-PARLA SURENDRA MANI KUMAR

ENROLL NO:- 16116043

//vga module code

`timescale 1ps / 1ps

output reg vsync ,

output reg hvedio_on,

output reg [9:0]x,

output reg [9:0]y

reg [1:0] count;

always@(posedge clk_100 , posedge reset )

HF = 48 , // h. front (left) border

HB = 16 , // h. back (right) border

VD = 480, // vertical display area

VF = 10,// v. front (top) border

VB = 33, // v. back (bottom) border

always @(posedge clk_25 or posedge reset)

if (x < (HD + HF + HR + HB - 1))

if (y < (VD + VF + VB + VR -1))

assign hsync = (x >= HD + HF + HB ) ? 1:0;

assign vsync = (y >= VD + VF + VB ) ? 1:0;

`timescale 1ns / 1ps

#0.05 clk = ~clk ;

VGA VGA(clk , reset , hsync , vsync , hvedio_on , x,y);

set_property PACKAGE_PIN W5 [get_ports clk]

set_property IOSTANDARD LVCMOS33 [get_ports clk]

create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

set_property PACKAGE_PIN V17 [get_ports {sw[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]

set_property PACKAGE_PIN V16 [get_ports {sw[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]

set_property PACKAGE_PIN W16 [get_ports {sw[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]

set_property PACKAGE_PIN W17 [get_ports {sw[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]

set_property PACKAGE_PIN W15 [get_ports {sw[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]

set_property PACKAGE_PIN V15 [get_ports {sw[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]

set_property PACKAGE_PIN W13 [get_ports {sw[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]

set_property PACKAGE_PIN V2 [get_ports {sw[8]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]

set_property PACKAGE_PIN T3 [get_ports {sw[9]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]

set_property PACKAGE_PIN T2 [get_ports {sw[10]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]

set_property PACKAGE_PIN R3 [get_ports {sw[11]}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]

set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]

set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]

set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]

set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]

set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]

set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]

set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]