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A Brief Study of

Reconfigurable Computation
Systems with a focus of FPGA
based devices

Bipul Islam
4th Year CSE group II
Reconfigurable Computing
A peek into the future of computing

‘Computing’comes from the Latin word, ‘compute’, which mean -- to calculate.

One of the greatest accomplishments of humans have been to automate this process
of computing to inexplicable limits. The computing speeds have manifested over
combined development of both computer science as well as electronics. The
electronics boom as predicted by Moore held good and human ability of
computation turned in-human in the timescale of mere decades.

From the humble beginning with just a few semiconductors on a single board, the
Integrated circuits have lost their macro scales and now boast of cutting edge
technology with millions of semiconductor devices on miniscule capsules. We are
living in an edge where the IC’s form a hidden category of machines that form the
backbone of our modern life-style electronics.

With each advancement in the field of IC’s (with respect to complexity) there has
been a visible advancement in ability of representing more and more complex
algorithms in machines. Complex ICs either enable us to write hardwired
algorithms, or, Software programs on standard ICs for representing the algorithms.
However there is a limitation -- hardwired logic has a high performance but are not
lack the flexibility, and the software-programmed logic has high flexibility but
performance does not match the hardwired logic devices.

Reconfigurable computing tries to blur this difference of hardwired logic and

software programmed logic. It tries to introduce a programmability in the
hardware itself, this will bring flexibility to the hardwired logic as well as improve
the performance of the software programmed logic. The principal difference when
compared to using ordinary microprocessors is the ability to make substantial
changes to the data path itself in addition to the control flow. On the other hand,
the main difference with custom hardware, i.e. application-specific integrated
circuits (ASICs) is the possibility to adapt the hardware during runtime by
"loading" a new circuit on the reconfigurable fabric.

Beginning of Re-configurable

The concept of reconfigurability in hardware was first proposed by Gerald Estrin

in 1960‘s when he idealized a computer made of a standard processor and an array
of ‘reconfigurable’hardware. The main processor would control the behavior of the
reconfigurable hardware and the hardware could be quickly tailored to perform
specific tasks (like, image processing, pattern matching) as quickly as any
dedicated hardware for the purpose. Again once this task was over, the system
could be reprogrammed on the fly for a different job at hand. This resulted in a
Hybrid computing structure that was well ahead of his times for G. Estrin.

However, with the advent of silicon based devices and more research in the field of
reconfigurability or programmability in the hardware in 1980s and 1990s, small
scale reconfigurable prototypes could be developed. But world received it’s first
commercial reconfigurable computer ALGOTRONIX CH2X4 in 1991 from the
Xilinx (who were the inventors of the concept of FPGA-- field programmable gate

Classification of the Re-configurable


The reconfigurable devices are classified into two classes:

(i) Hybrid systems

(ii) Fully-FPGA based systems

Both architectures are designed to scale the reconfigurability to large-scale

systems. They can be used in the traditional CPU cluster computer and network
intra structures.

The hybrid computers usually combine a single or a couple of reconfigurable logic

chips or FPGA’s with a standard microprocessor CPU. This can be done by
exchanging a CPU on a multi CPU board with an FPGA, (such a setup is called
hybrid-core computing) or, adding a PCI/PCI Express based expansion card to the
computer. Simplified, they are Von-Neumann based architectures with an
integrated FPGA accelerator.

Fully FPGA based computers form a new class. This class usually contain no
CPU’s or uses the CPUs only as interface to the network environment. This later
class removes the Von Neumann bottle-necks experienced by hybrid systems and
are also energy efficient and scalable to multiple machines.

XD1 is an example of hybrid system and COPACOBANA is a fully FPGA based

Classification of IC’s based on

As we see here, the ASICs (Application Specific Integrated Circuits) are the
Factory programmed chips which have a hardwired logic and are generally used
for a specific purpose like, the mobile phone ICs. Standard circuits are the widely
available semiconductor IC’s that only provide standard functions, they are not
standalone systems but they need other standard IC’s to be supplemented with to
form the logic circuits. However the most versatile class is the semi-custom IC
class. These class of IC’s can be reprogrammed as needed by the user. The mask
programmed classes of IC’s are generally custom programmed by the
manufacturers by mask-programming. Field programmable devices are what we
mean by reconfigurable devices. There have been different kinds of reconfigurable
devices like Programmable ROMs, Programmable Logic Array, Programmable
Array Logic, and Complex Programmable Logic Device. The latest inclusion in the
list is the FPGA systems. We will be mainly concentrating on FPGA in our
discussions of reconfigurable computing as they are hailed the face of future
computing due to their revolutionizing architecture and the way we look at
reconfigurable devices.

Field Programmable Gate Arrays

FPGA’s is composed of Logic cells and separate Input/output blocks. Each logic
cell can implement a function which is described by programming of the cell. The
interconnections of the cells are also programmable. Programming of the cell
classifies the FPGA into two types:
(i) Anti-fuses, i.e., high current has to be applied to a path to enable it
(ii) RAM, in this each logic block consists of a Lookup table, a flip-flop and is
interconnected with programmable routing pathways.

Beauty of the system is, we no longer need to handle complex methodologies like
masking to custom program the device. The code to be implemented is not simply
stored in the memory as a sequential set of instructions, rather the FPGA loads a
new circuit to adapt the hardware to the program logic at runtime.

Programming & Development of the

FPGA system
FPGA programming is composed of 4 steps:

(i) Schematic
(ii) Partition
(iv) Routing
(v) Configuration bit-string

Schematic step involves designing or outlining the Logical task/ algorithm using a
graphical editor that often ships with the FPGA package or by coding using a
standard Hardware Definition Language (HDL). The HDL resembles normal
programming languages but the algorithm is expressed in terms of logic gates.
Placement of the logic blocks are determined followed by the programming of the
Logic block interconnections or routing. The configuration bit-string is a set of
parameters available in each logic block that defines the response behavior of the

The FPGA development cycle has four stages:

(i) Design
(ii) Simulate
(iv)Simulate & Implement
Schematic step involves designing of the FPGA to suit user needs. The design is
then simulated using simulation suits. The synthesis step optimizes the design,
creates structural elements and mapping. Finally in the Implementation phase, I/O
pin assignment and routing is performed, the positioning of the logic block on the
FPGA is determined and final program file is generated.

Comparison parameters of the FPGA

based systems

The granularity of the reconfigurable logic is defined as the size of the smallest
functional unit (configurable logic block) that is addressed by the mapping tools.
High granularity, which can also be known as fine-grained, often implies a greater
flexibility when implementing algorithms into the hardware. However, there is a
penalty associated with this in terms of increased power, area and delay due to
greater quantity of routing required per computation.

Coarse-grained low-granular architectures are intended for the implementation for

algorithms needing word-width data paths. As their functional blocks are
optimized for large computations and typically comprise word wide arithmetic
logic units (ALU), they will perform these computations more quickly and with
more power efficiency than a set of interconnected smaller functional units; this is
due to the connecting wires being shorter, resulting in less wire capacitance and
hence faster and lower power designs. A potential undesirable consequence of
having larger computational blocks is that when the size of operands may not
match the algorithm an inefficient utilization of resources can result. These have
increased performance in terms of power, area, throughput than their more generic
finer grained FPGA cousins at the cost of flexibility.

Rate of reconfiguration

Configuration of these reconfigurable systems can happen at deployment time,

between execution phases or during execution. In a typical reconfigurable system,
a bit stream is used to program the device at deployment time. Fine grained
systems by their own nature require greater configuration time than more coarse-
grained architectures due to more elements needing to be addressed and
programmed. Therefore more coarse-grained architectures gain from potential
lower energy requirements, as less information is transferred and utilized.
Intuitively, the slower the rate of reconfiguration the smaller the energy
consumption as the associated energy cost of reconfiguration are amortized over a
longer period of time. Partial re-configuration aims to allow part of the device to
be reprogrammed while another part is still performing active computation. Partial
re-configuration allows smaller reconfigurable bit streams thus not wasting energy
on transmitting redundant information in the bit stream. Compression of the bit
stream is possible but careful analysis is to be carried out to ensure that the energy
saved by using smaller bit streams is not outweighed by the computation needed to
decompress the data.


The flexibility in reconfigurable devices mainly comes from their routing

interconnect. One style of interconnect made popular by FPGAs vendors, Xilinx
and Altera are the island style layout, where blocks are arranged in an array with
vertical and horizontal routing. A layout with inadequate routing may suffer from
poor flexibility and resource utilization, therefore providing limited performance.
If too much interconnect is provided this requires more transistors than necessary
and thus more silicon area, longer wires and more power consumption.

Advantages of FPGA

Advantage over other Field Programmable devices (like:

PLD, PLA etc.):

• Enhanced flexibility
• Reduced board space, power and cost
• Increased performance

Advantage over the ASIC devices:

• Re-programmibility (on the fly)

• Off-the shelf availability
• Zero Non-recurring engineering cost
• Reduced time to market
• Ease of use

Features of Current FPGA and

what awaits Next
For complex FPGA’s, prices can vary from some hundreds to more than thousand.
However the prices of FPGA’s are depricating at the rate of ten to thousand dollars
per year. According to a survey in USA, FPGA cores with 1 lakh gates can be
available in 10 to 15 $ within 2 to 3 years.

FPGA chips with about 8 million gates are already available today, but this is
expected to reach 50 million/chip in 2 to 3 years.

Modern FPGA’s have a power consumption betweeb 10 W to 200 mW/ MHz. Many
of the chips have I/O pins in the range of thousands. Frequency of an internal
processor is 25 to 150 MHz for a chip complexity of 300 gates.