HOW INTERRUPTS WORK

INTRODUCTION

I n the course of normal operations, the various I/O devices attached to a PC, such as the
keyboard and disk drives, require servicing from the system’s microprocessor. Although
I/O devices may be treated like memory locations, there is one big difference between the
two: I/O devices generally have the capability to interrupt the microprocessor while it is exe-
cuting a program. The I/O device does this by issuing an Interrupt (INT) or Interrupt Re-
quest (INTR or IRQ) input signal to the microprocessor.

INTERRUPTS
If the microprocessor is responding to INT signals and a peripheral device issues an interrupt
request on an IRQ line, the microprocessor will finish executing its current instruction and
issue an Interrupt Acknowledge (INTA) signal on the control bus. The microprocessor
suspends its normal operation and stores the contents of its internal registers in a special stor-
age area referred to as the stack.

The interrupting device (or an interrupt controller) responds by sending the starting address
of a special program called the interrupt service routine to the microprocessor. The micro-
processor uses the interrupt service routine to service the interrupting device. After the mi-
croprocessor finishes servicing the interrupting device, the contents of the stack are restored
to their original locations, and the microprocessor returns to the original program at the point
where the interrupt occurred.

Because more than one peripheral device might require the attention of the microprocessor at
any given time, all computer systems have methods of handling multiple interrupts in an or-
derly fashion. The simplest method calls for the microprocessor, or the interrupt controller,
to have multiple interrupt inputs that have a fixed priority of service. In this manner, if two in-
terrupt signals occur at the same instant, the interrupt that has the highest priority is serviced
first.

Actually, there are two varieties of interrupts used in microcomputers:

· Maskable interrupts (MI)—which can be ignored under certain conditions

· Non-maskable interrupts (NMI)—which it must always respond to

HOW INTERRUPTS WORK 1

 Most microprocessors have an output line called the Interrupt Enable (INTE) that it uses to
inform peripheral devices whether it can be interrupted. The logic level present on this line
determines whether the microprocessor will respond to an INT or IRQ input signal. The con-
dition of the INTE line can usually be controlled by software, which means the program can
determine whether the interrupt operation will be activated. Non-maskable interrupt inputs,
on the other hand, are signals that cannot be ignored by the microprocessor and, therefore, al-
ways cause an interrupt to occur regardless of the status of the INTE line.

A programmable interrupt controller IC and its relationship to the system’s microprocessor

is illustrated in Figure 1. The interrupt controller chip in the figure accepts prioritized IRQ
signals from up to eight peripheral devices on IRQ lines 0 through 7. When one of the periph-
erals desires to communicate with the microprocessor, it sends an IRQ to the interrupt con-
troller. The controller responds by sending an INT signal to the microprocessor. If two
interrupt requests are received at the same instance, the interrupt controller accepts the one
that has the higher priority and acts on it first. The priority order is highest for the device con-
nected to the IRQ-0 line and descends in order, with the IRQ-7 input given the lowest prior-
ity.

Figure 1:
Programmable Interrupt

Interrupt Circuitry
In the course of normal operations, the various I/O devices attached to the Turbo-PC—such
as the keyboard and disk drives—require servicing from the system’s microprocessor. The
Turbo-PC is an interrupt-driven system and employs the interrupt controller subsystem of
the M1523 to ensure quick, smooth performance from the system. Its interrupt subsystem
provides 14, independently programmable, edge-triggered, or level-triggered interrupt
channels.

HOW INTERRUPTS WORK 2

The M1523 provides two, 8-line interrupt controllers (INTC1 and INTC2), each of which is
equivalent to the 8259 PIC (Programmable Interrupt Controller) used in the original PC’s,
XT’s, and AT’s. These interrupt controllers are internally cascaded together to provide the
16 interrupt channels necessary for AT-compatibility. Like those discrete 8259’s used in the
original AT, the M1523’s controllers must be programmed to operate in cascade mode.
INTC1 is located at hex addresses 020 and 021 while INTC2 is located at 0A0 and 0A1.

Figure 2 shows the internal structure of an 8259A Interrupt Controller. It can handle 8
active-high, prioritized input signals on interrupt request lines IRQ-0 through IRQ-7. IRQ-0
receives the highest priority while IRQ-7 receives the lowest priority. Interrupt signals on
these lines are handled by the Interrupt Request Register (IRR) which stores all of the in-
terrupt levels requesting service, and the In-Service Register (ISR) which stores the priority
of all the interrupt levels currently being serviced.

Figure 2: Internal Structure of an 8259A Interrupt Controller IC

HOW INTERRUPTS WORK 3

 The priority resolver circuit evaluates the priorities of the bits in the IRR and then strobes
them into the ISR. Software may be used to inhibit (mask) any of the IRQ levels by writing a
mask-bit into the Interrupt Mask Register (IMR) for the desired interrupt levels. Masking
a given level of interrupt does not affect interrupt levels with lower priorities than the one
which was masked.

The interrupt controller’s Control Block contains two registers which oversee the operation
of the controller. The system writes control information into the Initialization Command
Word (ICW) and Operation Command Word (OCW) registers. Conversely, the system
can read the contents of the IRR and ISR registers.

Each of the M1523’s interrupt controllers contain 8259-compatible IRR, ISR, and IMR reg-
isters along with a priority resolver. The priority resolver in the interrupt controller is used
to determine the highest priority of all active IRQ inputs, even if multiple interrupts are acti-
vated simultaneously.

Of the 16 interrupt channels (IRQ-0 through IRQ-15) generated, five are used inside the
M1523, and therefore, do not have an external IRQ input pin. The other thirteen IRQ inputs
are available to the system for user definable interrupt functions that meet specific require-
ments of different user’s systems. Each IRQ input is assigned a priority level. IRQ-0 is the
highest and IRQ-15 is the lowest. The internally connected channels are:

Channel-0 (IRQ-0) - Timer/Counter interrupt

Channel-1 (IRQ-1) - Keyboard shift register full interrupt
Channel-2 (IRQ-2) - INTC2 cascaded to INTC1
Channel-8 (IRQ-8) - Real-Time Clock interrupt
Channel-13 (IRQ-13) - FPU-Error interrupt

Table 1 shows the designations for the various interrupt levels in the system.

Table 1: Designations INTERRUPT DESCRIPTION INTERRUPT DESCRIPTION

for the PC-compatible
Interrupt Levels NMI I/O CHANNEL CHECK OR
PARITY CHECK ERROR

INTC1 INTC2

IRQ0 MINUTE ALARM IRQ8 REAL TIME CLOCK

IRQ1 KEYBOARD BUFFER FULL IRQ9 CASCADE TO INTC1

IRQ2 CASCADE FROM INTC2 IR110 SPARE

IRQ3 SERIAL PORT 2 IRQ11 SPARE

IRQ4 SERIAL PORT 1 IRQ12 SPARE

IRQ5 PARALLEL PORT 2 IRQ13 COPROCESSOR

IRQ6 FDD CONTROLLER IRQ14 PRIMARY IDE CTRL

IRQ7 PARALLEL PORT 1 IRQ15 SECONDARY IDE CTRL

HOW INTERRUPTS WORK 4

The cascaded interrupt controller contains a cascade buffer/comparator, which evaluates the
multiple interrupt requests from the slave controller (INTC 2) that are channeled through the
master controller’s (INTC 1) IRQ2 input. Therefore, the interrupts funneled through the
IRQ2 input are all assigned a priority level equal to IRQ2. The comparator evaluates the
IRQ2 inquiries in a nested fashion between IRQ1 and IRQ3.

During an Interrupt Acknowledge cycle, the master interrupt controller writes a code word
into the slave controller. This code word is compared to three ID codes that have been written
into the slave controller. If the code word matches one of the previous codes, the slave con-
troller will issue an interrupt vector.

The Turbo-PC’s interrupt circuitry is illustrated in Figure 3. Its operation is as follows:

Figure 3: Turbo-PC Interrupt Circuitry

1. When one or more of the M1523’s IRQ inputs become active, the
selected interrupt controller sets its corresponding IRR bits.
2. The priority resolver evaluates the priority of the IRQ(s) received,
based on the conditions of the IRR, IMR, and ISR registers and asserts an
INTR signal to the microprocessor.
3. When the microprocessor accepts the interruption, it enters into INTA
cycles. These cycles produce the necessary signals (M/IO, D/C, and W/R
= 0) to cause the M1521’s internal bus controller to issue a coded INTA
signal (CBE0-CBE3=0000) to the M1523. This create the proper bus
conditions for data movement from the M1523’s Interrupt Controller,
through the M1521, and to the microprocessor.

HOW INTERRUPTS WORK 5

 4. During the first INTA cycle, the INTC’s highest priority ISR bit is set
and the corresponding IRR bit is reset. During this time, the internal
cascade address is generated but, the M1523’s data bus pins remain in a
high-impedance state. The microprocessor automatically inserts four bus-
idle states between the two INTA cycles. The M1523’s wait-state logic
automatically generates the required number of wait states for internal
delays.
5. Each I/O system must have a special program called an interrupt
service routine. This program is specific to that system’s function and
operational needs. After the controller informs the microprocessor that an
interrupt has occurred, it must produce an address to point the
microprocessor to the starting address of the service routine that
corresponds to the level of interrupt being serviced. This pointing address
(vector address) is located in portion of RAM memory called the vector
table. These addresses are physically located in the lowest 1 kB (0-3FF)
of RAM memory in the system and contain the starting addresses of the
various service routines. Table 2 lists the interrupt vectors used in the
Turbo-PC along with their functions.
These interrupt vectors can also be used by the programmer to execute software
interrupts in the system. This allows the program to take over and directly con-
trol I/O devices.
During the microprocessor’s second INTA cycle, the interrupt controller places
an 8-bit interrupt vector address (nn) on the data bus. The nn value corre-
sponds to the priority of the interrupt being serviced. This interrupt controller
converts the interrupt number into an absolute memory address which equals
4(nn).
The microprocessor pushes the contents of its internal registers on a stack and
latches the vector address bits during this time.
6. The microprocessor jumps to the address specified by the vector byte
and loads a 4-byte address. This address represents the beginning address
of the service routine for the interrupting device. The Pentium services
the interrupting device until an End Of Interrupt (EOI) instruction is
encountered in the routine.
This will cause the microprocessor to issue a specific EOI software instruction to
the interrupt controller. A specific EOI will cause the bit in the ISR register that
corresponds to the interrupt being serviced, to be cleared. The end of the inter-
rupt routine may also be marked by a nonspecific EOI command. This type of
EOI simply resets the highest priority ISR bit.
7. The EOI command from the CPU will cause the interrupt controller’s
ISR bit to be cleared at the end of the second INTA cycle. This marks the
end of the service routine. The microprocessor retrieves the contents of
its internal registers from the stack and resumes its normal operation at
the point where it left off when the interrupt was accepted.

HOW INTERRUPTS WORK 6

INTERRUPT FUNCTION Table 2:
0 Divide by zero Turbo-PC Interrupt
1 Single step Vectors and Their
2 Non-maskable interrupt (NMI) Functions
3 Break point instruction
4 Overflow
5 Print screen
6, 7 Reserved
8 Time or day hardware interrupt (18.2/sec)
9 Keyboard hardware interrupt
A Reserved
B, C Serial communications hardware interrupt
D Fixed-disk hardware interrupt
E Disk hardware interrupt
F Printer hardware interrupt
10 Video I/O call
11 Equipment check call
12 Memory check call
13 Disk I/O call
14 RS232 I/O call
15 (not used)
16 Keyboard I/O call
17 Printer I/O call
18 ROM basic entry code
19 Bootstrap loader
1A Time of day call
1B Get control on keyboard break
1C Get control on timer interrupt
1D Pointer to video initialization table
1E Pointer to disk parameter table
1F Pointer to graphics character generator
20 DOS program terminate
21 DOS function call
22 DOS terminate address
23 DOS CTRL-BRK exit address
24 DOS fatal error vector
25 DOS absolute disk read
26 DOS absolute disk write
27 DOS terminate, fix in storage
28 – 3F Reserved for DOS
40 – 5F Reserved
60 – 67 Reserved for user software interrupts
68 – 7F (not used)
80 – 85 Reserved by BASIC
86 – F0 Used by BASIC interpreter while running
F1 – FF (not used)

HOW INTERRUPTS WORK 7

 In addition, to the ISA-compatible interrupt functions, the M1523 offers up to eight, steer-
able, level-to-edge triggered PCI interrupt routes. These interrupts are provided for PCI
plug-and-play devices and are available at each PCI slot. The M1523 indexed registers 48h-
4Bh are used to establish the PCI-to-ISA IRQ routing tables for these interrupts. The lower
nibble of register 48h is used to route PCI interrupt INT1 to an ISA IRQ level. Similarly, the
upper nibble of the register is used to route INT2 to an IRQ level. Likewise, the nibbles of
49h deal with INT3 and INT4, while 4Ah handles INT5 and INT6, and 4Bh handles INT7
and INT8. Normally, these routes are established by the BIOS PnP Configuration process
during bootup.

NMI Circuitry
The Turbo-PC’s Non-Maskable Interrupt (NMI) function is performed by the logic cir-
cuitry illustrated in Figure 4. On the system board, there are two conditions that will cause an
NMI signal to be sent to the microprocessor. The first condition occurs when an active IO
Channel Check (IOCHCK) input is received from an options adapter card located in one of
the board’s ISA expansion slots.

ISA
SLOTS U18 U14
IOCHECK 70H 1523 µP

SERR
7 NMI
U12 LOGIC
1521 61H
EN IOCHCK NMI
3 NMI
PARITY SERR
ERROR
Figure 4: 6
IOCHCK

NMI Logic 7
SERR
Circuitry

The system’s BIOS enables this signal during initialization by writing a logic 0 into bit-3
(ENIOCK) of the M1523’s NMI Status and Control Port register at hex address 61.
When an ISA device produces an active IOCHCK signal, the M1523 responds by generating
an NMI signal that is applied directly to the microprocessor.

The other event that will cause an NMI signal to be generated is the occurrence of a Parity
Check (PCK) error in the system’s DRAM memory. The BIOS enables the parity check sig-
nal by writing a logic 0 into bit-7 of the NMI Enable register at hex address 70, during the
system’s initialization. When the M1521 detects a parity error, it signals the M1523 by acti-
vating its System Error (SERR) line. In turn, the M1523 issues the NMI signal to the micro-
processor.

HOW INTERRUPTS WORK 8

Port-B Functions
The Port-B function of previous of PC-compatible generations are performed in the NMI
Status and Control Register in the ALI chip set. This register, described in Table 3, is lo-
cated in the M1523 ISA bridge and can be accessed by placing an address of hex 61 on the ad-
dress bus. The register can be enabled for both Read and Write operations at this address.

Table 3:
NMI Status and
Control Register in
the ALI Chip Set

The Port-B functions primarily include enabling different system board options and report-
ing the status of key conditions. The enabling options include: the system’s Timer/Counter-2
output, system board error reporting, and IOCHCK/NMI function. The status of the
Timer/Counter-2 output, IOCHCK, and SERR lines can be read at this port.

The system’s speaker data signal is routed through bit-1 of the register, while bit-4 is toggled
each time a DRAM Refresh operation is performed.

HOW INTERRUPTS WORK 9