Beruflich Dokumente
Kultur Dokumente
Adders
2
4-‐bit
Ripple
Carry
Adder
A3 B3 A2 B2 A1 B1 A0 B0
C3
C2
C1
C4
C0
R3
R2
R1
R0
Carry
ripples
from
lsb
to
msb
3
ObservaAons
4
Reasoning
About
Carries
5
Ai
Bi
Carry
Logic
Cin
gi
pi
Ri
Invent
two
new
terms:
propagator,
generator
• g
==
1
means
this
bit
generates
carry,
irrespecAve
of
Cin
– g
=
AB
• p
==
1
means
this
bit
propagates
Cin
to
Cout,
but
doesn’t
generate
carry
– p
=
A
xor
B
Performance?
• p
and
g
generated
in
1
gate
delay
a`er
A
and
B
arrive
• R
is
2
gate
delay
a`er
Cin
arrives
6
Carry
Look-‐Ahead
Logic
A3 B3 A2 B2 A1 B1 A0 B0
g p g p g p g p
C3
C2
C1
C0
CLL
inputs:
p,g
from
all
4
bits,
C0
CLL
outputs:
all
carry
bits
(using
just
2
gate
delays)
C1
=
g0
+
p0C0
C2
=
g1
+
p1C1
=
g1
+
p1(g0
+
p0C0)
=
g1
+
p1g0
+
p1p0C0
C3
=
g2
+
p2C2
=
g2
+
p2g1
+
p2p1g0
+
p2p1p0C0
C4
=
g3
+
p3C3
=
g3
+
p3g2
+
p3p2g1
+
p3p2p1g0
+
p3p2p1p0C0
7
4-‐bit
CLA
A3 B3 A2 B2 A1 B1 A0 B0
g p g p g p g p
R3 R2 R1 R0
8
Space
Time
Tradeoff
Space Time
4 Bit Look-‐Ahead 4 x 11 + 14 = 58 gates (5 input) 5 gate delays
16 Bit Look-‐Ahead 16 x 11 + 152 = 328 gates (17 input) 5 gate delays
64
x
2
=
128
gate
64
Bit
Ripple
64
x
9
=
576
gates
(4
input)
delays
64 Bit Look-‐Ahead 64 x 11 + 2144 = 2848 gates (65 input) 5 gate delays
9
Carry-‐Skip
Adders
Only
compute
some
fast
carry
signals
C16 C0
10
Carry-‐Skip
Adders
Carry-‐Skip
Adder
Only
compute
some
fast
carry
signals
compute C8
C16 C0
11
Hybrid
Adders
Hybrid
Approach
A15..8
B15..8
A11..8
B11..8
A7..4
B7..4
A3..0
B3..0
12
Hierarchical
Hierarchical
Approach
A15..8
B15..8
A11..8
B11..8
A7..4
B7..4
A3..0
B3..0
4-bit 4-bit 4-bit 4-bit
g
p g
p g
p g
p
13
Example
Programs
14
ArithmeAc
and
Logic
R-‐type instrucAon
Prog.
inst
Reg.
ALU
Mem
File
+4
5
5
5
PC
control
15
Shi`
R-‐type instrucAon
Prog.
inst
Reg.
ALU
Mem
File
+4
5
5
5
PC
control
shamt
16
Immediates
I-‐type instrucAon
Prog.
inst
Reg.
ALU
Mem
File
+4
5
5
5
PC
control
control
imm
extend
shamt
17
Immediates
I-‐type InstrucAon
Prog.
inst
Reg.
ALU
Mem
File
+4
5
5
5
PC
control
control
16
imm
extend
shamt
18