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Abstract— Small robots can be beneficial to important applica- software, requires a lot of CPU time and a real-time operating
tions such as civilian search and rescue and military surveillance, system. By moving control to hardware, the robot can dedicate
but their limited resources constrain their functionality and the CPU to other tasks. However, we want both options
performance. To address this, a reconfigurable technique based
on field-programmable gate arrays (FPGAs) may be applied, available, as a software implementation is more appealing
which has the potential for greater functionality and higher when the robot is not engaged in highly articulated movement,
performance, but with smaller volume and lower power dis- thus the need to implement in reconfigurable hardware.
sipation. This project investigates an FPGA-based PID motion
control system for small, self-adaptive systems. For one channel
control, parallel and serial architectures for the PID control
Wireless
algorithm are designed and implemented. Based on these one- Force/Torque Com.
channel designs, four architectures for multiple-channel control Sensor
Host Computer
are proposed and two channel-level serial (CLS) architectures
are designed and implemented. Functional correctness of all the
designs was verified in motor control experiments, and area,
Motors Power Motor Digital
speed, and power consumption were analyzed. The tradeoffs Encoders Amplifier Closed -loop Controller
between the different designs are discussed in terms of area, MotorSensor
Control AI
power consumption, and execution time with respect to number Interface
computation
of channels, sampling rate, and control clock frequency. The Force Sensor
CCD Interface Wireless
data gathered in this paper will be leveraged in future work to Camera Force
Com.
Vision
dynamically adapt the robot at run time. Interface
Processing
Tilt Image
Sensor Processing
I. I NTRODUCTION Adaptation
Vib Signal
Processing
Because small robots have greater access to confined areas
and are cheaper to deploy in large numbers, they are bene-
ficial for many tasks such as urban search and rescue, mil-
itary surveillance, and planetary exploration. But their small
size constrains resources such as volume, payload capacity,
and power. Consequently, computational capacity, mechanical Fig. 1. CRAWLER functional architecture. The FPGA-based system will
abilities such as locomotion and manipulation, and sensor be an on-board, power efficient implementation of all functionality within the
modalities are also constrained. For a small robot to be used dashed line. Currently, it is implemented on 2 tethered PCs.
in a variety of applications, versatile functionality is required.
Not all functions are required for all applications and not all This research is a comparative study of FPGA-based PID
functions are required at all times. Thus, if limited resources control designs, relative to speed, area, and power consump-
can be reconfigured to tailor the robot to a specific application, tion. It is important to understand the trade-offs of the various
it may need fewer resources for equal or more functionality. implementations to best utilize resources during reconfigura-
Research has been conducted in the area of robot reconfig- bility. We expect that the study methodologies used in this
urability in mechanism, in software, but to a much lesser extent project can be extended to study other functions.
in hardware, specifically using the relatively new technology Research was conducted on CRAWLER (a.k.a. Termina-
of field-programmable gate arrays (FPGAs). In this study, we torBot) [1], which has dual-use arms for both manipulation
researched the design of a digital control system implemented and locomotion. The robot requires both a digital and analog
in reconfigurable hardware. Specifically, we looked at closed- system to implement functions such as closed-loop motion
loop proportional-integral-derivative (PID) control for a robot control, computer vision, sensing, and artificial intelligence, as
with high degrees-of-freedom, which when implemented in shown in Figure 1. In the current prototype, these functions
0-7803-9177-2/05/$20.00/©2005 IEEE 70
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are implemented on two desktop computers tethered to the
+ e (t) u (t)
robot. The FPGA-based digital control system will be a power- Pd Closed-Loop Power Controlled
P
Controller Amplifier Object
-
efficient implementation of all components (within the dashed
line of Figure 1) and embedded in the robot body.
Sensor
II. R ELATED W ORK
The benefit of software-based computation over hardware- Fig. 2. Closed-loop control system. The output of the controller, u(t), is an
based computation is the ability to reconfigure on-the-fly. This attempt to reconcile the desired value Pd and the measured value P .
Run Time Reconfiguration (RTR) of computation is the basis
for the flexibility and rapid growth of software-based solutions.
But software requires a hardware target on which to run. conducted a simulation-based study of it [12]. Chen et al.
FPGA chips can be reconfigured, too, but most only permit implemented a complete wheelchair controller on an FPGA
Compile Time Reconfiguration (CTR). However, a new breed with parallel PID design [13]. Samet et al. designed three PID
of FPGA chips, such as XC6000 and Virtex-II Pro, allow Run architectures for FPGA implementation - parallel, serial and
Time Reconfiguration (RTR) of logic [2]. Furthermore, some mixed [14]. Speed and area are the tradeoffs on the three
of these new FPGA chips, such as the Virtex-II Pro, have designs. Simulation results show the correct functions and
embedded microprocessor units (MPU), making it possible fast response time. All these prior works are for one channel
to build power-efficient and highly reconfigurable system-on- control and the important issue of FPGAs, namely power
chip designs. These systems combine reconfigurable software, consumption, for closed-loop control was not addressed.
a power-efficient hardware target on which the software can In this work, different designs for the closed-loop PID
run, and reconfigurable hardware all on a single chip. control algorithm are implemented on an FPGA for both one
“HW/SW co-design” usually refers to methodologies that and multiple channels. These designs are evaluated in terms of
permit the hardware and software to be developed at the same area, power, and speed. In this paper, first the PID algorithm
time - splitting some functions to be implemented in hardware is introduced, then, parallel and serial one-channel designs are
for additional speed, while others are implemented in software described in detail in Section IV. Multiple-channel designs
to free up logic resources. This is normally done offline. based on the one-channel designs are presented in Section V.
The combination of HW/SW co-design techniques with online Section VI introduces the test platform and methodologies,
RTR capability at both the hardware and software levels can then presents the results. A discussion of those results follows
optimally assign functions between the FPGA and software in Section VII.
dynamically [3].
In order to achieve this level of RTR, the system specifica- III. C LOSED - LOOP C ONTROL S YSTEM
tion must be partitioned into temporal exclusive segments, a A closed-loop control system is shown in Figure 2, which
process known as temporal partitioning. A challenge for RTR is used to control a device such as a servo motor. P and Pd
is to find an execution order of a set of sub-tasks that meet correspond to the controlled variable (e.g. rotational position)
system design goals, a process known as context scheduling. and its desired value, which is provided at a higher control
Several approaches can be found in the literature describing level. The goal is to eliminate the error between P and Pd .
these problems (e.g. [11]). All these approaches depend on The value of P is measured by the sensor, which is compared
performance and resource requirements of the requisite sub- with Pd to generate the error e(t). The output to the controlled
tasks to make an optimal tradeoff [3]. This paper investigates device, u(t), from the closed-loop controller is a function of
the power, area, and speed characteristics of particular PID e(t). Typically, this is a weak signal that requires amplification.
control implementations so that they may be used in future
work on hardware/software run time reconfiguration of a SoC A. PID Control Algorithm
robotic controller.
In this project, the PID algorithm is applied for closed-loop
FPGA-based SoC designs have been widely applied in
control. This is the most commonly used control law and has
digital system applications and RTR research has been ad-
been demonstrated to be effective for DC servo motor control.
dressed by many researchers. Elbirt et al. explored FPGA
The PID controller is described in a differential equation
implementation and performance evaluation for the AES algo-
as:
rithm [4]. Weiss et al. analyzed different RTR methods on the 1 t de(t)
XC6000 architecture [2]. Shirazi described a framework and u(t) = Kp e(t) + e(t)dt + Td (1)
Ti 0 dt
tools for RTR [5]. Noguera and Badia proposed a HW/SW
co-design algorithm for dynamic reconfiguration [3]. FPGA where Kp is the proportional gain, Ti is the integral time
power modeling and power-efficient design have also been constant and Td is the derivative time constant.
studied by various researchers [6]–[10]. For a small sample interval T , this equation can be turned
Closed-loop control algorithms, in particular, have been into a difference equation by discretization [16]. A difference
studied and implemented. Li et al. implemented a parallel equation can be implemented by a digital system, either in
PID algorithm with fuzzy gain conditioner on an FPGA and hardware or software. The derivative term is simply replaced
71
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MPL0
ADD1
T n
T
ADD0 MPL1 32
+
S1
UpBoun Bounder0
E
n K2 32 u(n-1) G
j=0 OvFl3
where Ki = Kp T /Ti is the integral coefficient, and Kd = Fig. 3. Parallel design of incremental PID algorithm.
Kp Td /T is the derivative coefficient. To compute the sum, all
past errors, e(0)..e(n), have to be stored. This algorithm is
called the “position algorithm” [16].
decomposed into its basic arithmetic operations:
An alternative recursive algorithm is characterized by the
calculation of the control output, u(n), based on u(n − 1) and e(n) = Pd + (−P )
the correction term ∆u(n). To derive the recursive algorithm, p0 = K0 ∗ e(n)
first calculate u(n − 1) based on Eq. (3): p1 = K1 ∗ e(n − 1)
p2 = K2 ∗ e(n − 2) (7)
n−1
s1 = p0 + p1
u(n−1) = Kp e(n−1)+Ki e(j)+Kd (e(n−1)−e(n−2))
s2 = p2 + u(n − 1)
j=0
(4) u(n) = s1 + s2
Then calculate the correction term as: For a parallel design, each basic operation has its own
∆u(n) = u(n) − u(n − 1) arithmetic unit – either an adder or multiplier. It is mainly
(5)
= K0 e(n) + K1 e(n − 1) + K2 e(n − 2) combinational logic. For serial design, which is composed of
sequential logic, all operations share only one adder and one
where multiplier.
K0 = Kp + Ki + Kd A. Parallel Design
K1 = −Kp − 2Kd
K2 = Kd Figure 3 shows our parallel design of the PID incremental
algorithm. The design requires 4 adders and 3 multipliers,
Equation (5) is called the “incremental algorithm”. The current corresponding to the basic operations shown in 7. All bold
control output is calculated as: signals are I/O ports, while others are internal signals.
The clock signal clk is used to control sampling frequency.
u(n) = u(n − 1) + ∆u(n) EncdCnt, the encoder counter value, represents the current
= u(n − 1) + K0 e(n) + K1 e(n − 1) + K2 e(n − 2) position P . The negation of P , P neg, is generated by bit-wise
(6)
complementing and adding 1. At the rising edge of control,
In the software implementation, the incremental algorithm
signal e(n) of the last cycle is latched at register REG1, thus
(Eq. 6) can avoid accumulation of all past errors e(n) and can
becomes e(n − 1) of this cycle. In the same manner, e(n − 2)
realize smooth switching from manual to automatic operation,
and u(n − 1) are recorded at REG3 and REG4 by latching
compared with the position algorithm [16]. More advantages
e(n − 1) and u(n) respectively. The registers can be set to
will be shown for the hardware implementation in Section IV.
initial values of 0 by asserting the reset signal, Reset. As
In PID control, increasing the proportional gain Kp can
long as the desired position Pd is also initialized to 0 when
increase system response speed, and it can decrease steady-
the system is reset, the control output is 0, which can keep
state error but not eliminate it completely. Additionally, the
the controlled device (i.e. the motor, in this system) static.
performance of the closed-loop system becomes more oscilla-
The computed control output u(n) may exceed the range
tory and takes longer to settle down after being disturbed as the
that the controlled device can bear. Bounder, as shown in
gain is increased. To avoid these difficulties, integral control
Fig. 3, is a value limitation logic that keeps the output in the
Ki and derivative control Kd can eliminate steady-state error
user defined range of U pBound and LowBound.
and improve system stability ( [17], respectively).
Control can become unsteady and fail in the event of an
overflow in any of the adders. OvF lx is asserted in the case of
IV. O NE - CHANNEL D ESIGNS
an overflow in adder x. All overflow signals are ORed together
First, we constructed a one-channel design based on the PID to generate the OvF l signal. When asserted, this signal can
control algorithm. The PID incremental algorithm (Eq. 6) is be used to shut down the controlled device.
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REGout0
MUX0 R
REG7
24 Bounder0 E Output_out(0)
R u(n)
UpBoun G 16
Pd 0 E d MUX0 REG7 loadout(0)
24 u(n) Bounder0
R UpBoun Clk
G MUX2 Pd
load(7) 16
0 E d REGout1
REG0 G MUX2
Bounder load(7) Output R
32 R Clk Output REG0 16
P0 Bounder
E Output_out(1)
Product E K0 0 32 16 16 32 R Clk G 16
1 P0 16 loadout(1)
G Product E 1 K0 0 32 16
load(0) MUX_OUT0 16 LowBoun G Clk .
MUX load(0) MUX_OUT0 16 LowBoun
Clk 4_1 d MUX .
Clk 4_1 d
MUX MUX .
REG2 32-bit
32 K1
3_1 REG2 32-bit
32 K1
3_1 .
1 MUX_OUT2 1 MUX_OUT2
32 R P2 32 R P2 16-bit .
2 16-bit 2 16
E 16 16 Product E 16
.
Product G
G load(2) ADD0 .
load(2) ADD0 MPL0 REGout15
MPL0 MUX4 Clk K2 2
Clk R
K2 2
u(n-1) 3 16 E Output_out(15)
EncdCnt(0) 0 Sum
u(n) 3 Sum
16 EncdCnt(1) 1 32 2
+ 2
* Product loadout(15)
G 16
32 2
+ 2
* Product EncdCnt(2) 2 Sel0
32
Sel2 32 Clk
32 . REG8 REG4
Sel0 Sel2 32 . MUX EncdCnt MUX1
16
MUX3
R P P_neg OvFl R e(n)
. 16_1 24
REG8
MUX1
REG4
MUX3
E - E
. G G
EncdCnt 24 R P P_neg OvFl 16 R 16-bit load(8) 0 load(4) 0
E - E e(n)
.
Clk
REG9
Clk
Control Unit
G G . REG1 R
load(8) load(4) E REG6 MUX_OUT3 ControlUnit0
0 0 . 32
Clk
REG9
Clk
Control Unit EncdCnt(15) 15 Product
R
E
P1 MUX
3_1
1
32
load(9) G e(n-1)in R e(n-1) MUX
E 1
3_1
load(9:0)
loadout(15:0
load(9:0)
REG1 R G )
loadout(15:0)
REG5 MUX_OUT3 ControlUnit0 load(1) 32-bit MUX_OUT1 Clk load(6) G 16-bit Clk Clk
32 E 4
16 ControlUnitM_srl sel0 Sel0
R P1 MUX 32 R e(n-1) MUX Clk sel1 Sel1
load(9) G load(9:0) load(9:0) CC REG3 Clk
Product E 3_1
1 E
3_1
1 Disable Reset
Rese sel2 Sel2
32 S1 t CC_ sel3 Sel3
G R 2 e(n-2) 2
CC_
Req Ack MAX CC we
load(1) 32-bit MUX_OUT1 Clk load(5) G 16-bit
16 Clk Clk
sel0 Sel0 Sum E
Rst
ControlUnit G
Clk sel1 Sel1 load(3) CC_Rst
REG3 Clk Rese sel2 Sel2 2 2
Flip_Flop0
32 S1 Disable Reset t sel3 Sel3
Clk
CC
we
R 2 REG6 2 Req Ack Sel1 Sel3 Req
E Start
Sum R e(n-2) CC_MAX
Reset
G
load(3) E
Flip_Flop0
Datapath Ack
2
load(6) G 2
Clk
Sel1 Sel3 Req
Clk Start
Reset
Channel Counter
Ack
Datapath MUX_CC REG_CC
Reset
0 1
CC
CC_next R CC
CC_p1
E Addr
G 4
+1 0 load(5)
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MPL0
Power P
K0 Motor
16
*
P0 Amp
e(n)
REGout0
ADD1 Shaft
R u(t)
MUX4 E Output_out(0) Encoder
G 16
ADD0 32 S1 loadout(0)
EncdCnt(0) 0 MPL1
EncdCnt(1) 1
+ ADD3 UpBoun Bounder0
Clk
Pd K1 d
EncdCnt(2) 2
24 16
REGout1 User expansion conectors
. P1 Output R
.
REG8 + REG6 * 32 u(n) 16
E Output_out(1)
MUX EncdCnt
24
R P P_neg 16 R en-1 OvFl1 + Bounder
loadout(1)
G 16
. 16_1
E - E ADD2
32 16 16
. 16-bit load(8) G load(6) G 16 Clk .
. LowBoun
32 .
Clk OvFl0 Clk d
.
e(n-1) in MPL2
+ S2
OvFl3 . Cport
. . PWM Encoder
EncdCnt(15) 15 K2 .
Reset 16 . Logic Counter
P2
OvFl2
4 REG0
en-2R
* REGout15
.
Host Computer
CC R
e(n-2) E REG7 R
un-1R
load(0) G R E Output_out(15)
16
Clk
u(n-1) E
OvFl0
OvFl1 OvFl
REG9
R loadout(15)
G 16
CPLD SDRAM
load(7)
G
E Disable Clk FPGA
Reset OvFl2 G
Spartan II
Clk load(9) Pd
OvFl3
Datapath Clk XC2S150
Clk
CC_Rst
Flip_Flop0 CC_Rst ARM7TDMI
Req CC
we Game Boy microprocessor
Start
Ack
CC_MAX Advanced <S/W PID>
<Trajectory Generator>
Step Response
B. Parallel PID based multiple-channel design 1250
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TABLE I TABLE II
D EVICE RESOURCES UTILIZATION OF DESIGNS . C LOCKS AND EXECUTION TIMES OF DESIGNS .
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TABLE IV
12000
P OWER DISSIPATION OF ONE - CHANNEL SERIAL DESIGN .
10000
number of slices
CLP parallel
8000
CLS parallel
Sampling Control clock Simulation Power (mW) 6000 CLP serial
Freq. (MHz) Freq. (MHz) Time(µs) (Dynamic state) 4000
CLS serial
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500 of channels, CLS serial based design is suggested. CLS serial
450
400 based design has the longest execution times, but the execution
350
time is not a major concern for these designs as long as the
Power (mw)
300
250 Serial number of channels is not so large that the total execution time
200 Parallel
150 exceeds the sampling period.
100
50
In addition, the results show that the dynamic process con-
0
0.0012 0.012 0.12 0.25 0.5 1.25 2.5 6.25 8.3325
sumes more power than the stable state, that higher sampling
Sampling frequency (MHz) frequency and control clock frequency consumes more power
than lower frequency, and that power dissipation increases as
Fig. 10. Power dissipation of one-channel serial and parallel design. the number of channels increases.
R EFERENCES
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