Electrical Engineering 1

Digital Systems
Lecture 10
Sequential circuit design and analysis with T flip flops

1. Introduction
We can use any flip flop to design counter circuits. In the last lecture we saw how to do this with D flip
flops. In this lecture we will repeat the same examples using T flip flops. The design process for T flip
flops is conceptually a little more complicated than for D flip flops, but the circuits that result are
usually simpler.

2 The T Flip Flop

The T flip flop has truth table and circuit symbol as follows:

T Q Clock Q+
0 0 0 T Q
0 1 1
1 0 1 Clock Q
1 1 0

As before, any signal without the + superscript refers to the value just before the clock edge. The +
superscript is used to denote values just after the clock edge. The T input can be regarded as a control
input whose function is:
• T=0 Hold the memorised bit constant
• T=1 Toggle the memorised bit

The truth table can also be drawn like this:

T Clock Q+ Name
0 Q Hold
1 �
Q Toggle

• When T=0, Q+=Q. In other words, the value of Q that will happen just after the clock edge is the
same as the value that Q had just before the clock edge.
• When T=1, Q+ =Q � , in other words, the value of Q that will happen just after the clock edge is the
complement of the value that Q had just before the clock edge

An illustrative waveform for the T flip flop is:

Clock

Hold Toggle Hold Toggle Toggle

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2.1 The T Flip Flop Characteristic Equation
We can derive the characteristic equation of the T flip flop from its truth table:
Q
T 0 1
0 0 1

1 1 0

𝑄𝑄 + = 𝑇𝑇. 𝑄𝑄� + 𝑇𝑇�. 𝑄𝑄

This equation tells us how the value of the memory bit after the clock edge (Q+) is derived from the
value of the memory bit before the clock edge before the clock edge (Q) and the T input before the
clock edge.

2.3 Analysing T flip flop circuits

Consider the following circuit, starting in the state Q0=0, Q1=0. What sequence does it follow?

1 Q0

T0 Q0 T1 Q1

Ck Q Ck Q
0 1

The relevant equations are:

𝑇𝑇0 = 1
𝑇𝑇1 = 𝑄𝑄0

We can work this out by forming table a table of values on successive clock cycles. The values of
����,Q , and ��
Q0 ,Q Q��1 (before the clock edge) give rise to values of T0, T1 (before the clock edge). These
0 1
values of T0, T1 will cause the values after the clock edge Q0+, Q1+ to be a flip (Q+ =Q � ) or a hold
+
(Q =Q) of the value before the clock edge. We can use this information to work out the sequence that
Q0, Q1 will go through.

Cycle Q1 Q0 ����
𝑸𝑸𝟏𝟏 ����
𝑸𝑸𝟎𝟎 T1 T0 Q+1 Q+0
Start 0 0 1 1 0 1 0 1
1 0 1 1 0 1 1 1 0
2 1 0 0 1 0 1 1 1
3 1 1 0 0 1 1 0 0
4 0 0
And repeats forever

This circuit is a 2-bit binary up-counter:

Q1Q0=00→01→10→11→00→01→10→11→ and so on forever
Denary interpretation of output=0→1→2→3→0→1→2→3→ and so on forever
It instructive to compare this circuit (built from T-types) with the circuit analysed earlier (built from D-
types):
2
 1 Q0

T 0 Q0 T 1 Q1 D0 Q 0 D1 Q 1

Ck Q Ck Q1 Ck Q0 Ck Q
1
0

2-bit binary up-counter using T-types 2-bit binary up-counter using D-types

The circuit built from T types requires fewer logic gates. This is usually the case for most common
types of counter, hence the popularity of T-type flip-flops.

3 Designing T flip flop circuits

We now look for a process to design a circuit that will give a required behaviour. For a 2-bit counter
built from T flip flops, this amounts to:

What goes What goes

here to give here to give
the required the required
sequence? sequence?

T0 Q0 T1 Q1

Ck Q Ck Q
0 1

We have to design the logic that goes into the boxes. The inputs to this logic can be the values of Q1,
Q0 (and their complements) before the clock edge. This requires a little more thought than was
necessary when we were using D flip flops. With a D flip flop, the value at the D input was simply
equal to Q+. With the T type we need to think what value T needs to have to give the required
transition. We can do this by drawing up a table that shows the value of Q before the clock edge, the
value of Q+ that we desire after the clock edge, and the value of T that is necessary in order to achieve
this:

Value before clock Desired value after What operation What value of T
edge Q clock edge Q+ will give this? will give this?
0 0 Hold 0
0 1 Toggle 1
1 0 Toggle 1
1 1 Hold 0

This is called the excitation table of the flip flop. It shows what value of input T is needed to cause
(“excite”) the required transition in the memory bit.

3.1 Example: a 2-bit binary down-counter

We will now use T-type to design a binary down-counter that counts through the sequence:

3
 Output=0→3→2→1→0→3→2→1→ and so on forever

Interpreting these denary numbers in binary means that this is what we need to design:

Q1Q0=00→11→10→01→00→11→10→01→ and so on forever

This means that we are designing two pieces of logic, one for T0 and one for T1. This can be done by
drawing up two tables (one for T1, one for T0) that show:
• the values of the inputs (Q0, Q1) to the box before the clock edge
• the value that we want after the clock edge Q+
• the value that we must force T to before the clock edge in order to get the required next value

We draw up our tables:

Value before Required value Input to give us

clock edge after clock edge required next value
Q1 Q0 Q1+ T1
0 0 1 1
0 1 0 0
1 0 0 1
1 1 1 0

Value before Required value Input to give us

clock edge after clock edge required next value
Q1 Q0 Q0+ T0
0 0 1 1
0 1 0 1
1 0 1 1
1 1 0 1

Our task is then to design the logic that takes the values of Q0, Q1 as inputs and produces the required
value of T at the output. This can be done with two K-maps:
Q1 Q1
Q0 0 1 Q0 0 1
0 1 1 0 1 1

1 0 0 1 1 1

𝑇𝑇1 = ���
𝑄𝑄0 𝑇𝑇0 = 1

We see that the desired T is not dependent on Q1 or Q0: it is simply 1 all of the time. Our circuit
solution is:

4
 1 Q0

T0 Q0 T1 Q1

Ck Q Ck Q
0 1

3 A more advanced example: an Up/Down counter

Sometimes it is useful to be able to reverse the direction of a counter under the control of an additional
input. As an example, we will design a 2-bit up-down counter which uses a control signal called
DOWN. When DOWN=0, the device functions as an up-counter. When DOWN=1, the device functions as
a down-counter:

When DOWN=0, the circuit will count up: Q1Q0=00→01→10→11→00→01→10→11…;

(denary interpretation): 0 → 1→ 2 → 3 → 0 → 1→ 2 → 3…;

When DOWN=1 it will count down: Q1Q0=00→11→10→01→00→11→10→01…;

(denary interpretation): 0 → 3→ 2 → 1 → 0 → 3→ 2 → 1…;

This will require 2 flip flops as we require 2-bits to represent the numbers 0,1,2,3. The transition tables
and Karnaugh maps for this device are shown below.

Value before clock Required value Input to give us

edge after clock edge required next value
Down Q1 Q0 Q1+ T1
1 0 0 1 1
1 0 1 0 0
1 1 0 0 1
1 1 1 1 0
0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 0 1

Value before clock Required value Input to give us

edge after clock edge required next value
Down Q1 Q0 Q0+ T0
1 0 0 1 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1
0 0 0 1 1
0 0 1 0 1
0 1 0 1 1
0 1 1 0 1

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 Q1Q0 Q1Q0
00 01 11 10 00 01 11 10
DOWN
DOWN
0 0 1 1 0 0 1 1 1 1

1 1 0 0 1 1 1 1 1 1

T1=DOWN.Q0+DOWN.Q0 T0=1
The equation for T1 is equivalent to an XOR gate:

����0 +DOWN
T1 =DOWN.Q ���������.Q0 =DOWN⊕Q0

This gives us our circuit:

DOWN

1 T0 Q0 T1 Q1

Ck Q Ck Q
0 1

4 Summary
In this lecture we have introduced counters as an example of the design approaches used to build
counters from T-type flip-flops Design proceeds by forming a table of the transitions of the state of the
flip flop outputs that must occur on each clock cycle, then deciding what value the T input should take
at the clock edge in order to give the required output after the clock edge.

Examples
1. The circuit starts with Q0=0, Q1=0. What will be the values of Q0 and Q1 on subsequent clock
cycles?

Q0+Q1 Q0+Q1

T0 Q0 T1 Q1

Ck Q Ck Q
0 1

Cycle Q0 Q1 ����
𝑸𝑸𝟎𝟎 ����
𝑸𝑸𝟏𝟏 T0 T1 Q+0 Q+1
Start 0 0 1 1
1
2
3

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2. Use T flip flops to design a counter follows the count sequence Q1Q0=00→01→11→10→00,
etc…. (This is a 2-bit Gray-code counter)

Value before Required value Input to give us

clock edge after clock edge required next value
Q1 Q0 Q1+ T1
0 0
0 1
1 0
1 1

Value before Required value Input to give us

clock edge after clock edge required next value
Q1 Q0 Q0+ T0
0 0
0 1
1 0
1 1

Q1 Q1
Q0 0 1 Q0 0 1
0 0

1 1

Table for T0 Table for T1

T0 Q0 T1 Q1

Ck Q Ck Q
0 1