Beruflich Dokumente
Kultur Dokumente
Yang Min
(Electronic Engineering Department, College of Mechanical and Electrical Engineering
Shanghai Normal University,
Shanghai China, 201418)
yangmin@shnu.edu.cn
Abstract: Aiming at incommodity of extent hearing aid in the nonlinear area. They divide the range of self-frequency
market, a new design of hearing aid is brought forward in this spectrum into a couple of bands so that they can make up for
paper. First, the system construction is discussed, the difference different audition loss. And most digital devices use low noise,
between which and other hearing aids is it uses FPGA for voice low distortion component so they work better that analog ones.
processing. Second, the application of FPGA and embedded soft But their shapes are too tiny to use conveniently for old people
core Nios II is described, how to utilize SOPC builder explore since their hands are not so flexible sometimes. In this paper,
Nios II embedded processor and what’s the benefit. DSP we want to bring forward a design of digital hearing aid, which
algorithm is also implemented in FPGA chip by Verilog HDL and uses SOPC (System on Programmable Chip), concrete
because of strong ability of parallel processing the system based speaking, uses FPGA (Field Programmable Gate Array) with
on FPGA runs faster than DSP chip does in signal processing. embedded software processor Nios II. This device promotes the
Third, the practicability of this device is explained through advantages of Nios II so that it can easily cooperate with
comparing with other hearing aids. The table shows the design peripheral equipments and use DSP (Digital Signal Processing)
has fine market respect because of its small size, cheap price and to deal with voice signal through relevant simulation
preferable operating performance. environment.
Keywords: FPGA; Hearing Aid; Nios II; DSP; II. CHARACTERISTIC OF FPGA AND NIOS II
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FPGA chip. Technicians utilize SOPC builder to custom In the part of signal processing, effort focus on dividing
embedded controller, typically Nios II, and DSP builder to add frequency, channels, automatic control of gain, how to
data processing module. These tools make FPGA stronger so eliminate background noise and how to compensate frequency
that it can handle almost all the applications in digital system response. In order to get basic information from low frequency
design. and get details from high frequency we divide voice into two
frequency band and do wave filtering individually, which is a
B. Nios II – an embedded soft core in FPGA
general method. People often decide the frequency division
Nios II processor is a general-purpose RISC soft core point at about 1.7~2.2 KHz [4]. Volume adjustment depends
provided by Altera in 2004. It has full 32-bit instruction set, on external potentiometer getting an analog input. De-noising
data path, and address space. Inheriting all the advantages of and compensation of frequency response are hotspots in
Nios, Nios II can easily implement custom peripheral research of hearing aid because the output voice users hearing
equipment and instructions. The Avalon bus is a unique is clear or not depend on the algorithm. But the algorithms are
technology used in FPGA, its most importance is solving not involved in this paper.
bottleneck of bandwidth for every bus arbiter. Nios II can be
loaded on certain families FPGA, basically technicians use Sampled
A/D audio
assorted software circumstance including Quartus II, Nios II MIC Signal FPGA
converter
IDE and SOPC builder to explore the device, and then use
software development environment based on the GNU C/C++ Worked Nios II
D/A audio
tool chain to write software program. After synthesizing the Speaker Signal
converter
design and downloading it into FPGA chip, an embedded
processor is produced.
Figure1. Block construction of digital hearing aid
Noteworthiness is Nios II has single-instruction 32*32
After processing the signal goes through a digital to analog
multiplication and division, 64-bit or 128-bit products of
audio converter and presents by speaker. Whistle is another
multiplication so that it is not inferior to DSP chip in mass
troublesome problem in digital hearing aid. Since speaker is
data processing, even better. Construction of programmable
fixed too close to microphone, the output voice comes into
DSP system can be built by DSP builder, and the function can
microphone again and forms feedback that brings whistle. We
be described by HDL (Hardware Describe Language).
compared different ways to decrease whistle, then we found
III. DESIGN OF SYSTEM SCHEME that it is an unavoidable problem in digital hearing aid while it
Digital hearing aid deals with voice through circuit so it seldom occurs in body hearing aid just because the distance
often does in a fixed buildup. Block construction can be seen between microphone and speaker is long enough. So we
in figure 1. Microphone acquires voice and converts it into decide to follow this way and improve it, which means we use
electronic signal. The next an analog to digital converter chip ear-jack in the circuit so that people can use all-purpose long
special for audio is needed. Then we get sampled voice. line earphone. Now whistle is solved.
Ordinarily voice is sent into DSP chip, but this time we send it IV. HOW TO ADD MODULES
into FPGA chip. These two chips have similar functions; the
Start SOPC builder to create a new Nios II system, which
difference is that FPGA has better performance and works
include Nios II processor and relevant peripherals. According
faster than DSP chip though their parallel operation both base
to hearing aid’s usage requirement, we need chiefly add
on highly pipeline[2]. Ripe algorithms such as FFT, IIR and
following modules, shown in figure 2.
FIR are proved many times faster running in FPGA than DSP.
It is because FPGA implement the instructions by hardware. • 32-bit CPU
• Timer
1896
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• JTAG DSP is an important part in hearing aid, which directly
decides the voice hearing from speaker. DSP can depart into
• External Flash Interface
two parts: hardware and software. We have constructed
• Analog to Digital Converter Interface hardware circuit by setting modules with Nios II as described
• Digital to Analog Converter Interface above, which has better ability of processing data than DSP
chip does [2]. While we can’t use statements of DSP to control
What we think about is how to make the hearing aid
processing directly, we need custom instructions by DSP
device has perfect performance and small bulk, so it
builder and Matlab/Simulink. Nios II have provided algorithm
doesn’t need too much input/output interface. In this
prototype for FFT and IIR. These custom-built instructions
system core chip is Cyclone II EP2C35F672, presented by
can be used in HDL file as library functions.
Altera. The chip has 35,000 logic elements which is
enough to implement the design. V. ANALYSIS OF PORTABLE HEARING AID’S
PRACTICABILITY
DSP Module
Nios II
Interface Hearing aid is the necessary for the hearing handicapped
32-bit CPU Flash
people and demand is so large. Since body hearing aid is
cheap and easy to use, but it can’t bring good effect. On the
Avalon Switch Fabric other hand, advanced digital hearing aids have perfect
performance but their high price scare most people away. My
Timer A/D D/A idea is to design a kind of digital hearing aid with cheap price,
Interface Interface small size bulk and strong signal processing ability. FPGA is a
good choice. After analyzing of basic indications we realize
JTAG Potentiometer with the application of FPGA and Nios II, it is possible to turn
interface this design into product. Indications comparison of different
hearing aids is given in table 1. Let’s call it FPGA
Figure2. Internal Module in FPGA
temporarily.
32-bit CPU uses as master port because it is the core of
TABLE 1. Comparison of different hearing aids
control and algorithm. We want the device can be used in
quiet circumstance; indoor circumstance and noise styles portable De-noise whistle easy nursing price
1897
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neck just like MP3, which will be a better way to 1) FPGA is a programmable device. Most of
maintain the user’s self-respect. work is finished by software and HDL program,
Error correction and debugging is easy in
• De-noise The performance of de-noising depends on
simulation environment and has no extra
excellent algorithm. In consideration of digital hearing
spending. So hardware costs little.
aids all using DSP algorithm, and better DSP chip
bring better result, we don’t compare them 2) Nios II is an open soft core. Compare with other
temporarily. hard core such as ARM and PowerPC, you don’t
need to pay for Nios II processor but get the
• Whistle As we know whistle comes from the
same function.
feedback of leaked speaker. When the device is
hanged from the neck, which means that we keep the VI. CONCLUSION
distance between MIC and speaker, it helps decreasing
In this paper we bring forward a design method of digital
whistle. So ear-jack is used in this design, every kind
hearing aid, in which FPGA works as core and Nios II plays
of earphone is suitable, that is a cheap and convenient
the role of central processor. The hardware we used has fast
method. At the same time, it saves time and money for
processing speed and tiny bulk, and are easily to improve. The
custom-built earphone.
part of speaker is modified so that it is more flexible for users,
• Easy Too small to use is a objective problem for tiny they can carry and use it everywhere conveniently. New
hearing aid. For example, user fixes his CIC hearing design has good portability and usability. Cooperating with
aid with the help of his family while he can’t change appropriate DSP algorithm it’ll be a perfect hearing aid device.
the setting frequently in varying circumstance without
REFERENCES
anybody’s help. Take a look from this side, we’ll find
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[4] H.T. Zhou, “DSP Application----Programmable Digital Hearing Aid,”
• Price Body hearing aid is the cheapest in these Journal of Fujian Teachers University (Natural Science), Vol. 18,
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kinds, which only costs dozens of dollars. Other [5] J. V. Oldfield and R. C. Dorf, Field Programmable Gate
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[6] Altera Corporation, Nios II Software Developer’s Handbook, December
acceptable by common people because there are few 2004.
hardware in the circuit. In addition, the cost of [7] Altera Corporation, Nios II Hardware Developer’s Handbook, December
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experiment and exploitation is even cheaper than
anything else.
The paper is supported by research item of Shanghai Normal University 2008. Number is SK200861
1898
Authorized licensed use limited to: Gandhi Institute of Technology & Management. Downloaded on July 12,2010 at 16:04:38 UTC from IEEE Xplore. Restrictions apply.