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Fermi-FET Technology


Transistor scaling, a major driving force in the industry for decades,

has been responsible for the dramatic increase in circuit complexity. Shorter
gate lengths have required lower drain voltages and concurrently lower
threshold voltages. Recent CMOS evolution has seen a dramatic reduction in
operating voltage as transistor size is reduced. This was due to the maximum
field limit on the gate oxide needed to maintain good long-term reliability.
Proper selection of the gate material can produce low threshold transistors with
off-state performance parameters equivalent to high threshold devices.

The Buried Channel Accumulation device, currently being used for p-

type transistor processes has the Fermi level at a considerable depth from the
gate thereby making it difficult to shut the device off. Attempts to bring the
Fermi level up result in severe degradation of device performance. Need for
optimization of existing BCA technology arose and Thunderbird Technologies,
Inc. delivered! The ‘incredible’: Fermi-FET.

The Fermi-FET technology brings the Fermi level nearer to the gate.
This technology merges the mobility and low drain current leakage of BCA
devices as well as the higher short channel effect immunity of SCI devices.
This paper highlights aspects of the technology in a non-mathematical
presentation to give a sound general understanding of why the technology is
the most promising avenue for advanced very short devices.

Fermi-FET technology can lead to significant improvement in circuit

performance, layout density, power requirements, and manufacturing cost with
only a moderate alteration of traditional MOSFET manufacturing technology.
This technology makes use of a subtle optimization of traditional buried

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channel technology to overcome the known shortcomings of buried channel
while maintaining large improvements in channel mobility.

Fermi-FET can optimize both the N-Channel and P-Channel devices

with a single gate material, provided the work function is near the mid-range
between N and P-type polysilicon. Materials that have been used in MOSFET
technology with a suitable work function include Tungsten, Tungsten Silicide,
Nickel, Cobalt, Cobalt Silicide, P-type Ge:Si and many others. There is about a
30% reduction in junction capacitance relative to traditional MOSFET devices.
This fact alone gives a significant speed advantage to the Fermi-FET in large
scale circuits. The total speed improvement produced by both the lowered
threshold and lowered gate and junction capacitances is very substantial.

In order to illustrate the impact of lowered threshold voltages via

work function engineering, the large-signal transient response of two inverter
structures was simulated. A comparison of conventional CMOS and metal-gate
Fermi-FET structures was performed. It is seen that the Fermi-FET inverter
displays significantly improved rise and fall times compared to the MOSFET.
The different delay characteristics are evident. It is seen that the Fermi-FET
inverter displays significantly improved rise and fall times compared to the
The individual device DC characteristics were already well-known
from the device simulations. For each inverter, the supply voltage was ramped
up to Vd with a delay sufficient to allow the circuit nodes to settle to their initial
DC state with the input low. The input was then pulsed high, then low; again
with a delay time long enough to guarantee all nodes reach steady state. The
corresponding outputs obtained give a comprehensive view of the device
performance as compared to the traditional technology and thus acts a primary
assessment of the feasibility of the new technology in lieu of existing ones.

Fermi-FET Technology

Figure (a)

The output of the mixed-mode simulations is shown in the figure.

Even at 0.4 mm gate length the low threshold Fermi-FET is almost twice as
fast as the MOSFET in this simple circuit.

Simple circuits such as this underestimate the benefit of the lowered

capacitance associated with the source/drain junctions, but they virtually ignore
the capacitance associated with the extended wiring in large circuits. The
Fermi-FET is the emerging technology in the ever-expanding empire of
electronics circuits and devices and is slated to be crowned the king in
foreseeable future.

Fermi-FET Technology


The Fermi-FET is a unique patented variation of the broad class of

devices known as “Field Effect Transistors” (FET). Although the transistor
operation differs markedly from standard MOSFET devices, the structure of
the new device has many similarities, thus permitting easy conversion of
existing CMOS process lines to production of Fermi-FET transistors.


The basic principle behind the working of a Field Effect Transistor is

the conducting semi-conductor channel between two ohmic contacts; source
and drain. The gate terminal controls the channel current and is a very high-
impedance terminal. The FET is thus a three terminal, unipolar device. The
name ‘field effect’ is due to the fact that the current flow is controlled by
potential set up in the device by an external applied voltage. There are two
types of FETs – JFET and MOSFET. The FET of interest here is the MOSFET.

The N-channel MOSFET has two lightly heavily doped n- regions

diffused into a lightly doped p-type substrate; separated by 25 μm.These n-
regions act as source and drain. An insulating layer is grown over the surface.
Metal contacts are made for the source and drain. A conducting layer of metal
will act as the gate, overlaying the insulating layer over the entire channel
region. Due to the presence of the insulating layer, the device is called
Insulated Gate FET (IGFET) or Metal Oxide Semiconductor FET ( MOSFET).

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Modern Complementary MOS (CMOS) processes incorporate
polysilicon gate structures less than 0.25 micron long, with the most common
process being 0.15µm. At this geometry, and the standard 1.8 volt Vdd, oxide
spacers and drain extensions are common. Most processes also make use of the
oxide spacer to form salicide on the gate and diffusions to reduce the sheet
resistance and to control the polytime constant on wide transistors.

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Most short channel CMOS processes create SCI type transistors for
both P and N-Channel devices. This decision has evolved as line widths
attained shorter dimensions primarily due to the reduced short channel effect
sensitivity of the SCI devices over the BCA transistor, traditionally used for the
PMOS. Its because of the widely known control problems with deep buried
channel transistor (BCA) technology that most short channel processes
incorporate both n-type and p-type polysilicon gates to create surface channel
inversion (SCI) devices for both transistor polarities.


Figure 1 – A cross-section drawing of an N-Channel SCI MOSFET

transistor. The polysilicon gate would be degeneratively doped n-type. The
drain extension region is typically utilized to reduce short channel effects
Figure 1 depicts the main features of a short channel NMOS SCI
device. Certain other refinements aimed at reducing short channel effects such
as pocket implants, SSR well, graded channel, and elevated diffusions have
been ignored for simplicity.

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The operation of surface channel transistors is relatively simple to

envision. Figure 2 shows an enlargement of the channel region with the source
end drain extension from Figure 1. As the gate electrode is biased from zero
(fully off) toward the threshold voltage, the initial charge on the gate drives
free holes in the substrate away from the gate region.

Figure 2 – A close-up of the channel region in Fig. 1 near the drain

side of the gate. The gate electrode has a positive bias but is below threshold
voltage. The silicon depleted of mobile carriers is shown as a white area. The
arrows represent the vertical field direction.

The combination of depletion charge on the gate and induced space

charged depletion region in the substrate create a vertical electric field through
the dielectric and into the substrate. This impedes carrier movement and hence
decreases carrier mobility. This is a major disadvantage of SCI transistors
affecting device performance to a large extent.

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Device scaling has forced the gate oxide to become ever thinner and
the average doping in the well region to increase. These lead to reductions in
carrier mobility; the ease with which charges can move through the transistor
producing drive current.

Figure 3 – The same region as in Fig. 2, but the gate bias is now just
above the threshold. The depletion region has reached its maximum depth and
a thin region of “inverted” silicon (n-type carriers in p-type silicon) exists just
below the gate oxide. The arrows represent the vertical field and consist of two
parts. The first part supports the depletion region and the second part reflects
the carriers in the inversion layer.

As the gate bias continues more positive, the threshold voltage is

reached. At this point the depleted silicon region under the gate stops
expanding and additional charge on the gate results in free conduction carriers
from the diffusion moving to the region under the gate (see Figure 3). It is
these carriers that are responsible for the output current of the transistor.

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It should be noted that for an SCI device, good short channel

performance requires high channel doping to counteract short channel induced
leakage and threshold drop, but at the same time needs a low threshold voltage
due to the low operating voltages of short channel processes. This dictates the
thinnest possible gate oxide must be used.

The thin gate oxide and high vertical electric fields have caused a new
challenge not previously large enough to cause difficulties; polysilicon
depletion. Polysilicon depletion occurs when free carriers are swept away from
the bottom of the poly gate due to high vertical fields. In an SCI type of device,
this occurs when the transistor is fully turned on. As can be seen in Figure 3,
this depletion causes the gate dielectric to appear thicker than it actually is,
reducing transistor performance.

In summary, SCI devices, the current device used in many short

channel applications, have three major design difficulties:

• High Capacitance – As SCI devices shrink, the higher substrate doping

causes increased parasitic junction capacitance around the source and drain

• Lowered Channel Mobility – Higher channel doping and increased

vertical electric field make it more difficult for carriers to move across the

• Polysilicon Depletion – The high charge on the gate can cause

polysilicon depletion to occur, lowering the transistor drive current.

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At longer channel widths, the BCA architecture was widely used for
the P-Channel transistor in CMOS processes. This was primarily done because
the BCA transistor would use the same n-type polysilicon gate used by the N-
Channel device, greatly simplifying the process. Recently it became apparent
to most manufacturers that the BCA architecture was incapable of scaling to
the very fine line widths in development today. The added process complexity
of using both n-type and p-type poly was offset by the better SCE immunity of
the SCI transistor.


Figure 4 – A cross-section drawing of an N-Channel BCA transistor.

Note that the polysilicon gate would be doped p-type. The drain and source
extensions are connected by an n-type channel layer. An N-Channel BCA
device would be built with the structure shown in figure 4. The polysilicon
electrode is p+, and there is an n-type channel between the source and drain.
The depth of the channel is minimized to reduce short channel effects (SCE).

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Although the structure of a BCA device is very similar to a SCI

transistor, the operation of the two is markedly different. This is due to the
presence of the p-n junction formed by the “channel” and well regions
abutting. As in all p-n junctions, free carriers diffuse across the junction until
the retarding field, due to the ionized donor and acceptor atoms, causes the
drift and diffusion flows to equalize. This field leads to the built-in potential of
p-n junctions. The magnitude of this built-in potential is determined by the
doping density of the silicon on both sides of the junction.

This potential causes carrier depletion on either side of the
metallurgical junction. The widths of these depletion regions are proportional
to the relative doping of the p and n regions. In traditional BCA architectures,
the “channel” region is more highly doped than the well region beneath it. The
arrows in Figure 6 show the vertical electric fields present with the gate
electrode at zero bias.

Figure 5 – A close-up of the channel region from Fig. 4 above.

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The dashed line depicts the location of the p-n junction and depleted
silicon is shown as a white area. The arrows represent the vertical field
direction. Note that the junction potential is not high enough to fully deplete
the entire channel region. There is another field due to the gate work function
that also depletes the surface part of the channel region.

This potential also causes some depletion of charge near the
bottom surface of the gate. Since the gate doping is usually very high the
depletion width in the gate is small, but as channel lengths shrink, this can
become an important effect in the subthreshold region.

Figure 6 – A graph depicting the vertical electric field on a line

normal to the silicon surface under the conditions of Figure 5. Wjn and W jp
make up the space-charge region due to the metallurgical junction. The region
labeled Wpn is depleted due to the potential difference between the gate and the
channel. This charge is reflected in the poly depletion Wpp .

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Figure 6 shows the vertical electric field in the wafer with the gate
electrode at zero bias (as in Fig. 5). Note that the field reverses direction within
the channel region where the depletion from the junction Wjn meets the
depletion induced from the gate electrode Wpn.

As the gate electrode bias is moved from zero towards V dd , the field
from the gate initially decreases reaching zero at Vt . The gate field then
reverses and begins to climb as more charge is injected into the channel at the
source electrode. Figure 7 shows the conduction channel forming just above
the junction depletion region.

Figure 7 – The channel region from Fig. 5 above, with the gate bias at
just above the threshold voltage. The channel begins to open near the edge of
the junction depletion region and widens toward the surface as neutral silicon
until the surface is reached. High-level injection begins after this point.


BCA devices have a significant advantage over SCI devices in terms

of channel mobility. This is due to two reasons.

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• First, the vertical field within the channel is substantially lower in a BCA
device. This is because the gate does not have to deplete majority carriers away
from the interface to form a channel. The gate supplied vertical field is due only
to the mobile conduction charge.

• Second, improvement in channel mobility because this architecture can

be made with a significantly lower total doping density in the channel. This
improved channel mobility is a major advantage over traditional surface channel
inversion devices.

Figure 8 – The vertical electric field on a line normal to the silicon

surface under the conditions of Figure 7. Note the neutral region above Wjn
below Wpn . Increasing the gate bias will reduce Wpn and Wpp but leave the
junction field largely unchanged.

Figure 8 shows the vertical electric field associated with a transistor

in the condition shown in Figure 7. Further increases in gate bias result in the
channel width increasing toward the surface and then excess carriers are
injected with an exponential distribution peaked slightly beneath the interface,
as shown in Figure 9.

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Figure 9 – With sufficient gate bias, the channel is under high-level

injection. Since the carriers are majority type the only vertical field present
within the conducting layer is that due to the conduction carriers themselves.

Note that the junction depletion region remains largely unchanged

during the gate sweep. Figure 9 shows the vertical field profile with the gate
bias near Vdd. Even though the conduction carrier distribution at this point has
the same exponential shape as an SCI device, the distribution width is greater
in the BCA and the peak concentration is lower. This decreases carrier-carrier
interactions also helping BCA channel mobility.

Another benefit of this type of device is that the poly depletion occurs
at the off state. Poly depletion negatively affects leakage but not drive current.
This is in itself a rather important development and hence needs to be
optimized further to suit growing demands on semi-conductor technology.

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Figure 10 – The vertical electric field under the conditions of Figure

9. Depending upon the lateral field conditions there may or not be any region
above the junction with a zero vertical field component.


At longer channel widths, the BCA architecture is superior to surface

channel architectures. The improved channel mobility leads to higher
saturation current, the lower substrate doping can dramatically reduce the
parasitic diffusion capacitance and the wider channel lowers the gate
capacitance at equivalent oxide thicknesses. Problems with this type of
transistor appear as the channel length and operating voltage decrease.

Transistor scaling, a major driving force in the industry for decades,

has been responsible for the dramatic increase in circuit complexity. Shorter
gate lengths have required lower drain voltages and concurrently lower
threshold voltages. The problem with the BCA is that the channel turns on at
the bottom of the conducting channel, far removed from the gate electrode as
shown in Figure 7. With the initial conduction far from the surface it can be
difficult to shutoff the device.

Fermi-FET Technology

Figure 11 - Atlas output predicting the N-Channel Id Vg performance

of identical BCA MOSFET transistors at two different L o values.

Notice in Figure 11 that the subthreshold region of the shorter device

is no longer linear. The two devices show a ΔVt of a reasonable 0.08V, but as
the gate bias approaches zero volts, there is a distinct non-linearity to the
shorter line width subthreshold swing. The huge rise in leakage produced by
this effect limits the usefulness of the device to devices above a minimum line

Transistor scaling requires the operating voltage of devices to be

reduced as well. SCI devices are able to reduce threshold by thinning the gate
oxide thickness. BCA devices have only a very small but negative correlation
between Vt and Tox . Threshold can be reduced in a BCA by increasing the
channel depth, which augments the problem above as the channel opens even
further from the gate as the threshold is dropped. Threshold can also be
reduced by increasing the channel doping, keeping the depth constant. This

Fermi-FET Technology
improves the 2D degradation, but the mobility reduction with the added doping
removes the drive current advantage.

Figure 12 - Atlas output predicting the N-Channel Id Vg performance

of BCA MOSFET transistors with reduced thresholds by increasing doping in
the channel region.

The problems associated with BCA devices all spring from the fact
that the channel opens from the bottom, significantly removed from the gate.
This lack of “gate coupling” leads to the poor subthreshold swing and limits
the minimum attainable channel length. These problems can b esummarised as

• Minimum attainable channel length is limited-as the depth of the channel

is reduced, depletion regions attain comparable dimensions
• The BCA transistor is difficult to turn off- the opening is at the bottom of
the channel, far removed from the gate electrode
• The sub-threshold swing is non-linear- the sub-threshold characteristics
of BCA devices is poor

Fermi-FET Technology


The channel of a BCA device first opens at the edge of the channel
side depletion region caused by the p-n junction (see Figure 7). If the doping
density in the channel layer is lowered, or the layer is made thinner, the
channel will open closer to the gate oxide interface. Eventually there will not
be enough dopant in the channel layer to completely satisfy the space-charge
requirement of the junction below it. With less dopant in the channel than the
junction requires, the conduction path will open at the silicon surface similar to
a SCI device, but the conduction in this type of transistor will be majority
rather than minority carriers. Hence the name Surface Channel Accumulation
or SCA transistors.

Figure 13 – Long channel simulations showing the Subthreshold

Swing vs. Xj for three different Nd :Na combinations . As the junction
approaches the surface, the transistor changes from BCA type to Fermi-FET
and then to SCA type.

Fermi-FET Technology


SCA and BCA transistors make up the broad family of “buried

channel” transistors. The Fermi-FET transistor is a specific optimization of
buried channel transistors. A Fermi-FET transistor occupies the region near the
crossover from BCA to SCA devices. This allows a Fermi-FET to have the
mobility and subthreshold swing advantages of a BCA device while
maintaining the short channel effect immunity of a SCI or SCA transistor.

Figure 13 shows the “S” parameter or Subthreshold Swing of long

channel transistors using several combinations of substrate and channel doping
densities. Regardless of the doping levels used, there is a minimum S value
where the device transitions between BCA and SCA operation.This is the
Fermi-FET region. This minimum value corresponds to the point where the
device threshold is roughly equal to the Fermi-potential plus the built-in
potential of the junction. The S-chart serves as a means to “tune” the profiles
for maximum Fermi-FET performance.

Figure 14 shows simulation results of N-Channel transistors with gate

lengths of 0.2 µm. Both devices have identical gate oxides and Source/Drain
diffusions. The Fermi-FET device uses p-type polysilicon for the gate electrode
while the SCI device uses the traditional n-type. Because of the low drain
voltage (1.8V), the Fermi-FET was moved slightly toward the BCA end of the
range to reduce the threshold somewhat.

Even with a much higher Vt , the Fermi-FET device outperforms a

similar surface channel device.The linear graph clearly shows the much
improved mobility of the Fermi-FET. Both devices have identical diffusion
profiles and contact spacing. The log plot of Figure 14 shows that there is a

Fermi-FET Technology
small amount of DIBL penalty for this device, but even at the BCA end of the
threshold spectrum it is still a reasonable amount. Higher operating voltages
allow an even greater performance improvement due to increased overdrive,
but lower operating voltages (further scaling) require threshold voltage
lowering techniques.

Figure 14 – Simulation of identical SCI (dashed line) and Fermi-

FET (solid line) transistors produced these IdVg curves


Figure 15 depicts a Fermi-FET transistor analogous to the BCA

device shown in Figure 7. The difference being that the doping in the channel
region is lowered (or the depth is decreased) such that the depletion region
from the p-n junction would extend to the region very near the surface of the

Fermi-FET Technology

Figure 15 – A close-up of the channel region of a Fermi-FET type of

transistor. This drawing is similar to the BCA shown in Fig. 5. The dashed line
depicts the location of the p-n junction and depleted silicon is shown as a white

With the junction depletion using most or all of the dopant in the n-
channel, an interesting aspect of SCA devices occurs. Equation 2 defines a
built-in potential associated with a gate electrode added above the oxide in
Figure 13. Movement of charge between the polysilicon gate and the silicon
must balance this potential, but there is not enough charge left within the
channel region to deplete and satisfy the potential difference.

Figure 16 illustrates how this extra charge movement is accomplished

in a SCA device. Once all mobile electrons are depleted from the channel,
additional potential increase is created by moving holes from the substrate into
the formally n-type region, creating a “volume inversion” or a psuedo p-type

Fermi-FET Technology

Figure 16 – A simulation depicting the location and density of mobile

charged carriers in the substrate of a Fermi-FET transistor. Electrons and hole
concentrations are shown according to the scale at left. Only concentrations
above ni are shown so the white regions designate depleted silicon. The Gate
and Source are at zero volt bias with the Drain electrode at 1.5 V (right side).

This volume inversion is unique to the SCA (and Fermi-FET) type of

device. It is responsible for the lack of short channel roll-off usually seen in
BCA type transistors. With the gate potential at zero, the drain field cannot
reach the source diffusion and cause carrier injection. The drawing in Figure 16
was produced using Silvaco International’s Atlas program. The simulation was
continued with increased gate bias through threshold into saturation. As the
gatebias is increased slightly, the excess holes are swept away from the
interface. The Figure ‘A’ uses the identical carrier concentration shading
histogram shown in Figure 16.

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Even 100 millivolts on the gate is enough to deplete the silicon

surface region. At this gate bias, the drain current begins to rise although the
current level and carrier concentration are still very low. Further increases in
Vg continues this process. At V g =0.3V, the concentration in the channel is
above n i , but still less than the chemical donor concentration in the channel
region. The channel layer still has a positive space charge. This is shown in
Figure ‘B’.

Note that the current flow while at the surface near the source is not
tightly bound to the interface by a strong vertical field as in a SCI device. At
the drain end of the channel, the current flow actually moves significantly
away from the interface due to the relatively high drain bias. The low vertical
field is one of the main contributors to the significant increase in channel
mobility of this type of transistor.

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At this gate bias, the channel region contains many more free
electrons than holes, but the electron concentrations are still far short of the
ionized donor atom population. Charge neutrality has not yet been reached, so
no carrier accumulation in the channel has occurred. We define threshold of
SCA or Fermi-FET devices as the point at which the channel carrier
concentration exceeds the net chemical dopant concentration; the onset of
strong accumulation.

The Figure ‘C’ shows still higher gate bias with a dashed white line
representing the electron concentration of 1017 cm-3 at the source diffusion. 1017
is roughly the net dopant concentration in the channel so the line roughly
represents the boundary between strong and weak accumulations. The
transistor has not yet reached Vt , although the channel charge and drain current
are both rising rapidly. The high threshold is a potential drawback of this type
of device. If it were not possible to overcome this limitation, it would be
unusable for low voltage applications.


At an applied gate bias of 0.9 V. the 1017 carrier concentration line is

now continuous across the channel region. This situation corresponds roughly
to a traditional extrapolated V t and results in a drain current of approximately
10 A/µm. If the transistor falls into the Fermi-FET category, the vertical
component of the electric field through the gate dielectric is close to zero at a
gate bias of Vt . The very low vertical field results in near-bulk carrier mobility

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in the channel. This can be seen in the high gm values (about 3X higher than
SCI) near threshold. Figure 17 shows a Fermi-FET transistor in saturation
along with a surface channel device of identical size for comparison.


Figure 17 – Simulation results of Fermi-FET (left) and SCI (right)

transistors depicting the location and density of mobile charged carriers in the
substrate. Both transistors are in saturation with Vg =Vd =1.5V.

Note in Figure 17 that the carrier type in the polysilicon gate is

opposite since an N-channel Fermi-FET uses p-type polysilicon as a gate.
Another point of interest is the large difference in the depletion width between
the two transistors. This is due to the lower substrate doping levels used in a
Fermi-FET and results in lower parasitic junction capacitance.

Figure 18 shows the simulated drain current output of the two

transistors illustrated in Figure 17. The Fermi-FET clearly shows the potential
for superior performance with a subthreshold swing of 73.3 mV/decade
compared to 91.5 mV/decade for the SCI device, but the higher Vt of the

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Fermi-FET does not permit enough overdrive to match the saturation current
seen in the inversion device.

Figure 18 – ATLAS simulation results of Fermi-FET and SCI

transistors depicting the IdVg response in both log and linear plots. Both
transistors have identical gate lengths and dielectric thicknesses.

Short channel lengths have been accommodated in SCI and traditional

BCA devices by reducing the applied drain voltage and the threshold voltage
accordingly. The Fermi-FET however operates near the point where the
channel junction just depletes the channel region as shown in Figure 15. If the

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threshold voltage is dropped by increasing the channel doping or making the
channel deeper, the device will move into the BCA mode of classical buried
channel transistors with it’s poor short channel performance.

As long as Vd is large compared to the threshold voltage Vt , (Vd = 2.5

Vt ) the increased lateral carrier velocity in the channel of the Fermi-FET
produces a higher saturation current. Without a suitable low threshold Fermi-
FET, only higher voltage applications would benefit from the improved
transistor architecture. Fortunately a viable alternative is available to permit
operation at any threshold desired.


Minimizing the vertical component of the electric field in the channel

is responsible for the improved mobility performance of the Fermi-FET. This
optimization does however limit the range of threshold due to the substrate
doping. Changes in channel doping are possible, in fact they are desirable for
particular line widths and applications, but these changes must be accompanied
by changes in the Well doping and/or channel depth to maintain the Fermi-FET
low field condition. This means that many different channel doping levels will
all have approximately the same threshold voltage.

In Fermi-FET devices, threshold reduction must be implemented in a

different manner The factors responsible for the threshold voltage in a buried
channel transistor (including the Fermi-FET transistor) are defined in Equation
3 below. Equation 3 represents the terms behind the threshold voltage of a
buried channel transistor. The threshold voltage (neglecting the ∆ Vt term
which is the result of short channel effects) is made-up of four distinct voltage
components. These are shown graphically in Figure 19.

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Figure 19 - Athena simulated cross section with the component

voltages from the Vt equation.

• V 1 results from the difference in contact potential between the aluminum

metal and the p-type polysilicon gate, and the aluminum metal and the p-well
region under the fermi-tub structure.

• V 2 quantifies the voltage induced across the depletion region below the
fermi-tub:p-well junction.

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• V 3 represents the voltage across the fermi-tub itself. This is made up of
the depletion region above the fermi-tub:p-well junction and depletion between
the junction induced depletion region and the silicon surface due to the gate

• V 4 quantifies the voltage developed across the gate oxide due to the field
from the polysilicon gate terminating on charge in the region defined as V 3 .

The Fermi-FET is a special case and can allow the equation to be

simplified. Since the Fermi- FET condition requires the depletion region to just
deplete the channel region, V 2 and V 3 reduce to the potential across the
junction itself.


With the tub fully depleted by the junction in a Fermi-FET, there will
be virtually no vertical gate field at threshold, so V4 reduces to zero. This
means that the threshold voltage of a Fermi- FET transistor using a polysilicon
gate reduces to just V 1 +V 2 +V 3 .


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Equation 5 shows that lowering the threshold voltage of a Fermi-FET
is best accomplished by changing the first term. Large changes to the second
term would move the device away from the Fermi-FET region. This is opposite
to the traditional methods of threshold control.

V 1 is basically the difference in work function between the gate

electrode material and the silicon substrate just below the depletion region.
Figure 20 shows I d Vg simulations with an identical substrate but different gate
materials. Choosing a gate with the proper work function allows threshold
voltages well within the BCA range for a polysilicon gate device, but with
none of the short channel penalties associated with deep buried channels.

Figure 20 – Simulated IdVg show the effect of different work


It is clear from Figure 20 that almost any desired threshold could be

attained by variations possible to the V1 term. More importantly, if a material
with a work function near the midpoint of the silicon band-gap were used, the

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same material would serve for both the P-Channel and N-Channel transistors.
Such materials are Tungsten, Titanium Nitride, Tungsten Silicide, and several
others not shown in the graphic.

Metal-gated Fermi-FET structures have yet to be verified

experimentally, but initial experiments appear to affirm the academic work that
postulates that the Fermi-FET architecture maintains significant advantages
over SCI devices at least through gate lengths of 50 nm. In addition, the
lowered vertical field in the Fermi-FET produces dramatic reductions in gate
tunneling currents through very thin gate dielectric layers.


The Fermi-FET device developed and patented by Thunderbird

Technologies Inc. can provide significant performance advantages relative to
conventional CMOS technologies for a variety of products. The discussion
below is a brief overview of several product areas that is predicted to benefit
most from the Fermi-FET technology.

In general, the Fermi-FET will directly benefit performance-driven

digital products, due to the higher drive current and lower capacitances
inherent in the device architecture. The Fermi-FET has also been evaluated
with respect to some of the other considerations that impact technology
decisions, such as process sensitivity, leakage, power consumption,
temperature and noise characteristics, scalability and reliability. In addition, the
costs, in terms of dollars, human resources and time-to-market constraints must
be carefully weighed when considering any new technology introduction.
Considering these issues, the following product groups is expected to benefit in
terms of market differentiation and competitive advantage.

Fermi-FET Technology
• DSP - Due to the increasing ASSP nature of the DSP market, in contrast
to the MPU market, designs are introduced based upon specific market
demands. This allows easier introduction of a new device or process technology
into the product line. An existing CMOS line may be run in parallel with a new
Fermi-FET line to support existing products, while existing products are
redesigned, if feasible, and new products are being introduced. The technical
benefits to be derived from the Fermi-FET technology for DSP products are
expected as follows:

a) The Fermi-FET offers significantly higher performance due to lower

intrinsic device capacitances and better drive current. In the highly competitive
DSP market, this is particularly important.
b) Considering analog content, the Fermi-FET should offer lower noise than
conventional CMOS, due to its buried-channel nature. This has not been verified
experimentally yet, but it is reasonable to expect based upon the device
structure, and its physics of operation.
c) Again concerning analog behavior, the Fermi-FET provides a
significantly higher small-signal transconductance just above turn-on compared
to a surface-channel device. Combined with the lower intrinsic capacitances, the
higher gm means higher fT devices.
d) Matching properties should exceed those of conventional surface-channel
devices, again due to the device's buried-channel nature, the lower dependence
of Idsat on Vt, and the low dependence of Vt on oxide thickness.
e) Temperature characteristics of the Fermi-FET have been measured and
typically exceed those of conventional surface-channel devices, in terms of
current drive degradation with temperature.

Fermi-FET Technology
• MPU - For standard MPU products which are more performance-driven,
rather than price- driven, the Fermi-FET must be introduced at an appropriate
point in the technology roadmap. The MPU products require the highest
performance possible, but are also very sensitive to time-to-market requirements
and need design information which is timely and as accurate as possible.
Technology scalability is also extremely important. Scaling the device to very
deep-submicron linewidths, while retaining the performance advantages at
longer linewidths is possible. Thunderbird is currently working on methods to
extract Fermi-FET design information from measured data and/or simulations in
a way that is compatible with existing commercial EDA tool sets. This is
critically important. Product designers need to learn how to design with the
Fermi-FET as quickly as possible, and the device characteristics need to be
incorporated within the design methodology as smoothly and efficiently as

• MCU - For product applications such as these which may be embedded,

are already established as catalog parts and are more price-driven, rather than
performance-driven, the Fermi-FET can provide nearly a generational leap in
performance with very little (if any) investment in retooling required. It has
been Thunderbird's experience that it is often possible to reduce process
complexity, due to the lack of the LDD in the device structure, for example,
hence lower the manufacturing cost. Analog bolt-ons to MCU parts will also
enjoy the same benefits as the DSP products.

• Logic/ASIC/FPGA/Gate Array - General purpose logic will also

benefit from the Fermi-FET's higher performance, of course, but the cost of
porting such low margin products to a new technology should be carefully
considered. The most likely candidates will be the ASIC, and perhaps gate array
products. For these applications, the stream of designs may be simply switched
over to the new technology once it is qualified. Gate array base levels would

Fermi-FET Technology
need to be redesigned, to take advantage of the expected performance increase.
It would be reasonable to expect to be able to shrink die size based upon the
device performance, for a given linewidth. This of course leads to lower
manufacturing costs.

• SRAM - As with the general-purpose digital applications, SRAM would

clearly benefit from the reduced device capacitances and higher drive current.
Due to the higher performance, it would be possible to shrink cell and I/O
dimensions, and subsequently decrease the die size. As with ASICs and gate
arrays, decreased die size means lower costs. This is in addition to the benefits
derived from increased yield due to device stability with manufacturing

• Analog/Mixed-Signal - Telecom, data conversion and networking

products would all benefit from the characteristics mentioned in the DSP bullet.
To date, no Fermi-FET analog blocks have been fabricated by Thunderbird, but
the expectations of lower noise, higher transconductance with lower device
capacitance, hence higher fT are reasonable based upon current device physics
knowledge and simulated characteristics.

• Power MOS - This is an area Thunderbird plans to explore in the near

future. Due to the buried nature of the channel, for longer channel length
devices, the current density capability of the Fermi-FET is greater than surface-
channel CMOS. Due to the higher mobility experienced by the carriers in the
channel, the Rdson at a given geometry will be lower than conventional surface-
channel devices as well. This allows either die shrinks or increased drive
capability for applications requiring a very low output impedance, such as
motors and actuators.

Fermi-FET Technology

Fermi-FET Technology


In summary, the products which are probably in the best position to

benefit from the Fermi-FET technology could be ranked as follows:

• DSP products (ASSP and standard parts)

• MPU products (CPUs)

• MCU products (embedded or standard parts)

• Networking products (ATM chips)

• SRAM products

• ASICs/Gate Array products

• Analog/Mixed Signal products (Conversion, industrial control)

• Power/RF products (not known at this time)

Of course the list above is not exclusive, and there are many more
areas which could benefit from a high performance device architecture such as
the Fermi-FET.Significant manufacturing advantages may surface as well, but
this is simply a reasonable expectation since not enough silicon has been run to
compile a statistical database for any of the Fermi-FET variants made to date.
The expectation is based upon the limited silicon to date, and an intuitive

Fermi-FET Technology
understanding of the device sensitivities. Other advantages may surface as
well, particularly with respect to the path-breaking low-threshold technology.


The Fermi- FET is the latest in emerging revolutionary transistor

technologies. Initial experiments appear to affirm the academic work that
postulates that the Fermi-FET architecture maintains significant advantages
over SCI devices at least through gate lengths of 50 nm. In addition, the
lowered vertical field in the Fermi-FET produces dramatic reductions in gate
tunneling currents through very thin gate dielectric layers. These features and
the inherent advantages of the Fermi- FET over the existing traditional
transistor technologies renders it the most promising of all evolving

The performance advantages gained by using the Fermi-FET will

provide unique marketing opportunities, through distinct product
differentiation, which is important in increasing market share. In addition,
decreased manufacturing costs, improved yields and die shrinks provide a rapid
return on investment. Finally, as the Fermi-FET continues to be scaled, the
technology will provide a sustainable competitive advantage.

Fermi-FET Technology


1. B. L. Austin. Performance Analysis and Scaling Opportunities of

Bulk CMOS Inversion and Accumulation Devices. PhD thesis, Georgia
Institute of Technology, MAY 2002

2. M. W. Dennen. Fermi-FET technology

3. Ben G. Streetman. Solid State Devices



Fermi-FET Technology


Fermi-FET transistor technology can lead to significant improvement

in circuit performance, layout density, power requirements, and manufacturing
cost with only a moderate alteration of traditional MOSFET manufacturing
technology. This technology makes use of a subtle optimization of traditional
buried channel technology to overcome the known shortcomings of buried
channel while maintaining large improvements in channel mobility. This
technology merges the mobility and low drain current leakage of BCA devices
as well as the higher short channel effect immunity of SCI devices. This paper
highlights aspects of the technology in a non-mathematical presentation to give
a sound general understanding of why the technology is the most promising
avenue for advanced very short devices.

Fermi-FET Technology