RedHawk Training PDF

RedHawk Training
Apache Design Solutions

Product Training Seminar Series
VERSION: V5.1-AL-RH122-08FEB2013
1 © 2012 ANSYS, Inc. March 8, 2017 Apache

Apache
Design,
Design,a asubsidiary
subsidiary of
of ANSYS
Training Agenda
• Voltage Drop Analysis Theory
• RedHawk Static and Dynamic Analysis Flow
• RedHawk Low Power Flow
• Using Tcl Commands in RedHawk
• RedHawk Explorer
• VCD Handling in RedHawk
• Package Netlist Handling
• Chip Power Model Generation
2 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

Apache Product Platforms
RedHawk
Power-Noise-Reliability Platform for Digital SoCs
Voltage Drop (Static/Dynamic), EM (Signal/Power), Fix and Optimize,
Psiwinder(Timing), Low Power verification
Totem
Power-Noise-Reliability Platform for
Analog/Custom/Memories
Voltage Drop (Static/Dynamic), EM (Signal/Power), Substrate Noise Analysis
Sentinel
Package-Board Level Extraction, Analysis Platform
3D Full-wave Extraction - AC, DC, Transient Analysis
Power Artist
RTL and Gate Level Power Calculation
Analysis Driven Power Optimization
RedHawk
SoC “PNR” Platform
RedHawk
NX SEM PsiWinder ALP PathFinder

Power Reliability Noise Low Power ESD
 Grid Weakness  Average  Clock jitter  Rush-current  Rule based

 Static/Dynamic power  RMS  Critical path  Differential Voltage  Static
 Static/Dynamic Drop  Peak  Crosstalk  Noise Coupling  Dynamic
 Power EM  Switched memory
 Fix & optimize analysis
 Embedded package

Static Voltage Drop Background
Vdd Pad Ipad
R
Iavg Iavg
Cload Cload
Vss Pad
Instance Instance
 On-chip power/ground network  mesh of resistors

 Instances  DC current sources

Static Voltage Drop on P/G Network
• Average current is calculated for each instance

• Vstatic is computed at every node (Ohm's law ...)
• Wire / via electromigration (EM) is post-processed from static current
density
Vstatic
Vdd Pad Ipad
R
Iavg Iavg
Vss Pad

Gate-level Average Power Calculation
Leakage Internal Switching Average

Power Power Power Power
Switching Power = ½ * Cap * V^2 * Freq * TR
From SPEF
From Timing File
From .lib
Internal Power = Internal Energy(in .lib) * Freq * TR
P(total) = P(Leakage) +
½ * (Internal-energy * Freq * TR) +
From .lib ½ * C * V^2 * Freq * TR
Dynamic Voltage Drop Problem Definition
On-chip power/ground network
i(t,V)
Vdd Pad
L R Cdev
is(t)
Rload
V(t)
Cpg
Cload
- Cload
Vss Pad
Switching instance Non-switching instance

Output: 1->1
 On-chip power/ground network  R,L,C mesh

 Switching instances  i(t,V) sources
 Non-switching instances  Effective decaps, ESR and leakage
Dynamic Voltage Drop on P/G Network
• PWL current for each instance

• Vdynamic waveform is computed at every node by transient simulation
V(t)
Vdd Pad
i(t,V) ESR
Cpg
Cdev Cload
Vss Pad
Non-switching instance
Switching instance
Output: 1->1

Difference Between Static and Dynamic
Static Dynamic
Switching instances will draw transient current (AC)

All instances will draw an average current (DC)
Non-switching instances will draw only leakage
Total Average demand will be much less than real peak

demand current for the chip Dynamic will see the real peak demand current
Portion of the demand current is supplied by

Demand current is completely supplied by battery decaps
(Intrinsic / Intentional / PG caps)
Instances will draw transient current only when it
Doesn’t matter when an instance switches switches
Instances will draw the current all the time Simultaneous switching causes huge peak current
demand
No drop across package due to Ldi/dt effects

Ldi/dt drop across package and die inductance
(Current is constant)

RedHawk in Design Flow
Early Analysis
Grid Quality
Pad placement
Floorplanning FAO Switch Placement
Chip Power Model
Package Selection
Qualitative Analysis
Power distribution quality
PG Weakness Checks
Placement/CTS FAO Clock buffer clustering
Simultaneous Switching
Decap placement
Signoff Verification
Static IR
Power EM
Routing Dynamic Drop
Low Power Signoff
Impact on Timing
Chip Power Model
RedHawk Static Analysis Flow
Data Preparation
Extracted Package Netlist Design Setup
Power Calculation FAO

Mesh Editing/Addition
Package DC Analysis & Via addition/Removal
Optimization Pad optimization
Power Grid Switch Addition/Removal
Extraction
Static Chip Power Model IR/EM Simulation
Result Exploration
Sentinel Platform RedHawk Platform

RedHawk Input Data Requirement
Library Data Design Data Redhawk Data
• LEF • DEF • GSR
• LIB • SPEF • Command File
• GDS • STA* • GSC
• APL* • VCD
• TECH* • Package
• Pad Files
* : These inputs are created using Apache utilities

Technology File Generation
Apache provides several utilities to convert various tech

file formats
• ircx2tech : for converting TSMC ircx file to apache

format
• rhtech : for converting STARRC-XT NXTGRD/ITF files to
apache format

What is Inside STA File ?
• Slew
– Required for Static (Power calculation uses Slew)
– Required for Dynamic (Current w/f is dependent on Slew)
• Timing Windows
– Not required for static
• Instance Frequency
– Required for static and dynamic
• Clock domain info
– Required for static and dynamic

STA File Generation
Verilog/DEF Spef SDC LIB
ATE
STA File

RedHawk Modeling for Standard Cells
Standard cell Modeling
Spice Netlist Spice Model
APL
APL Current APL CDEV
450
400
VDD
350
300
ESR
Current
250
200
150 I-leak
100
50 CDEV
0
0 50 100 150 200 250 300
Time
VSS

RedHawk Modeling for Memories and IPs
Memory/Hard-IP Physical Modeling
GDS LEF Layer map
GDS2DEF
LEF DEF

Current/Cap Modeling for Memories and IPs
Current Modeling From Simulation W/f Cap Modeling Through ACE
Simulation Waveform Data

Spice Netlist Spice Model
(FSDB,PWL etc)
Sim2iprof ACE
APL Current APL CDEV
Current/CAP Modeling Through AVM
APL Current
Synopsys LIB/ Datasheet
Parameters
AVM
APL CDEV

Specifying Voltage Source Locations
Option-1
Redhawk automatically identifies the voltage source locations
from PINS section in DEF
Option-2
User can specify the master cell name for P/G pads through a file
Option-3
User can specify the P/G pad instance names through a file
Option-4
User can specify the P/G pad (x,y) locations through a file
See manual for details

Specifying Voltage Sources (Cont’d)
*PCELL
DVDD12
DVSS
PASLZ55 VDD
PADLZ55 VSS
*PAD
VDD_PAD1
VSS_PAD45
PVDD1DGZ
17.5 242.0 METAL6 POWER
*PLOC
DVDD1 4905 878.85 METAL4 POWER
DVSS1 4880 938.85 METAL4 GROUND
DVDD2 4905 998.85 METAL4 POWER

GSR (Global System Requirement) File
TECH_FILE <path to TECH File> DEF_FILES {

<Path to the DEF files>
LIB_FILES { }
<Path to LIB Files>
} STA_FILE {
<Path to timing file>
LEF_FILES { }
<Path to LEF files>
} CELL_RC_FILE {
<Path to Spef file>
GDS_CELLS { }
<Path to Gds2def models>
} VCD_FILE {
Hierarchical IP <VCD file details>
APL_FILES { }
models & Transistor
<Path to APL models>
Level Totem views
} (Optional) PAD_FILES {
<Path to Pad File>
CMM_CELLS { }
<Path to CMM models>
}
Library File Pointers Design Data Pointers

Commonly Used GSR Keywords
• BLOCK_POWER_FOR_SCALING (BPFS)
– Used for defining power target values
– RH will scale the toggle rate to meet user specified power target
– Scaling can be done at Full-chip/Block level. It can be master cell
specific too
– Can define pin specific power for multi-vdd cells
BLOCK_POWER_FOR_SCALING {
FULLCHIP FULLCHIP 1.2
FULLCHIP BLOCK_INST_NAME 0.5
CELLTYPE MEM_1024x768 0.1
FULLCHIP INST1 0.005 VDD1

FULLCHIP INST1 0.006 VDD2
}

• INSTANCE_POWER_FILE (IPF)
– Can be used to import instance power numbers from 3rd
party tools
– RH will assign the power number from this file as it is
– Instances missing in this file will get zero power
– Supports pin specific
INSTANCE_POWER_FILE design.ipf
#Format of design.ipf
Inst1/inst_100 0.0123
Inst1/inst_102 0.0123
Inst1/inst_104 0.0123
Inst1/inst_105 0.0123
Inst1/inst_106 0.0123
Inst1/inst_107 0.0123
Inst1/inst_108 0.0123
Inst1/inst_108 0.0123
Inst1/inst_109 0.0123 VDD

FREQUENCY 100e6 Dominant Frequency of the design
TOGGLE_RATE 0.15 1.5
INSTNACE_TOGGLE_RATE {
instance_name toggle_rate
} Global Toggle Rate Used
(BPFS will override this)
BLOCK_TOGGLE_RATE {
block_name toggle_rate
}
INPUT_TRANSITION 100e-12
Default Slew value used
(Used for instances missing in STA File)

TEMPERATURE 125
To specify the P/G Extraction Temperature
VDD_NETS {
VDD 1.2
inst_129973/VDD_INT 1.2
}
GND_NETS {
VSS 0 Nets being analyzed and Ideal Voltage
}
IGNORE_TECH_ERROR 1
IGNORE_DEF_ERROR 1
IGNORE_UNDEFINED_LAYER 1
IGNORE_LEF_DEF_MISMATCH 1 Option to proceed even with Errors

GSR File Overview
VDD_NETS {
VDD 1.0
}
GND_NETS { Key Redhawk Settings

VSS 0 Like analysis voltage , Temperature etc
}
FREQ 266e6
INPUT_TRANSITION 100e-13
TEMPERATURE 125
DYNAMIC_SIMULATION_TIME 10e-9
DYNAMIC SIMULATION SETTINGS
DYNAMIC_PRESIM_TIME -1
DYNAMIC_TIME_STEP 10e-12
BLOCK_POWER_FOR_SCALING {
FULLCHIP GENERIC 1.2
}
You can use Apache utility rh_setup.pl to generate
TOGGLE_RATE 0.2 the command file/GSR

Command File Overview
# Import data # Import data

import gsr GENERIC.gsr import gsr GENERIC.gsr
setup design setup design
# Calculate power # Calculate power

perform pwrcalc perform pwrcalc
# Power/Ground grid extraction # Power/Ground grid extraction

perform extraction -power –ground perform extraction -power –ground -c
# Static IR analysis # Dynamic IR analysis

perform analysis –static perform analysis –dynamic
# Exporting the DB for future use # Exporting the DB for future use
export db static.db export db dynamic.db
Static command file Dynamic command file

RedHawk Low Power Analysis

Controlling Leakage Power
• Next generation chips in 65nm

and 45nm
• > 50 % of total power goes to
leakage
• Cell phone battery life
• Standby power cannot exceed 5%
of full operational power
• Product’s competitiveness
depends on its ability to control Kim et al, "Leakage Current: Moore's Law Meets Static Power,"
IEEE Transactions on Computers, Vol. 36, No. 12, December
leakage 2003, pp. 68-77

Leakage Power Saving Using MTCMOS Switches
• Can turn off the power for Un-gated domain
inactive blocks using

switches
EN Switch
• Switches are made with High
Vt transistors for minimal Internal Power Domain (Switched domain)
sub-threshold leakage
Low Power Block

Different Switch Architectures
Power Gating Switch Models
Header Switches (PMOS) Footer Switches (NMOS)

Vdd Vdd
CTL
Block
Block
CTL
Vss Vss

Challenges in Power Gated Designs
• High surge of current to charge/

discharge the internal capacitors
during powerup
• This can cause huge voltage drop

on neighboring “always on” blocks
• Peak current flowing through the Vdd of Always-On block

switches should be within limits
Total chip current
Vdd of Power-up block
Time

Challenges in Power Gated Designs (Cont’d)
• Daisy chain structure for switch enable helps reducing rush current
Constant Power Domain
Simultaneously
Turn-On All Switches
Switch
Switch
Switch
Staged Switch
EN Delay Delay Turn-On
Internal Power Domain

25ps
• Rush current can be reduced by 50ps
increasing the delay between

switches
75ps
• Increasing the delay will also

cause an increase in block
wake-up time 75ps

• Rush current can be reduced by

reducing the number of switches
• But this will increase the current

flow through individual switches
• Also increases the ON state power

grid resistance
• Increases the wake-up time

• High rush current can

cause oscillations in the
power ground n/w due to
fast turn ON (L di/dt)

• Alternate switch architecture to • Switch placement can be
reduce rush current and ON state improved to optimize the ON
voltage drop state drop
VDD
EN1
EN2
Small Big
VDD_INT Switch
Switch
More switches can be used
in critical areas to reduce the drop
Small switch is used to charge the internal
nodes; Big switch will reduce the ON state
resistance

• If VDD2 ramps up faster than

VDD1 VDD2
VDD1, OUT0 can stay at a level
above threshold voltage for more
time.
OUT0
IN0 OUT
• There could be high crowbar

current in the receiver cell
VSS VSS
• More significant when wakeup
time is more
• Need to analyze the voltage

differential analysis on driver
receiver pair

RedHawk–LP Features
ON state Analysis
Static IR drop analysis
Dynamic analysis
OFF state Analysis Switch size and architecture

Leakage Number of switches
Placement of switches
Powerup Analysis Interval between switches
Rush current Switch turn ON sequence
Noise coupling
Wake-up time
Crowbar current
P/G n/w oscillations

RedHawk – LP
STA
slew/clocks/timing APLPWCAP
Apache tech lef def/gds lib
Spef/Dspf
import gsr GENERIC.gsr
setup design Optional
setup analysis_mode lowpower

User control file (GSR): perform pwrcalc
VDD_NETS {
VDD 1.2 perform extraction -power –ground -c
inst_129973/VDD_INT 1.2
}
SWITCH_MODEL_FILE apache.sw perform analysis –lowpower
APL_FILES { explore design
cell.current current
cell.cdev cap
cell.pwcdev pwcap
} Reports Maps
GSC_FILE design.gsc
* Required only for Rampup analysis

Additional Data Requirements:
APL PWCAP Data
• Power gates are non-linear elements in different modes
• Transition from “off” to “on” state requires charge transfer to/from design
• Design capacitance varies as function of node voltages
• Long simulation times to capture entire power-up process
• Required only for Powerup analysis; Not required for ON state analysis
Non-linear capacitor modeling
r7_ht_and2tc: cap modeling for ramp-up

Actual 3.40E-03
Circuit 3.20E-03
3.00E-03
2.80E-03
2.60E-03
RedHawk 2.40E-03
Equivalent 2.20E-03
Circuit 2.00E-03
0 0.5 1

STA File with Switch Turn ON time
• STA File should contain turn ON time for the switch enable
pins
• Required only for Rampup analysis; Not required for ON
state analysis
set ADS_CELLS_NEED_INPUT_TW { switch }

getSTA * -o design.timing

Switch Model File
• Need to run APL characterization for

switches to create the electrical model
• Captures the switch characteristics for

different operating modes
• Required for both Rampup and ON

state analysis
Review the switch model file at :

design_data/apl/switch.model

GSC File
• Global switching constraint (GSC) file
to specify the operating mode for the
switch
– Specify the state of BOTH switch instance and
power-gated block/instance:
• [gated_block] POWERUP
• [switch_instance] POWERUP
– Or specify domain_name to include everything
in that domain
• * [domain_name] POWERUP
• Can perform analysis for multiple

scenarios using “import gsc”
command
• GSC file is optional for ON state
analysis. By default, all switches are
assumed to be in ON state

RedHawk VCD based run

VCD Based Analysis Introduction
• RH supports two type of simulation outputs

– VCD (Value change dump) File
– FSDB (Fast signal database)
• VCD/FSDB can be generated at two stages:

– RTL Level : contains only Flop and primary I/O activity
– Gate Level : contains activity for all nets in the design
• RH supports both gate level and RTL level VCD/FSDB

Type of VCD/FSDB
• True-time
– VCD has SDF back-annotated.
– Switching events in VCD will indicate the real time at
which instance switches
• Non-True-time
– VCD is NOT SDF back-annotated
– Simulator assumed unit-gate-delays for generating this
VCD
– RedHawk will use STA_FILE to derive the switching
time
– VCD is used only for Switching scenario information

VCD Based Dynamic Analysis Flow
Cycle selection
Setup
Scans through the entire VCD and selects
cycles which are critical for analysis
Power calculation
and
Cycle Selection
Extraction
Dynamic
Simulation

GSR Settings Requirements
FRONT_PATH indicates the test-bench

top hierarchy used in simulation
GSR: This path needs to be removed with

SUBSTITUTE_PATH (“”) in order to match VCD net
VCD_FILE { names with DEF net names
GENERIC GENERIC.vcd
FILE_TYPE VCD
FRONT_PATH "GENERIC/"
SUBSTITUTE_PATH ""
SELECT RANGE <start t> <end t>
TRUE_TIME 1
}

Command File Settings
TCL:
setup design
perform pwrcalc
perform extraction –power –ground -c
setup package
perform analysis -vcd
VCD Based Dynamic Simulation

Cycle Selection Outputs
• Cycle-by-cycle power numbers
adsRpt/worst_power_cycle.rpt
• Explorer showing Power versus Cycle Graph
Data Integrity ->

VCD Check ->
VCD Cycle Power Profile

GSR Setting Required for RTL VCD
GSR:
VCD_FILE { Indicates that file is RTL VCD
GENERIC GENERIC.vcd
FILE_TYPE RTL_VCD
FRONT_PATH "GENERIC/"
SUBSTITUTE_PATH ""
FRAME_SIZE 2500
TRUE_TIME 1
MAPPING <filename>
}

Package Netlist Handling In Redhawk

Package Impact on Dynamic Voltage Drop
Inclusion of package effects

– Ldi/dt noise
– Choice of package capacitance
– Current limiting effect
Without Package Model
With Package Model

Different methods for annotating Package
• Using lumped values through command file

– Setup package/wirebond/pad constraints
• Using package spice netlist

– In the form of RLCK models
– In the form of S-Parameter form

Including Package in RedHawk Analysis
Package Layout Package Netlist

RLCK Spice / S-Param Model
SENTINEL
Ploc File Package Compiler
Including Package in Dynamic Simulation is very

important to capture the L*di/dt drop across the
package
REDHAWK

GSR Settings Requirements
DYNAMIC_SIMULATION_TIME 5e-9
DYNAMIC_TIME_STEP 10e-12 Sufficient presim to charge

internal nodes
DYNAMIC_PRESIM_TIME 20e-9
PAD_FILES {
GENERIC.ploc Ploc files with package hooked up
}
PACKAGE_SPICE_SUBCKT GENERIC.package.spi Wrapped Package spice netlist

Lunch Break

Lab Instructions
• Download the testcase
̵ ftp ftp.apache-da.com
̵ username: anonymous
̵ password: <your email address>
̵ ftp> bin
̵ ftp> cd outgoing
̵ ftp> get RH_Lite_Training.tar.gz
• Un-tar the bundle
̵ gtar -zxvf RH_Lite_Training.tar.gz
• cd dynamic
̵ Review command file and GSR
̵ Review Design Data (design_data dir)
• setenv APACHEROOT <APACHE install path>
• setenv PATH $APACHEROOT/bin:$PATH
• redhawk –f run_dynamic.tcl

RedHawk GUI Overview
Pull-down Menu
Navigation Menu
Layer/Legend
Selection
Layout Window Maps
Query/Search
Message Window
Bird’s eye view
TCL Console
GUI Basic Operations
Viewing Selective Nets Viewing Selective Layers
Viewing P/G Pads

Search / Query Options
Property Query
clear selection
zoom to an instance or location
Fit Screen

Viewing Different Maps
Map Shortcuts
Complete List of Maps Controlling Map Color Legends

Viewing Different GUI Reports
Log Message Summary Reports
Various List of Violations

Viewing Different Waveforms
Current w/f Voltage w/f
TCL command:
plot voltage <options>
TCL command:
plot current <options>

Minimum Resistance Path Tracing
• Traces the minimum resistance path for an instance from the electrically nearest
voltage source point
• Can be invoked using Tcl Command : ‘perform min_res_path’
̵ perform min_res_path -inst <instName >: Traces the connectivity for the instance
for all P/G pins from electrically nearest voltage source
• Can also be invoked from Instance Property box window
White: VSS Path Trace

Yellow: VDD Path Trace

Minimum Resistance Path Tracing
• min_res_path also generates a resistance report which will give the break-up of
resistance and voltage drop across different wire/via segments in the path
• By default, this command generates the output in adsRpt/res_path.rpt file. User can
control this using “-o” switch.
adsRpt/res_path.rpt file

Important Text Reports
File Description
adsRpt/redhawk.log Redhawk log file
adsRpt/power_summary.rpt Power Summary Report
adsRpt/<design>.power.rpt Detailed Power Report
adsRpt/Static/<design>.inst.worst Instance Static IR Report
adsRpt/Dynamic/<design>.dvd Instance DVD Report
adsRpt/Static/<design>.em.worst Instance EM Report

Using TCL Commands in RedHawk

Commonly used TCL Commands
Command Description
import db/export db For importing and exporting the database
help To get help on any TCL command
print type Prints the cell type wise switching statistics
plot switching Plots switching histogram
plot analysis Plots analysis histograms
gsr get / gsr set Queries / Assigns a GSR keyword parameter
(supported only for selected keywords)
condition set –time/-xy/-type Filters the analysis results to specified time/bbox or cell
type

GUI Display Related Commands
Command Summary
select add $inst Highlights a particular instance in GUI
select addfile $file Highlights all instances listed in the input file
select clearall Clears all GUI highlights
marker add –position $x $y Adds a marker sign (+) in the specified location
marker delete -all Deletes all marker highlights in the GUI
plot line –position $x1 $y1 $x2 $y2 Plots a line in GUI
config viewlayer … Turn ON/Off various layers in GUI
config viewnet … Turn ON/Off various nets in GUI
config viewpad … Turn ON/Off pads in GUI
dump gif Saves a GIF image of GUI display
zoom rect $x1 $y1 $x2 $y2 Zoom in-to the specified rectangle
zoom get Get the current zoom coordinates

Instance Attribute Query Commands
Command Switch
-master
-freq
-power
-peak_current
-resistance
Returns Various properties
get inst $inst -decap of an instance
-switching_status
-bbox
-location
-orientation
-voltage
Loops through all instances in the
get inst * -glob
design

Cell Attribute Query Commands
Command Switch
-type
-height
get cell $cell -width of a master cell
-pins
-pgarcs
Loops through all master cells in
get cell * -glob
the library

Net Attribute Query Commands
Command Switch
-ideal_voltage
get net $net -worst_drop of a net
-worst_em
Loops through all nets in the
get net * -glob
design

Pad Attribute Query Commands
Command Switch
-info
-voltage
-current Returns Various properties
get pad $pad of a pad
-layer
-location
-net
get pad * -glob Loops through all pads in the design

Switch Attribute Query Commands
Command Switch
-int_voltage
-voltage_drop Returns Various properties
of switch instances
-current
get switch $switch
-net_pair
-turn_on_time
-status

Design Attribute Query Commands
Command Switch
-bbox
-worst_inst_drop of the design
-worst_inst
get design
-worst_wire_drop
-worst_em
-stats

Result Analysis and Root Cause identification using
RedHawk Explorer

RedHawk Explorer
• Explorer is a new tool which helps in locating, isolating,

understanding and resolving design/data issues causing
hot-spots
– Root cause Identification for DVD/IR/EM/ALP issues
– Data integrity checks on input library/design data and
user settings
– Local and global design weakness analysis
– Analysis result summary generation
• Tightly integrated with Redhawk GUI – Provides easy
cross-probing capabilities
• Available from RH V10.1 as productized addon

RedHawk Explorer Goals
Summary Data Integrity Design Weakness Hot Spots
• Design Summary • Library Data • VRM/Package • Pass/Fail checks
• Results Summary • Design Data • PDN Connectivity • Root cause identification
• Run Summary • RedHawk Data • Current Distribution
Identifies Regions Identifies Regions Identifies the Design/Data

Provides High Level Quality Issue Causing the hot
Affected with Data Affected with Design
summary spot
quality Issues Quality Issues
Data Integrity checks Qualitative Analysis/Signoff Quantitative signoff

How do I run RedHawk Explorer ?
TCL Command: explore design

(can be executed at any stage after “setup design” )

Summary Section

Summary Section
Design Summary
Result Summary
Power Summary
Static IR
Power EM
Dynamic Voltage Drop
Low Power
Run Details
Summary Section
Power Summary Break-up
Various Maps
Run Details

Summary Section
Voltage Drop Break up Tells what % of instances are

switching in dynamic simulation
Demand Current and Battery current

Difference indicates decap current contribution Shows Analysis Histograms

Data Integrity Analysis

Data Integrity Check Summary
Library Data
APL Current Check
APL Cap Check
APL Pwcap Check
LIB Check
LEF Check
CMM Check
Gds2def Check
Design Data
DEF Check
SPEF Check
IPF Check
RED cross indicates that there is a problem STA Check
with this input
Gate VCD Check
RTL VCD Check
RedHawk Data
GSR & TCL
Package Settings
 Design specific data integrity check PAD_FILES
 Helps to identify and understand impact of missing data GSC_FILE

 Breaks design into regions and presents missing data for each region Log Summary
ERROR Check
WARNING Check
Data Integrity Check Example
APL Cap Check
APL Coverage Details
Highlights Regions with violations
Provides a sorted list of cells based on

number of instances
Provides cell-type wise classification

Related Output Reports Section
Provides pointers to relevant reports in adsRpt
• Presents relevant files in hyperlinked manner

• Describes and provides their content

DEF Check Example : Short Debug
Direct zoom into RH GUI by clicking on the image
Highlights Regions with shorts

(User can click and zoom into RH) Exact short location highlighted with marker

DEF Check Example : Short Debug
RH will also zoom into the rectangle with

violations and add marker for all violations
RH also pops up stepper window with list of

violations within the zoomed rectangle

Layer/Domain Wise Reporting in DEF Check
• RHE reports layer/domain wise breakup of shorts, wire/via/instance

unconnects and missing vias checks

GSR / TCL Setting Checks
Common mistakes made in GSR/TCL

are identified here

Design Weakness Analysis

Overall Design Weakness Exploration
VRM/Package Related
Pad Placement Quality Check
Package Drop Contribution
PDN Related
PG Resistance Distribution
PG Resistance Balancing
Switch Placement Quality Check
Decap Distribution Check
Current Related
Power Distribution Quality
Clock Buffer Clustering
Peak Current Check
Simultaneous Switching Check

Pad Current Check Example
Divide the design into partitions
Find the max pad current in each partition

(Domain specific)
Computes the average pad current across the chip in each domain
(Total Pad current / Number of pads)
Checks whether any pad drives more than 5X the average pad current across
the chip
Reports violations
Review pads with high (EM, IR) and low (over-design, connectivity issue)
currents

Design Weakness Analysis Example
PG Resistance Distribution Check
Indicates that PG Resistance in this region is

2.94 X higher than the average PG Resistance
obtained from all regions
Histogram showing PG Resistance distribution in different regions
Changing the constraints on-the-fly through

cross-probing menu

Changing the Constraints
Using constraint editor

(Before running RHE)
Using RHE GUI

(After running RHE)
Using Text Editor

(Before running RHE)
• vi adsRHE/rhe_threshold.rpt
• Edit the constraints you want
• explore design –constraint_file <new_thresh_file>

Cross-probing violations in RedHawk GUI
User can click on zoom button or

directly click on the image
When you click on the image, RH/RHE does 3 things:

• Zooms into the violating regions
• Highlights the worst instance within the regions
• Update the map with some relevant views
• Example, PG resistance map will display SPT for the worst instance
Related Maps Section
Design Weakness -> Power Distribution Quality -> Related Maps
High Load
High Freq
High Power
High Toggle
Rate
Clock
Clustering
Related maps section helps

identifying the exact cause for a
weakness
Getting Help on a Specific Item
Hot Spot Analysis
Power Noise
Root Cause Identification
Root Cause for DVD/IR/EM Issues
30% due to
less pads
15% due to 25% due to

clock High DvD simultaneous
clustering switching
40+ reasons
why you have
30
a hot-spot! % due to less
decaps
Hot Spot Analysis
DVD Hotspots highlighted here
Various signoff checks
Hot Spot Analysis
Driven by Pass/Fail Criteria
Automate Hot-spot issue

isolation
Hot Spot Analysis
Checking Hot-spot #1
Detailed analysis inside the region
Instance level histogram

within hot-spot 1
Indicates that this hot-spot region has

power issue
Region Level Issues
Global Issues
Design Weakness Ranking
This hot-spot region ranks 7 among all regions in the design based on Total Clock Power
(Rank-1 indicates the weakest region)
Data Integrity Checking
Region Level Data Integrity Analysis
SPEF coverage in this region is only 93 %
Hot Spot Analysis at Instance Level
Detailed analysis at instance level
Hot Spot Analysis
Instance Level Debug
This hot instance has high

peak current
Missing Spef
Load is high causing high
current !!
Shortest Path Tracing
Highlights Shortest Resistance

Path to P/G Pads
Equivalent Tcl Command:

User can directly zoom into the bottleneck segments
perform min_res_path –o res_path.rpt
Explorer Command Line Options and
Log Details
Command Description
explore design Runs Explorer and Pops up GUI
explore design -view Pops up Explorer GUI
explore design -off Closes Explorer GUI
explore design –constraint_file <cons_file> Runs Explorer with a user specified constraint file
Log File Description

adsRHE/adsRHE.log Central summary Log
adsRHE/adsDWE/adsDWE.log Design Weakness Analysis Log
adsRHE/adsDIE/adsDIE.log Data Integrity Analysis Log
adsRHE/adsHSE/adsHSE.log Hot Spot Analysis Log
Tea Break
REDHAWK-LP LAB
RedHawk – LP Lab

setup design
• Mixed Mode Analysis
– cd low_power # Calculate power
perform pwrcalc
– redhawk –f run_low_power.tcl
setup analysis_mode lowpower
# Power grid extraction

perform extraction -power -ground -c
• Review the GSR and Command
# Lumped resistance(in Ohms) for package,wirebond
File # and pads
# Default values are all 0, i.e no off-chip impact
– Virtual domain included in GSR setup package -power -r 0.005 -l 2.5 -c 5
setup package -ground -r 0.005 -l 2.5 -c 5
– Switch model file setup wirebond -power -r 0.01 -l 2.2 -c 1.42
-ground -r 0.05 -l 1.7 -c 0.2
– GSC file setup pad -power -r 0.001
setup pad -ground -r 0.001
– STA file with switch timings #
perform analysis –lowpower
– setup analysis_mode lowpower explore design
Command File
GSR Review
Switch Model
GSC File
Switch Lef File
STA file with switch timings
APL Pwcap files
More Simulation time

Relaxed time step
Mixed Mode Analysis
GSC File Review

Powerup
100% switches in Powerup
RedHawk – LP Lab
• Voltage waveform for powerup

instance Vdd
– plot voltage -name
inst_129973/inst_362960
-sv
Vss
• Supply current waveform

– plot current -net -power
–pad –sv
– Shows higher battery current
during powerup
RedHawk – LP Lab (Cont’d)
• Voltage waveform for powerup

instance Vdd
– plot voltage -name
inst_129973/inst_362960 -sv
– Rampup between 3ns and 5ns
• Voltage w/f for Always ON instance

– plot voltage –name
inst_130017 -sv
– Shows higher drop during Powerup
• Voltage Domain Current W/f
– Represents the total current through the switches
xgraph adsRpt/Dynamic/virtual_domain_total_i.rpt
• Rampup Movie
– Results -> Movie -> Make
Low Power Support in Explorer
• Analysis Summary for Low Power

• Data integrity Checks for LP analysis
• Signoff Analysis Support
– Peak current
– Wake-up time
– Differential voltage check
– Noise coupling check
– Switch Id-sat check
– Off state Leakage and Voltage check
• Rampup switch turn ON Movie Generation
View the slides in slide-show mode(shift+F5)
Low Power Summary
Switch Turn ON Movie
ALP Related Data Integrity Check
ALP Hotspots Section
Peak Rampup Current & Rampup Time Checks
Battery Current & Demand Current Checks
What is Differential Voltage Check ?
Differential Voltage Analysis
Pass/Fail Criteria Check
List of violations
Violations highlighted in GUI
Cross-Probing Violations
Driver and receiver instances are highlighted using different

colors . Driver uses Green color and Receiver uses White
color. You can choose the color using Cross-probing options.
Adjusting Differential Voltage Thresholds
User can control the diff voltage limit and

number of violations to display
Differential voltage histogram
Differential Voltage Violation Details
Receiver Turning ON much before Driver
Receiver will be seeing the gate voltage slowly ramping up.

Creates high short circuit current
Differential Voltage Violation Report
Noise Coupling Check
Noise Coupling Analysis : Summary
Noise Coupling Analysis Details
Switch Id-sat Check
Highlights switch instances in the design which are driven to their saturation region
due to excessive current flow during powerup
Switch Off State Check
This check analyzes the effectiveness of power gating in the design in terms of reducing the leakage power
Low Power : Related Maps & Movies
In the movie, you can verify that Receiver Turns on

much before Driver
RedHawk – LP Lab Summary
• Used RedHawk low-power analysis for

– Analyzing dynamic voltage drop in ON state
– Determining the leakage current in “sleep mode”
– Finding P/G rail voltages after “power up” and analyzing the wakeup
time
– Analyzing the effect of “rush current” on the design with the movie
mode
– Experimenting:
• Switch turn-on time
• Number of switches
– Performing mixed mode Rampup analysis
ALP Movie Support For Mother-Daughter
Switches
• If the design contains mother-daughter switches,

RHE can now generate the switch turn on movie for
both the mother switch chain and daughter switch
chain.
• Mother switch chain movie will be
displayed with a different color
• In order to enable this feature, turn on
the following keyword in RedHawk
before executing “explore design”
̵ set rhe_rampup_enable_md_movie 1
Changing the Low Power Constraints
Explorer -> Generate ->

Edit Constraints
Chip Power Model Generation
CPM Technology
• Full chip frequency domain simulation and model order

reduction
• Cdie/Rdie for each domain
• Icc(t) for every domain and pin
– Full chip current signature simulation
– VCD based and Vectorless switching scenario
• Interactive cross-probing of nodes within CPM
Chip Power Model (CPM)
Spice compatible accurate model for the DIE which can be used in
Package/Board level analysis
CPM can be created using “perform pwrmodel” command in the same Dynamic simulation setup
Cdie
I
Rdie
REDHAWK SENTINEL
Chip Power Model
AC, DC, Transient

Simulation for
Chip-Package-System
Chip Power Modeling Flow
• No package parasitics are used in the

Setup Design simulation ( Chip power model is package
independent)
Power Calculation • No separate dynamic simulation required
• CPM internally performs dynamic simulation

PG Extraction for capturing the current signature
• CPM dynamic simulation run time might be

higher than regular dynamic simulation time
CPM Creation
Command File
# Import data
setup design
# Calculate power
Exactly same inputs and setup used
perform pwrcalc in dynamic simulation
# Power grid extraction

perform extraction -power -ground -c
# Package, wirebond, pad setup

setup pad
setup package
setup wirebond CPM Generation Command
# CPM Creation
perform pwrmodel –nx 5 –ny 5 –o design.cpm
Apache Resource Center
 Apache Online Customer Support Center
– http://support.apache-da.com
– Email: support@apache-da.com
Thank You!!!

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Apache Design Solutions

1 © 2012 ANSYS, Inc. March 8, 2017 Apache

• Voltage Drop Analysis Theory

• RedHawk Static and Dynamic Analysis Flow

• RedHawk Low Power Flow

• Using Tcl Commands in RedHawk

• VCD Handling in RedHawk

• Package Netlist Handling

• Chip Power Model Generation

2 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

NX SEM PsiWinder ALP PathFinder

 Grid Weakness  Average  Clock jitter  Rush-current  Rule based

4 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

Vdd Pad Ipad

 On-chip power/ground network  mesh of resistors

5 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

• Average current is calculated for each instance

6 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

Leakage Internal Switching Average

Switching Power = ½ * Cap * V^2 * Freq * TR

From Timing File

Internal Power = Internal Energy(in .lib) * Freq * TR

Switching instance Non-switching instance

 On-chip power/ground network  R,L,C mesh

• PWL current for each instance

9 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

Switching instances will draw transient current (AC)

Total Average demand will be much less than real peak

Portion of the demand current is supplied by

No drop across package due to Ldi/dt effects

10 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

Extracted Package Netlist Design Setup

Power Calculation FAO

Static Chip Power Model IR/EM Simulation

Sentinel Platform RedHawk Platform

Library Data Design Data Redhawk Data

• LEF • DEF • GSR

• LIB • SPEF • Command File

• GDS • STA* • GSC

* : These inputs are created using Apache utilities

13 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

Apache provides several utilities to convert various tech

• ircx2tech : for converting TSMC ircx file to apache

14 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

15 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

Verilog/DEF Spef SDC LIB

16 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

Spice Netlist Spice Model

APL Current APL CDEV

17 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

GDS LEF Layer map

18 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

Simulation Waveform Data

APL Current APL CDEV

Current/CAP Modeling Through AVM

19 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

See manual for details

21 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

TECH_FILE <path to TECH File> DEF_FILES {

Library File Pointers Design Data Pointers

22 © 2012 ANSYS, Inc. March 8, 2017 Apache Design, a subsidiary of ANSYS

FULLCHIP FULLCHIP 1.2