7.

Addressing Modes I

Data Formats: Registers

• The MFC5270 registers have 32 bits
• The data bus is 32 bits wide
• Instructions can operate on
• Bits, Bytes, Words & Long words
• Indicated by the .B, .W & .L extensions
• Organization of Data Formats in Registers:

2
 Data Formats: Memory
Data is stored using big-endian scheme
Operands are assumed to be aligned based on their size:
—16-bit operands aligned on 0-modulo-2 addresses
—32-bit operands aligned on 0-modulo-4 addresses
Operands can be misaligned; however, this leads to performance degradation 3

Byte Transfers

0x1230 Byte 1 Byte 2 Byte 3 Byte 4

0x1234
0x1238

31 15 7 0
Byte 1

move.b 0x1230,%d0

4
 Word Transfers

0x1230 Byte 1 Byte 2 Byte 3 Byte 4

0x1234
0x1238

31 15 7 0
Byte 1 Byte 2

move.w 0x1230,%d0

Longword Transfers

0x1230 Byte 1 Byte 2 Byte 3 Byte 4

0x1234
0x1238

31 15 7 0
Byte 1 Byte 2 Byte 3 Byte 4

move.l 0x1230,d0

6
 Instruction Format

An Instruction consists of
– operation code (which function to perform)
– location of every operand for the function
– extension word(s) with values of the operand(s)

Operation word (op code, modes, locations)

Extension word 1 (if any)
Extension word 2 (if any)

Effective Address
Operand location can be specified using
1. The register field within the instruction
2. The instruction’s effective address field
3. The instruction’s definition (implied specific register);
other fields within instruction specify whether the register
is an address or data register and how it should be used.

An instruction’s addressing mode specifies value of

an operand, a register that contains the operand, or
how to derive the effective address of an operand.
Each addressing mode has an assembler syntax.
8
 Addressing Modes
Refer to the way in which an operand address can
be specified. Addressing modes of MCF5271:
1 Data Register Direct
2 Address Register Direct
3 Address Register Indirect
4 Address Register Indirect with Postincrement
5 Address Register Indirect with Predecrement
6 Address Register Indirect with Displacement

7 AR Indirect with Scaled Index and 8-Bit Displacement

8 Program Counter Indirect with Displacement Mode
9 PC Indirect with Scaled Index and 8-Bit Displacement
10 Absolute Short
11 Absolute Long
12 Immediate
9

Assumptions for Examples

Assume that before each example program segment the
MCF5271 designated registers contain the following data:

D1 0x12345678
D2 0xFEDCBA98 0x000200 0x78 0x9A
A2 0x010000
A3 0x011000
0x00FFFE 0x11 0x22
and the contents of memory are: 0x010000 0x33 0x44
0x010002 0x55 0x66

0x011000 0x77 0x88

0x011002 0x99 0xAA

10
 Data Register Direct

Generation EA = Dn
Assembler Syntax Dn
EA Mode Field 000
EA Register Field Register number
Number of Extension Words 0

11

Data Register Direct

move.b %d1,%d2 After D1 0x12345678
D2 0xFEDCBA78

move.w %d1,%d2 After D1 0x12345678

D2 0xFEDC5678

move.l %d1,%d2 After D1 0x12345678

D2 0x12345678

Before D1 0x12345678
D2 0xFEDCBA98

12
 Address Register Direct

Generation EA = An
Assembler Syntax An
EA Mode Field 001
EA Register Field Register number
Number of Extension Words 0

13

ColdFire’s Address Bus

The ColdFire has a 32-bit PC
– Enabling the addressing of 232 byte locations (4GB)
Only 24 bits connected externally
– Bits A[23:0] connected: can access 224 (16MB) bytes

A31 … A24 A23 … A16 A15 … A8 A7 … A0

internal external

– Internal lines used to qualify the address generated by software

– Additional addressing space available through chip select (CS)
– Byte, Word and Longword access facilitated using byte select (BS)

BS3* BS2* BS1* BS0*

b31 b24 b23 b16 b15 b8 b7 b0
address
address + 4 14
Special Instructions for A Registers

• The ColdFire has special instructions to operate on

address registers
• Special Instructions
– movea, adda, suba (do not affect the CCR)
– cmpa (comparison operation - does affect the CCR)

• Cannot operate on a byte of an address register

– Only word and long word operations permitted

move.b %a0,%d1 is legal; but

movea.b %d0,%a1 is NOT

– Word operands are sign extended

15

Word Operations on Addr. Registers

• An address register holds a 32 bit address which
is a single entity
• All operations are on 32-bits
• For word operations the word (16-bits) is first
sign extended to longword (32-bits)
• Address space wraps-around (in both directions)

MOVEA.W #4,%A0 and MOVEA.L #4,%A0 give the same result

#4.W = 0x0004 is sign extended to 0x00000004

MOVEA.W #-4,%A0 and MOVEA.L #-4,%A0 give the same result

-4.W = 0xFFFC is sign extended to 0xFFFFFFFC
16
 Address Register Direct
movea.b %d1,%a3 illegal (invalid size)

movea.w %d1,%a3 After D1 0x12345678

A3 0x00005678

movea.l %d1,%a3 After D1 0x12345678

A3 0x12345678

Before D1 0x12345678
A3 0x00011000

17

Address Register Indirect

Generation EA = (An)
Assembler Syntax (An)
EA Mode Field 010
EA Register Field Register number
Number of Extension Words 0

18
 Address Register Indirect
A2 0x00010000

0x010000 0x33 0x44

0x010002 0x55 0x66

19

Address Register Indirect Examples

move.b (%a2),%d2 After D2 0xFEDCBA33

move.w (%a2),%d2 After D2 0xFEDC3344

move.l (%a2),%d2 After D2 0x33445566

Before D1 0x12345678
D2 0xFEDCBA98 0x010000 0x33 0x44
A2 0x00010000 0x010002 0x55 0x66
A3 0x00011000

20
Absolute Addressing: Short

Generation EA given
Assembler Syntax xxx.W
EA Mode Field 111
EA Register Field 000
Number of Extension Words 1

21

Absolute Addressing: Long

Generation EA given
Assembler Syntax xxx.L
EA Mode Field 111
EA Register Field 001
Number of Extension Words 2

22
 Absolute Addressing
The instruction uses the actual absolute address for
accessing data in memory
Absolute short: After 0x1000 0x12 0x34
move.l %d1, 0x1000 0x1002 0x56 0x78

Absolute long:
move.b %d1, 0x00010000 After 0x10000 0x78 0x44
0x10002 0x55 0x66

Before D1 0x12345678

23

0x00000000
Size of assembled instructions
0x00007FFF
move.b 0x7fff, %d0 ;2 words
0x00008000
move.b 0x00007fff,%d0 ;3 words

move.b 0x8000, %d0 ;2 words

(0x8000 becomes 0xffff8000)
0xFFFF8000
How do we get 0x8000 ???
0xFFFFFFFF move.b 0x00008000,%d0 ;3 words

Absolute Addressing Revisited

24
 Immediate Data

Generation Operator given

Assembler Syntax #<xxx>
EA Mode Field 111
EA Register Field 100
Number of Extension Words 1 or 2

25

Immediate Data

The data is a constant immediately provided by the instruction

Used to deal with constants: Before D2 0xFEDCBA98

move.l #0x1000,%d2 After D2 0x00001000

add.l #0x100200,%d2 After D2 0xFEDCBC98

Note: how is this different from

add.l 0x100200, %d2 ?

26
 10 words = 20 bytes 0x11000 0x12000
2010 = 1416 = 0x14

0x11012 0x12012

Example 1: Write program to move 10 consecutive words of

data starting at memory location 0x011000 to a consecutive
block of memory starting at memory location 0x012000. The
program should start at 0x010000.
27

Example 1: assembly lang. program

.section main
Start: movea.l #0x11000,%a0 * a0 points at start of block 1
movea.l #0x12000,%a1 * a1 points at start of block 2

move.l #10, %d0 * initialize counter in d0

Loop: move.w (%a0),(%a1) * move word -- block1 to block2

adda.l #2, %a0 * increment pointer 1
adda.l #2, %a1 * increment pointer 2

sub.l #1, %d0 * decrement counter

bne Loop * if counter not equal 0, loop
.end otherwise exit

28
 Example 1: pseudo-code

addr1 = 0x11000
addr2 = 0x12000
for(i = 0; i < 10; i++)
{
Read a word from addr1
Write the word to addr2

increment addr1
increment addr2
}

29

Example 1: control constructs

CODE BLOCK1
* Initialization statements

move.b #10, %d0 * initialize counter in d0

Loop:
CODE BLOCK2 * Loop internals

sub.l #1, %d0 * decrement counter

bne Loop * if counter not equal 0, loop
otherwise exit

30
 Example 1: fill in remaining code (1/2)
Start: movea.l #0x11000,%a0 * a0 points at start of block 1
movea.l #0x12000,%a1 * a1 points at start of block 2

move.b #10, %%d0 * initialize counter in d0

Loop:
CODE BLOCK2 * Loop internals

sub.l #1, %d0 * decrement counter

bne Loop * if counter not equal 0, loop
otherwise exit

31

Example 1: fill in remaining code (2/2)

Start: movea.l #0x11000,%a0 * a0 points at start of block 1
movea.l #0x12000,%a1 * a1 points at start of block 2

move.b #10, %d0 * initialize counter in d0

Loop: move.w (%a0),(%a1) * move word -- block1 to block2

adda.l #2, %a0 * increment pointer 1
adda.l #2, %a1 * increment pointer 2

sub.l #1, %d0 * decrement counter

bne Loop * if counter not equal 0, loop
otherwise exit

32
 Variable Length Operands Memory

23 0 PL N
P PU PM PL PM N+1
Example 2: Add two words
PU N+2
P and Q of 24 bits (3 bytes) Q QU QM QL QL N+3
and to store the result in R QM N+4
R RU RM RL
QL N+5
RL N+6
Note: For simplicity, we are using 3x8=24 bit
RM N+7
operands to illustrate the principle of multiple RU N+8
precision arithmetic. In reality, it might be 64 or
8-bits wide
128 bits.

• MFC5270 can perform arithmetic operations directly only on

longwords (32 bits)
• To operate on data of other lengths (e.g. 64, or 128 bits)
– Need special instructions to take into account the carry
33

Multiple Precision Arithmetic

• The X – bit and C – carry bit are set by arithmetic
operations
CCR X N Z V C
• Carry is changed by logical operations X is not
• The X bit is used by special instructions

ADDX %Dn,%Dm [ Dm ] ← [ Dm ] + [ Dn ] + X
SUBX %Dn,%Dm [ Dm ] ← [ Dm ] - [ Dn ] – X
NEGX %Dn [ Dn ] ← 0 - [ Dn ] – X
34
 35

Example 2: Extended Precision

Memory
.section ADD24BIT PL N
* This will add two 24 bit numbers in memory PM N+1
* and stores the result in memory PU N+2
start move.b PL, %d0 get lower byte of P QL N+3
add.b QL, %d0 add lower bytes QM N+4
move.b %d0, RL store lower byte result in RL QL N+5
RL N+6
move.b PM, %d0 get middle byte of P
RM N+7
move.b QM, %d1 get middle byte of Q RU N+8
addx.b %d0,%d1 add middle bytes with carry 8-bits wide

move.b %d1, RM store middle byte result in RM

move.b PU, %d0 get upper byte of P
move.b QU, %d1 get upper byte of Q
addx.b %d0,%d1 add upper bytes with carry
move.b %d1, RU store lower byte result in RU

Note: For simple illustration only – MFC5270 does NOT have byte sized arithmetic operators.

AR Indirect with Displacement

Generation EA = (An) + d16

Assembler Syntax (d16,An)
EA Mode Field 101
EA Register Field Register number
Number of Extension Words 1

36
 AR Indirect with Displacement
• The effective address of the operand is given by the contents
of an address register plus a displacement/ offset
• Syntax (d16,%An)
• The 16-bit offset d16∈ [-32768,+32767] is sign extended and
added to the address register
• Often used to access items in a table

A1 Memory
e.g. If [a1] = 0x1000 0x00001000 0x1000
move.w (0x10,%a1),%d0 0x1002
0x1004
[d0] ← [M(0x10+[a1])] Offset = 0x10 0x1006
0x1008
[d0] ← [M(0x1010)]
0x1010
37 16-bits wide

(An) with Displacement: Examples

Assume that table called “ASCII_NUM” holds ASCII codes for “0” to “9”
Example 3 - get the ASCII code for the number “5” into D0
Memory
movea.l #ASCII_NUM,%A0 ASCII_NUM 0x30 31
adda.l #5,%A0 0x32 33
0x34 35
move.b (%A0),%D0
0x36 37
0x38 39
Note: the content of A0 has been changed!
(16-bits wide)

Example 4 - same thing using AR indirect with displacement

movea.l #ASCII_NUM,%A0 ;start of table into A0

move.b 5(%A0),%D0 ;ASCII code for 5 into D0

Note: the content of A0 intact; saved one instruction (3 words)

38
 Instruction LEA
LEA - Load Effective Address
– calculates the effective address of an operand and loads it into
an address register
– operates on 32-bits and is thus an intrinsically longword op
– a facilitator for setting up address register pointers, one of the
most powerful instructions
Note: It’s the address, not
the contents of the location,
that is transferred!

LEA ASCII_NUM,%A0 [A0] ← ASCII_NUM

LEA 0x0010ffff,%A5 [A5] ← 0x0010ffff
C
O LEA (%A0),%A5 [A5] ← [A0]
M
P LEA 12(%A0),%A5 [A5] ← [A0] + 12
A
R LEA 10(%A0),%A0 [A0] ← [A0] + 10 (incr. A0 by 10)
E
MOVEA.L #0x0010ffff,%A5 [A5] ← 0x0010ffff

AR Indirect with postincrement

Generation EA = (An); An = An + size

Assembler Syntax (An)+
EA Mode Field 011
EA Register Field Register number
Number of Extension Words 0

40
 AR Indirect with postincrement
move.b (%a2)+,%d2 After D2 0xFEDCBA33
A2 0x00010001
move.w (%a2)+,%d2 After D2 0xFEDC3344
A2 0x00010002
move.l (%a2)+,%d2 After D2 0x33445566
A2 0x00010004

Same as register indirect, except the address register is

automatically incremented by the data size (in bytes) after it
is used to do the data operation specified in the instruction.

Before: 0x10000 0x33 0x44 D2 0xFEDCBA98

0x10002 0x55 0x66 A2 0x00010000
41

AR Indirect with predecrement

Generation An = An – size; EA = (An)

Assembler Syntax -(An)
EA Mode Field 100
EA Register Field Register number
Number of Extension Words 0

42
 AR Indirect with predecrement
move.b -(%a2),%d2 After D2 0xFEDCBA44
A2 0x0000FFFF
move.w -(%a2),%d2 After D2 0xFEDC3344
A2 0x0000FFFE
move.l -(%a2),%d2 After D2 0x11223344
A2 0x0000FFFC

Same as register indirect, except the address register is

automatically decremented by the data size (in bytes) before it
is used to do the data operation specified in the instruction.

Before: 0x0000FFFC 0x11 0x22 A2 0x00010000

0x0000FFFE 0x33 0x44 D2 0xFEDCBA98 43

10 words = 20 bytes 0x11000 0x12000

2010 = 1416 = 0x14

0x11012 0x12012

Example 5: Write program to move 10 consecutive words of

data starting at memory location 0x011000 to a consecutive
block of memory starting at memory location 0x012000, but
in reverse order.
44
 Example 5: assembly lang. program
MOVE.B #10,%D0 * Initialize counter for loop
MOVEA.L #$11000,%A0 * Initialize A0 with first mem location
MOVEA.L #$11114,%A1 * Initialize A1 with second mem location
LOOP MOVE.W (%A0)+,-(%A1)* Move data and in/decrement A0/A1
SUB.L #1,%D0 * Decrement counter
BNE LOOP * If D0 <> 0, go to label LOOP
TRAP #15 * Halt Simulator

* Code segment to move 10 words

* from (A0) to (A1) in reverse order

45

Memory Memory
ARRAY1 ARRAY2

ARRAY1+8 ARRAY2+8

+16 +16

16-bits wide 16-bits wide

Example 6: A Routine to add two arrays, ARRAY1 and ARRAY2

and leave the result in ARRAY2. Each array is comprised of
five 64-bit words; need to use extended precision arithmetic
using ADDX (add with extend).
46
 Example 6: assembly lang. program
move.b #5,%D0 ;set D0 up as a counter to count 5 elements
lea ARRAY1,%A0 ;set A0 up to point at ARRAY1
lea ARRAY2,%A1 ;set A1 up to point at ARRAY2
again move.l (%A0)+,%D1 ;move 32 most significant bits of ARRAY1 into D1
move.l (%A1)+,%D2 ;move 32 most significant bits of ARRAY2 into D2
move.l (%A0)+,%D3 ;move 32 least significant bits of ARRAY1 into D3
move.l (%A1)+,%D4 ;move 32 least significant bits ARRAY2 into D4
add.l %D3,%D4 ;add least significant bits bits leaving result in D4
addx.l %D1,%D2 ;add most significant 32 bits with extend (X) bit

move.l %D4,-(%A1) ;store 32 least significant bits in ARRAY2

move.l %D2,-(%A1) ;store 32 most significant bits in ARRAY2
adda.l #8,%A1 ;adjust A1 to point at the next 64 bit word
subq.l ;decrement array element counter
bne again ;if counter not equal 0 go back and do again
… ;else exit (continue with the rest of the program)
47