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Chapter 1
Introduction to Memories
Jin-Fu Li
Advanced Reliable Systems (ARES) Lab.
Dept. of Electrical Engineering
N ti
National l Central
C t lU University
i it
Jhongli, Taiwan
Outline
20%
52%
16% 71%
83%
90% 94%
16%
64%
13%
32% 9%
6% 4%
16% 8% 4% 2%
99 02 05* 08* 11* 14*
*Foreast Source: SIA, ITRS, 2000
National Central University Jin-Fu Li 4
Embedded Memory – Advantages
• Area
− Embedding multiple memories on a single SOC reduces
the
h amount off silicon
ili used
d
• Performance
− Embedding faster, wider memories and moving them
closer to processor can increase system performance
substantiallyy
• Power
− Embedded memories eliminate the need to drive off
off-chip
chip
capacitance between the stand-alone memories and other
system chips
• Design reuse
− By reusing embedded memories, system designers can
significantly reduce develop time and cost
National Central University Jin-Fu Li 5
Embedded Memory – Quality
• During manufacture
− Yield
− Exponential yield model
− Y = e− , where A and D denote the area and
AD
• During
D i use
− Soft error rate
• ECC
− Detect/repair defects in individual words
− 25-30% area overhead
∗ Ex:
E 6 extra bits
bi ffor single
i l bit
bi correction
i ini 32 bi
bit words
d
− Latency penalty
∗ At least one clock cycle
y latency
yppenalty
y
Logic
g Tester .Test the remaining
non-memory components
.Test Built-In Self-Test (BIST)
Read/Write Memory or
Random Access Memory (RAM) Read Only Memory (ROM)
column decoder
k
n-bit address column mux,
m-bit data I/Os sense amp
amp,
write buffers
National Central University Jin-Fu Li 11
1-D Memory Architecture
S0 S0
Word0 Word0
S1 S1
Word1 Word1
S2 S2
Word2 Word2
A0
S3 S3
Decoder
A1
Ak-1
m bit
m-bit m-bit
m bit
Input/Output Input/Output
A0
ecoder
A1
Row De
Ak-1
Sn-1
Wordni-1
A0
Aj-1 Column Decoder
Sense Amplifier
Read/Write Circuit
m-bit Input/Output
National Central University Jin-Fu Li 13
3-D Memory Architecture
Row
Column
ock
Blo
Input/Output
Address der
ow Decod
M
Memory Cell
C ll
Ro
Column decoder
D t I/Os
Data I/O
RAM Cell
n-1:k
Sense Amp
Amp, Column Write
k-1:0 Mux, Write Buffers Clocks
bit - bit
4-T SRAM cell
word line
bit - bit
bit bit
bit
WL=1 WL=0
on + off +
+ Cs Vs Cs Vs
Input Vdd - -
-
V s = V max = V DD − V tnt
Q max = C s (V DD − V tn )
dQ s
IL = −( )
dt
dV s
IL = −C s ( )
dt
ΔVs
IL ≈ −C s ( )
Δt
Cs
t h = | Δ t |≈ ( )Δ Vs
IL
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Memory Elements – DRAM Refresh
Operation
As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the
hold time is
50 × 10 −15
t h= −9
× 1 = 0 .5 μ s
1 × 10
Memory units must be able to hold data so long as the power is
applied. To overcome the charge leakage problem, DRAM arrays
employ a refresh operation where the data is periodically read from
every cell
cell, amplified
amplified, and rewritten
rewritten.
The refresh cycle must be performed on every cell in the array with a
minimum
i i refresh
f h ffrequency off about
b t
1
f refresh ≈
2t h
IL
on +
Cbit Cs Vs Vf
+ -
Vbit Vf
-
Q s = C sV s
Q s = C sV f + C bit V f
Cs
Vf = ( )V s
C s + C bit
precharge
precharge
p g
bit, -bit
word line
word
data
- bit bit
data
N5 N6
write data
word
write
N3 N4
word
bit -bit
bit, bit
- bit bit
N1 N2
write
cell -cell
cell, cell
write data
word<3> word<0>
word<2> word<1>
word<1> word<2>
word<0> word<3>
word<6>
d 6
word<5>
word<4>
word<3>
word<2>
word<1>
word<0>
a2 a1 a0
National Central University Jin-Fu Li 26
Memory Elements – Row Decoder
Actual implementation
a0
a4
a3
a2 word
a1
-a0 clk
Pseudo-nMOS example
a0 word
od
a1 a2 en
write
read0
read1
write
read0
read1
-rbit1 -rwr_data rwr_data rbit0
R1 R2 R3 R4 C1 C2 C3 C4
R1 0 1 0 1
1 0 0 0
0 1 0 0 0 0 1 1
R2
0 0 1 0 1 0 0 1
R3 0 0 0 1 0 1 1 0
R4
C1 C2 C3 C4
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Memory Elements – ROM
A 4x 4-bit NAND-based ROM array
C1 C2 C3 C4
R1 R1 R2 R3 R4 C1 C2 C3 C4
0 1 1 1 0 1 0 1
R2
1 0 1 1 0 0 1 1
R3
1 1 0 1 1 0 0 1
1 1 1 0 0 1 1 0
R4
2N word lines
1 2 3 N
Address bits 2M columns