Build efficient datapath designs
By Aamir Farooqui
Sr. R&D Engineer
Synopsys Inc.
E-mail: aamirf@synopsys.com
Datapath is often considered to
be a specialized part of an arith-
metic logic unit design. How-
ever, the scope of datapath com-
ponents is more than that—it is
present in any RTL code that
contains *, +, -, >, <, <= and >=
shift operators. Even simple
finite state machines require
datapath components in the
form of incrementors, adders or
multipliers. With increasing
clock frequencies now reaching
the GHz scale, the burden of
efficient datapath design is rap-
idly increasing.
In many high-performance
VLSI designs, including all
high-performance micropro-
cessors, datapath is imple-
mented with custom design
techniques. The circuit and lay-
out of such structures are largely
handcrafted to achieve maxi-
mum performance and better
layout density. Most designers
are not aware that incremen-
tors, adders, subtractors or mul-
tipliers represent the presence
of datapath components in
finite state machines, memory
address generators, FIFO and
stack. In general, whenever a +,
-, *, <, >, or = sign is used in
HDL, a datapath component is
built in silicon.
With process technologies
shrinking below 90nm, issues
with signal integrity and leak-
age current are becoming
much more significant. Beyond
the already complex timing, re-
liability and functional correc-
tion tasks and sophisticated
Col 7 C6 C5
A Carry-
CSA B addition
C nents for best QoR. Module
CPA
Sum
Figure 1: Without carry-save addition, A+B+C would require two carry-
propagate adders, and only in the final recombination.
a b c de
+ + + design, carry-save operands bit
+ The module compiler tool takes
+ a certain set of constraints, cre-
Sum
Figure 2: The vector addition of six
inputs would use a carry-propagate
adder for each 2-to-1 reduction.
analyses on noise and power are
needed to ensure that the final
results will operate within
specifications. To perform cus-
tom design datapath for all
these disciplines would require
a large amount of time. In
today’s fast-changing market,
it is no longer possible to
handcraft all the RTL and get
the best performance.
Synopsys offers fully auto-
mated high-performance data-
path generators. These tools of-
fer datapath performance com-
parable to handcrafted designs
and provide more efficient sig-
nal integrity, power, verification
and layout tools for multidimen-
sional specification. This sys-
temic solution increases the
overall quality-of-results (QoR)
while reducing the time to cre-
ate these results.
Smart datapath generators
integrated into the design com-
piler operate on VHDL and
Verilog-based RTL designs and
offer high-performance data-
path synthesis. Meanwhile, its
module compiler language
(MCL) was developed specifi-
C4 C3 C2 C1 Col 0
save
Sum
Carry
cally to describe high-perfor-
mance datapath designs and
f provide more f lexibility and
features, structured datapath
manipulation and pipelining.
the MCL description and, given
ates high-performance data-
path implementations. A pow-
erful feature of MCL is to pre-
serve datapath regularity dur-
ing synthesis and generate au-
tomatic relative placement
used by place-and-route tools.
Building blocks
Adders are probably the most
widely used building blocks in
digital circuits. Every multi-
plier, divider, incrementor,
decrementor, comparator and
subtractor requires some sort of
add operation. Synopsys has a
variety of adder architectures
embedded into its datapath
tools. These adders range from
slow, but small ripple carr y
adders to very fast large fastcla
adders for integer and floating-
point operations. Two new
adder architectures in DC and
MC are “pprefix” and “aofcla,”
respectively. These adders offer
the best area-time QoR for given
design constraints.
Multipliers are the most criti-
cal element of any datapath, as
the speed of the multiplier often
determines the speed of the
cycle time of the digital design.
Designing high-performance
multipliers is always a chal-
lenge. Moreover, the physical
design of the multiplier is rather
difficult because of the complex
interconnections. There are
three basic parts of a parallel
multiplier: the partial product
generator, partial product adder
and final adder.
Datapath generators offer a
wide variety of multiplier ar-
chitectures with the ability to
mix and match their compo-
compiler also generates the
relative placement informa-
tion of the multiplier struc-
tures. Datapath generators
also offer the f lexibility to
choose between 3-2 adders or
4 x 2 compressors for better
physical layout of the multi-
plier architectures.
Shifters are expensive
(large-area) logic components
in arithmetic datapaths.
Shifters are sometimes used to
generate fixed dividers or mul-
tipliers. Datapath tools offer
shifters that may have a combi-
nation of the following features:
• Arithmetic or logical;
• Shifts only to the right, only
to the left or bidirectional;
• Regular or barrel shifter.
Multiplexers are not truly
datapath elements, but they are
extensively used in adders,
shifters, dividers, comparators
and datapath I/O selection.
The area and speed of the mul-
a b c d e f
CSA CSA
co0 co1
ci0
CSA
ci1
co2 ci2
CSA
CPA
Sum
Figure 3: The vector addition of six
inputs using CSA rewires a ripple
adder to do a 3-to-2 reduc-tion.
tiplexers is mostly governed by
the technology’s library cells.
However, a judicious selection
of multiplexers and their con-
trol signals also makes a big dif-
ference in datapath design.
Some simple optimizations for
multiplexers are merging two
levels into one larger multi-
plexer, using a pair of inverting
and non-inverting output mul-
tiplexers or using AND-OR
logic.
Datapath capabilities
Any integer datapath compo-
nent and architecture combina-
tion can be used either through
direct component instantiation
for optimal user control (not a
preferred method) using DW
foundation libraries or through
arithmetic operators in the
RTL. Since datapath tools are
context-driven, they automati-
cally select, given a certain set
of constraints, the best architec-
ture through RTL extraction,
also called adaptive datapath
extraction.
Module compiler covers de-
signs that cannot be expressed
using standard RTL or require
features such as structured
datapath design, carry-save op-
erands bit manipulation or rela-
tive placement information.
The f loating-point (FP)
datapath components can only
be instantiated through DW
Foundation and/or module
compiler as a function call. The
Synopsys FP library offers a set
of parameterizable FP compo-
nents and graphic architectures.
FP functions conform to the nu-
merical representation model
and accuracy requirements of
the IEEE 754 FP standard. All of
the functions provide either one
or two optional 8bit FP opera-
tional status flags to the inter-
face logic. All of the functions,
with the exception of FP com-
parison (DW_cmp_fp), have a
3bit RND input port that en-
ables dynamic programming of
the rounding modes on interme-
diate FP operation results. The
formats of RND rounding input
and STATUS output are the
same for all functions. The static
parameters e (exponent) and f
(fraction) enable a user to imple-
ment not only the standard
IEEE 754 FP functions, but also
virtually any FP format, and
allow the selection of the right
amount of precision and range
for a particular application.
There are var ious tech-
niques to improve the perfor-
mance of a datapath, such as
avoiding expensive car r y-
propagations and using carry-
save operations wherever pos-
sible. Other techniques in-
clude high-level arithmetic op-
timizations (in-context opera-
tor synthesis, operator merg-
ing and operator sharing).
These techniques are most ef-
fective when the biggest and
most complex possible data-
path blocks are extracted from
the RTL code.
Carry-save operations—One
major speed-area enhancement
technique used in modern digi-
tal circuits design is the ability
to add operands with minimal
carry propagation. The basic
idea is that three or more oper-
ands can be reduced to two us-
ing carry-save-adders (CSAs)
that perform the addition of
multiple operands while keep-
ing the sum and the carries
separate. This means that all of
the columns can be added in
parallel without relying on the
result of the previous column,
creating a two-output “adder”
with a constant delay that is
independent of the input size.
In Figure 1, A+B+C is com-
puted with one single carry-
Multiply vs. square
Multiply
Figure 4: A 32bit square is 40 percent smaller and 15 percent faster than
the 32bit multiply. In-context synthesis describes the hardware as X * X.
propagate adder using carry-
save addition. Without carry-
save addition, A+B+C would
require two carry-propagate
adders. Only the final recombi-
nation of the final carry and
sum vectors requires a carry-
propagate addition. CSAs are
useful when there are many ad-
dends. This is the case in multi-
plication, for example, where
many partial products must be
added together.
The schematic in Figure 2
shows how a generic tool would
synthesize a vector addition of
six inputs. This would use a
carry propagate adder for each
2-to-1 reduction. If this were a
performance design, a carry-
look-ahead type architec-
ture would be obtained for
each adder and suffer the area
penalty.
The schematic in Figure 3
shows how the same function
would be implemented in CSA
arithmetic using Synopsys
datapath synthesis tools. This
technique rewires a ripple adder
to do a 3-to-2 reduction. Then at
the final stage, the last two inter-
mediate sums need to be re-
duced to a single binary sum. A
propagate adder will be used for
this final 2-to-1 reduction.
Complex operator merging—
Complex arithmetic operator
merging is a special case of in-
context synthesis. Operator
merging allows the removal of
carry-propagate adders and re-
sults in faster and smaller de-
signs. Such optimizations are
possible only in an environment
of automated module genera-
tion using in-context synthesis.
Datapath generators are ca-
pable of operator merging for *,
+, -, >, <, <= and >=. Shift, mul-
tiplexer and truncation opera-
tors are also merged.
In sum-of-product (SOP)
operator merging, multiple
products and summands are
added together in one datapath
40% smaller
15% faster
Square
block with only one carr y-
propagate final adder. Internal
results are kept in redundant
number representation (carry-
save) wherever possible:
z = a * 2 * b * d - 3 * (c * d * e)
In product-of-sum (POS) op-
erator merging, multiple sums
and a product are mapped to a
datapath block with only one
carry-propagate final adder:
z = (a + b - c + d) * c
In-context operator synthesis—
This can improve the QoR in a
real design containing a mix
of datapath operators. Three
simple examples will be used to
explain the concept: constant
multiply, square and shift.
In each case, building an opera-
tor with respect to how it is
a bc d ef
CSA CSA
co0 co1
ci0
CSA
ci1
co2
ci2
CSA
CPA
Sum
Late arrival input
Figure 5: The ‘a’ input arrives late, thus it can be applied to the last
CSA and minimize the worst path delay of the circuit.
being used delivers better re-
sults than building the opera-
tor out of context.
The first case, multiplica-
tion by a constant, shows what
happens if you look just beyond
the boundary of the operator.
If you create a 32 x 32 multi-
plier and then tie one of the
inputs to a constant pattern,
the results are predictably
worse than creating a multi-
plier structure that takes ad-
vantage of the constant input.
In-context operator synthesis
techniques allow the descrip-
tion of the multiplier X * Y,
automatic detection that X or
Y is a constant, and generation
of the appropriate structure.
The second case in Fig-
ure 4 is more interesting. A 32
x 32 multiplier can be created
and then tie both inputs to-
gether to generate a squaring
circuit. Alternatively, a special
multiplier structure can be cre-
ated for this purpose. Such a
32bit square is 40 percent
smaller and 15 percent faster
than the 32bit multiply. In-con-
text synthesis automates the
design process to describe the
hardware simply as X * X.
Circuit timing is one of the
most important design criteria
to be optimized in several
phases of synthesis process. In-
context timing-driven synthe-
sis and optimization allows tree
delay minimization of the cir-
cuits based on input arrival pro-
file. Consider the case in Fig-
ure 5. The “a” input arrives
late, therefore it can be applied
to lthe last CSA, hence mini-
mizing the worst path delay of
the circuit.
ab c d e f
CSA
co1
ci0
CSA
co2 ci1
CSA
co2
ci2
CSA
CPA
Sum
Mutually exclusive operator
sharing—Mutually exclusive op-
erator sharing offers the maxi-
mum area benefit through shar-
ing a single operator for differ-
ent operations. For example, if
there is an add operation within
an if-else statement, then a
single adder with the required
control signals is built by the
datapath tools.
if(COND) then
Z = A + B;
else
Y = C + D;
end if;
Register retiming, automatic
pipelining—Pipelining achieves
faster throughput clock rates
while possibly sacrificing la-
tency. Register retiming per-
forms optimization of sequen-
tial logic by moving registers
through combinational logic
and across hierarchical bound-
aries to optimize timing with
minimum area impact. The
same functionality is preserved
at I/O boundaries. Register
retiming also supports clock
gating and will work on any de-
sign into which gated clocks
have been inserted through the
A B C D
Multiplier
Adder tree
Final adder
Temp0
Final adder
O larger and more complex than
Area cost:
2 Multipliers
1 Adder tree
1 Shifter
3 Final adders
SOP optimizations cannot be applied.
Figure 6: The new datapath flow can explore different architectures corresponding to a section of the design
containing the datapath and pick the best macro-architecture, given a certain set of constraints.
DesignWare component
DW_add_fp
DW_mult_fp
DW_flt2i_fp
DW_i2flt_fp
DW_cmp_fp
Table 1: All functions provide either one or two optional 8bit FP operational status flags to the interface logic.
use of a power compiler. On
purely combinational designs,
DC Ultra can be used to insert
pipelines to achieve timing re-
quirements and support mul-
tiple clocks. The formal verifi-
cation tool Formality has a fea-
ture that allows retimed designs
to be verified as long as the de-
sign does not contain an inter-
nal feedback loop.
Third-generation techniques
allow the operators to be created
on the fly. They can insert pipe-
lines in the middle of the opera-
tors if required. This allows
pipelining to be automated
smoothly across the entire
datapath. Designers can specify
the desired operating speed. If
the compiler is not able to
achieve that speed, it will insert
pipelines where needed. De-
signers can guide the placement
of the pipelines, such as at the
E F A B
Multiplier Multiplier
Final adder
Temp1
Shifter
Temp2
Area cost:
2 Multipliers
1 Adder tree
1 Shifter
2 Final adders
Saving of one final adder
Description
Floating-point addition
Floating-point addition
Conversion from floating point to integer
Conversion from integer to floating point
Floating-point comparison
end of a Wallace Tree in a multi-
plier. Such control over pipe-
lining is difficult in a manual
design environment.
DC Ultra synthesis flow
DC Ultra has a powerful new
datapath engine that can extract
arithmetic components and
optimize them to provide im-
proved results in datapath-in-
tensive designs. This capability
is a key component of the high-
level optimization (HLO) phase
of compile.
The first step in the DC Ul-
tra datapath flow is macro-ar-
chitecture selection. A macro-
architecture is a group of arith-
metic components configured
to implement an arithmetic ex-
pression. In this phase, the RTL
is examined to identify macro-
architectures that contain
datapath elements.
C D E F
Multiplier
Final adder
Temp1
Shifter
Temp2
Adder tree
Final adder
O
Figure 6 shows an example
of two different macro-architec-
tures derived from a segment of
Verilog code. The new datapath
flow can explore different ar-
chitectures corresponding to a
section of the design contain-
ing the datapath and pick the
best macro-architecture, given
a certain set of constraints.
This step is followed by
datapath extraction from the
macro-architecture (a macro-
architecture could contain sev-
eral arithmetic operators). Suc-
cessful datapath extraction re-
quires that arithmetic opera-
tors be “directly” connected, or
have no random logic in be-
tween datapath elements de-
fined by the *, +, -, >, <, <= and
>=. Shift and truncation opera-
tors can be extracted, as well as
multiplexers. Datapath extrac-
tion is timing-driven and occurs
during compile. Any extracted
operators can either be shared
or unshared, depending on
which strategy yields the great-
est benefit—again, given a cer-
tain set of constraints.
Finally, the extracted data-
path is implemented using the
Smart Datapath Generators.
The new datapath f low pro-
vides a quick way to identify the
smallest and fastest architec-
tures for the arithmetic compo-
nents. Smart Generators pro-
vide support across operators
and applies all the optimiza-
tions mentioned above to the
datapath designs.
Most datapath designs are
the designs shown here. Even
for designs consisting of tens of
thousands of gates, Synopsys
datapath tools deliver high per-
formance and enhancements
in productivity. These tools
supplement design techniques
with intelligent, high-perfor-
mance synthesis and optimiza-
tion algorithms.