12, ‘The following memories are specified by the num- ber of word times the number of bits per word. How many address lines and input-output data lines are needed in each case? (a) 8kx32 (b) 256Kx64 (c) 32Mx32 (d) 4Gx8 13, How many 32Kx8 RAM chips are needed to provide a memory capacity of 1M bytes? How many address lines are needed? 14. How many lines must be decoded for the chip select inputs for the problem 132. Specify the size of the de- coder. 15. Using the 64Kx8RAM construct the 256Kx32 RAM. 16. What will be the size of the ROM which maintains truth table of square of 3 bit numbers? 17. What will be the size of the ROM which maintains the truth table for product of two 8 bit numbers? 18. A32Kx8 RAM chip uses coincident decoding by split- ting the internal decoder into row and column select. Assuming that the RAM cell array is square (almost), what is the size of each decoder, and how many AND. gates are needed for decoding and address? 19. A DRAM has 12 address pins and its row address is 1 bit longer than its column address. How many ad- dresses total does the DRAM have? 1. Only read access is seen in A. Instruction cache B. Data cache C. TLB D. LI cache 2. First hardware cache that is used in a computer sys- tem is A. Instruction cache B. Data cache Cc. TLB D. Li cache 4. A computer system has a cache with access time 10ns, a hit ratio of 80% and average memory access time is 24ns. Then what is the access time for physical memory?8. What is the average memory access time of a m/c whose hit rate is 93%, with cache access time of 5ns and main memory access time of 80ns? 9. If we want an average memory access time of 6.5ns, our cache access time is Sns, and our main memo- ry access time is 80ns, what cache hit rate must we achieve? 10. Assume that a system has two level cache with hit ratios 90%, 97% and access times 4ns and 15ns and main memory access time is 80ns. What is the average memory access time? 11. Consider a direct mapped cache with 64 blocks and a block size of 16 bytes. What block number does byte address 1200 map to? 13, In a 16KB direct mapped cache with line length of 32 bytes how many bits are needed to determine the byte that a memory operation references within a cache line, and how many bits are used to select the line in the cache that may contain data. 16. How many total bits are needed for a direct mapped cache with 64KB of data and one word blocks, assum- ing a 32bit addresses and computer is a 32 bit com- puter. 17. Assume direct mapped cache with 4 locations. Find out the final content of cache if the sequence of re- quests are 001, 010, 011, 100, 101 and 111. Repeat the same for two way set-associative cache. Assume with both LRU replacement policy. The content of the memory isas follows. Assume initially cache is empty. Address Data 000 o101 001 Mu o10 0000 ou o110 100 1000 101 0001 110 1010 1 010025. Consider details of two cache memories. Which is faster in accessing memory? In each case, t, is the ac- cess time of the cache memory, tm is the access time of the main store, and h is the hit ratio. Cache A. t,, = 70 ns, Ons, h=0.9 Cache B.t,=60ns, t=5ns, h=09 26. For the following system, calculate the hit ratio h re- quired to achieve the stated speedup ratio $ compared to the system with only memory. Use following de- tails: 35. A block direct mapping cache has lines/slot that con- tains 4 words of data. The cache size is 64Kline and the main memory capacity is l6Mbytes. a. Given the following main memory address 3AF- F80h, find the values for tag, line/slot and word field in hexadecimal. b, Given the following information, find the main memory address in hexadecimal. tag _line/slot_word 11 word 10 word 01 word 00 3Fh | 9DA3h Data 40. Effective Access Time Example: A computer has a single cache (off-chip) with a 2 ns hit time and a 98% hit rate. Main memory has a 40 ns access time. What is the computer's effective access time? If we add an on-chip cache with a.5 ns hit time and a 94% hit rate, what is the computer's effective access time? How much of a speedup does the on-chip cache give the computer? Answers: Effective memory access time in the first case= 0.98*2 ns + 02 * (40+2) ns = 2.8 ns. Effective memory access time with on-chip cache= .5 ns + .06* (2 ns +.02 * 40 ns) = .668 ns. ‘Therefore, speedup is 2.8 / 668 = 4.2.