PD Checks

List of checks:
Initial:
checkDesign
timeDesign
physicalcells check
checkUnique
preplace checks:
checkDesign
checkpinAssignment
check_timing
checkFPlan
macro orientation
reportDensityMap
queryDensity
utilization
PGmesh
Placement checks:
checkDesign
report_clock_gating_check
timeDesign
check_timing
reportGatecount
checkPlace
congestion
Density
Utilization
Placeopt checks:
How many buffers added
checkDesign
timeDesign
check_timing
reportGatecount
checkPlace
congestion
Density
Utilization
CTS checks:
Clock build are not
checkDesign
timeDesign
check_timing
reportGatecount
checkPlace
congestion
Utilization
reportClockTree
analyzeClockTreespec
ckSynthesis -check {setCTSMode –engine ck}
clockDesign
CTSopt checks:
How many buffers are added
checkDesign
timeDesign
check_timing
reportGatecount
checkPlace
congestion
Density
Utilization
Route checks:
checkDesign
timeDesign
check_timing
reportGatecount
checkPlace
congestion
Density
Utilization
verifyConnectivity
VerifyGeometry
Routeopt checks:
checkDesign
timeDesign
reportGatecount
checkPlace
congestion
Density
Utilization
verifyConnectivity
VerifyGeometry
Routeopt_hold checks:
timeDesign
reportGatecount
congestion
Density
Utilization
verifyConnectivity
VerifyGeometry
Note: checkDesign, check_timing, timeDesign, checkPlace,

reportGatecount checks, density, congestion(starting from preCTS) and
Utilization checks are done in each and every stage.
Initial Design checks
command : checkDesign
Description: checks for missing or inconsistent library and design data at any
stage of the design and also gives following reports.
Summary report: checkNetlist , checkplacement, dontUsecell, floating

IO,floatingIopins, floatingPort, HFnet, nooutputNet, pgtermConnectivity.
Command : :checkNetlist
Description: check netlist gives information regarding Design summary i.e. std
cells ,I/O pad cell, area, power and ground ports, pins.
Summary report:
Design summary:
Total standard cell number (cells) : 203886
Total Block cell number (cells) : 15
Total I/O pad cell number (cells) : 0
Total standard cell area (um^2) : 474749.91
Total Block cell area (um^2) : 564569.85

Total I/O pad cell area (um^2) : 0.00
Design Statistics:
Number of Instances : 203901
Number of nets : 234858
Average number of pins per Net : 3.18
Maximum number of pins in Net : 24224
I/O port summary:
Number of primary I/O ports : 718
Number of input ports : 364
Number of output ports : 354
Number of Bidirectional ports : 0
Number of power/Ground ports : 0
Command : :Checkplacement
Description: checksplacement gives any place and unplaced instances

information.
Summary report:
No violations found
Number of placed instances : 0
Number of unplaced instances : 203901
Macro blocks : 15
Placement Density : 69.9% (1039320/1486935)
Floating I/O pins:

I/O pin not connected in design:
ctieXttrigack_i[3]
ctieXttrigack_i[2]
ctieXttrigack_i[1]
a5_b_in[7]
a5_b_in[6]
a5_b_in[5]
a5_b_in[4]
a5_b_in[3]
a5_r_in[7]
a5_r_in[6]
a5_r_in[5]
a5_r_in[4]
Dontusecells:
VIAONPEH_BUF_PW_12
VIAONPEH_BUF_PW_16
SEN_CKGTNLT_CTY2_4
SEN_CKGTPLT_CTY2_4
Sadslsuk41p2048x32m4b8w1c0p1d1t0rw11
SEN_CKGTPLT_CTY2_4
Cdc_triple_flop_rstn
High fanout Nets : 35
Command : timeDesign -prePlace -setup
Description: Returns worst negative slack (WNS) ,total negative slack(TNS) in all
path groups and also DRVs.
Summary report:
Setup analysis:
Setupmode All reg2reg reg2cgate default
WNS(ns) -15.308 -0.016 0.271 -15.308
TNS(ns) -15.367 -0.032 0.00 -15.334
Violating paths 5 2 0 3
All paths 36842 34733 1524 907
Worst Violated path summary :
Endpoint: a5_axi_clk_o (^) checked with leading edge of clk_a5_test
Begin point: axi_clk_sel_i[0] (v) triggered by leading edge of clk_a5_test
Analysis View: ACT_INIT .ss0p99vm40c.cworest.setup.setup
Other end arrival time : 0.000
- External delay :35.000
+ Phase shift :50.000
= Required time :15.000
- Arrival time :30.308

= Slack time : -15.308
Clock Rise Edge : 0.000
+ Input delay :30.000
+ Drive adjustment : 0.005
=Beginpoint arrival time :30.005
Command : timeDesign -prePlace -hold
path groups.
Summary report:
Hold analysis:
Hold mode All reg2reg reg2cgate default
WNS(ns) 0.010 0.014 0.046 0.010
TNS(ns) 0.000 0.000 0.000 0.000
All paths 36841 34732 1524 907
Physical cells checks:
Description: reports all physical cells in design like tabcells, Endcap cells
Tabcells: tabcells are present in design. cell to cell distance is 30um.
Endcapcells : Endcap cells are present design.
PowerGating: power gating cells are present in design. Aon(always on )

buffers and Sleep buffers.
Command : checkUnique
Description: whether the netlist is unique or not information
Summary report: 1 means netlist is unique.

Preplacedesign Checks
Command : :checkFPlan
Description: checks the quality of the floorplan to detect potential problemsbefore

the design is passed on to other tools.
Summary report:
Floating/unconnected IO pins : 12
No.of regular pre-routes not on tracks : 0
Command :checkpinAssignment
Descrption: checks the generated partition and I/O pins
Summary report :
Total pins : 718
Legally assigned pins : 718
stage of the design and also gives following results
Report: checkNetlist , checkplacement, dontUsecell, floating IO,floatingIopins,

floatingPort, HFnet, nooutputNet, pgtermConnectivity.
Summary report:
Design summary:

Design Statistics:
I/O port summary:

information.
Summary report:
Total instances with placement violations : 10
Instances placed overlapping with other instances :10

Of which 17354 are fixed
No.of unplaced instances : 202019
Command : :reportIsolation
Description: Reports the added isolation cells and instances.
Summary report:
Isolation cells : 0
Command : : check_timing
Description: checks consistency and completeness on the timing constraints

specified for a design.
Summary report:
Warning Warning description No of warnings

Clock_expected Clock not found where 31
clock is expected
Ideal_clock_waveform Clock waveform is ideal 8
No_drive No drive assertion 49
No_input_delay No input delay assertion 48
with respect to clock
Uncons_endpoint Unconstrained signal 76
arriving at end point
Macro orientation:
Description: Describes macro orientation and status.
Summary report:
MX90 : 5
R90 : 3
MY90 : 3
R270 : 4
Status : fixed
Macro placement Description: In encounter GUI ameba shaped logo is there just
go trough it once select the corresponding floor plan and press shift+G
command for hierarchical view,it gives whether macro are placed relatively or not
and also module separation will also appears. some of the related pics for a5_top
design we taken.we can identify with different colours.
Floor plan View:
Pic
Command :reportDensityMap
Summary report:
Pic
Command :queryDensity
Description: gives module and pin density information
Summary report:
Pin density : 12.2%
Module Density : 60.9%
Utilization : 73.38
PG mesh:
pg mesh established in metal 7,metal 8 and metal 2(power gating) layers .and also
connection established to follow pins.
Placement Checks

Summary report:
Design summary:
Design Statistics:
I/O port summary:


information.
Summary report:
Placement Density : 58.58%(431290/736191)
Command :report_clock_gating_check
Description: reports information of all or specific clock gating checks of the

current design.
Summary report:
Instance Enabl Clock Type Level Setup Setup
e rise fall
INDUS_CLOCK_a5_top_RC_HIER_INST201/RC_CGIC_INS EN CK L H 0.176 0.181
T
Command :timeDesign –preCTS -setup
Summary report:
Setup analysis:
WNS(ns) -11.143 -11.143 -4.101 -1.384
TNS(ns) -47628.9 -46319.1 -1273.7 -174.535
All paths 36842 34733 1524 907
DRVs Real Total

Nr nets(terms) Worst vio Nr nets (terms)
Max_cap 100(100) -35.809 103(103)
Max_tran 2263(39210) -121.315 2279(39417)
Max_fanout 2715(2715) -24207 2748(2748)
Max_length 0(0) 0 0(0)
Density : 58.584%
Congetion : 0.00% H and 0.27% V total:0.27%(H+V)
Endpoint: ../u_fifo_in/pheader2_valid_e6_reg/RD (^) checked with leading

edge of clk_a5
Begin point: ../n_resetreg3_reg/Q (^) triggered by leading edge of clk_a5
- Recovery :7.019
+ CPPR adjustment :0.000
- Uncertainty :0.200
= Required time : -5.219
- Arrival time : 5.924
Command : timeDesign -prePlace -hold
path groups.
Summary report:
Hold analysis:
Hold mode All reg2reg reg2cgate Default
WNS(ns) 0.037 0.037 0.058 0.055
TNS(ns) 0.000 0.000 0.000 0.000
All paths 36841 34732 1524 907
Command :reportGateCount
Description: reports no of gates, cells and area information.
Summary report:
Gate area : 0.5292 um^2

Gates : 1932034
Cells : 187269
Area :1022432.6 um^2
Command : : check_timing
Description: checks consistency and completeness on the timing constraints

specified for a design.
Summary report:
Warning Warning description No of warnings

Clock_expected Clock not found where 31
clock is expected
Ideal_clock_waveform Clock waveform is ideal 8
No_drive No drive assertion 49
No_input_delay No input delay assertion 48
with respect to clock
Uncons_endpoint Unconstrained signal 76
arriving at end point
Command :checkPlace
Description: To check for unplaced switches and all macros placed with in the
core.
Summary report:
Place :202741
Unplaced :0
Placement Density :58.58%

Placeopt Checls

Summary report:
Design summary:
Design Statistics:

I/O port summary:

information.
Summary report:
Command :timeDesign –preCTS -setup
Summary report:
Setup analysis:
WNS(ns) -0.301 -0.301 -0.182 -0.218
TNS(ns) -196.727 -180.057 -2.021 -15.408
All paths 26842 34733 1524 907
DRVs Real Total

Max_cap 0(0) 0 4(4)
Max_tran 0(0) 0 0(0)
Max_fanout 3145(3145) -59 3178(3178)
Density : 61.593%
Endpoint: ../iutlb_miss_req_reg/D (^) checked with leading edge of clk_a5
Begin point: ../u_sadslsuk41p64x63m4b2w1c0p1d1t0rw11/Q(macro) (^)

triggered by leading edge of clk_a5
- setup : 0.180
= Required time : 1.620
Command : timeDesign -preCTS -hold
path groups.
Summary report:
Hold analysis:
WNS(ns) 0.038 0.038 0.068 0.052
TNS(ns) 0.000 0.000 0.000 0.000
All paths 36841 34732 1524 907
Summary report:
Gates : 1973888
Cells : 197473
Area :1044581 um^2
Total cells added in place opt :10204

Command :checkPlace
core.
Summary report:
Place :212945
Unplaced :0
CTS checks
Clock Tree:
Summary report:
Design summary:
Design Statistics:
I/O port summary:


information.
Summary report:
Clock Trace:
Clock Tree: a5_clk_i
Nr. subtress : 1971
Nr .sinks : 22583
Nr.Rising sync pins : 22567
Nr.Inverter Rising sync pins : 0
Nr Falling sync pins : 16
Nr.Inverter falling sync pins : 0
Nr . Unsync pins : 0
Clock Tree: atclk_i
Nr. subtress : 5
Nr .sinks : 70
Clock Tree: pclkdbg_i
Nr. subtress : 7
Nr .sinks : 68
Summary report:
Gates : 2038970
Cells : 201382
Area :1079023 um^2
Command :timeDesign –postCTS -setup
Summary report:
Setup analysis:
WNS(ns) -1.338 -0.669 -0.439 -1.338
TNS(ns) -1444.9 -1174.6 -13.190 -257.107
All paths 36842 34733 1524 907
DRVs Real Total

Max_cap 0(0) 0 4(4)
Max_tran 1947(1947) -0.209 1948(27583)
Max_fanout 3070(3145) -59 3212(3212)
Density : 66.271%
Endpoint: ../ pmuirq_o(v) checked with leading edge of clk_a5
Begin point: ../ pmn_ccnt_overflowed_reg/Q (macro) (v) triggered by leading

edge of clk_a5
- External delay : 1.315

- setup : 0.180
+ Source insertion delay :0.007
Command : timeDesign -postCTS -hold
path groups.
Summary report:
Hold analysis:
WNS(ns) -1.273 -1.272 0.047 -1.273
TNS(ns) -227.234 -191.088 0.000 -36.145
All paths 36841 34732 1524 907
Endpoint: ../ rst_dest_n (^) checked with leading edge of clk_a5
Begin point: a5_rst_n_i (^) triggered by leading edge of clk_a5
Analysis View: ACT_INIT .ff1p21v125c.cbest.hold.hold
+ Removal : 0.078
- CPPR adjustment :0.000
+ Uncertainty :0.100
+ Input delay :0.000
+ Drive Adjustment :0.004
Command :reportClockTree
Description: clock tree structure information such as the number of subtrees

,sinks, and buffers and maximum, minimum trigger edge delay at sinks.
Summary report:
Clock:a5_clk_i
Nr. of subtrees :1971

Nr .of sinks :22583
Nr of buffers :2
Nr of level :16
Root rise input Tran :0.1(ps)
Root fall input Tran :0.1(ps)
(Actual) (Required)
Rise phase delay : 1273.3 ~ 1573.8(ps) 0~10(ps)
Fall phase delay :1348.2~1847(ps) 0~10(ps)
Trig. Edge skew : 370.3(ps) 80(ps)
Rise skew : 300.5(ps)
Fall skew : 498.8(ps)
Max. Rise buffer Tran : 112.2(ps) 80(ps)
Max. Fall buffer Tran : 92.4(ps) 80(ps)
Max Rise sink Tran : 107.7(ps) 80(ps)
Max fall sink Tran : 93(ps) 80(ps)
Min Rise buffer Tran : 16.6(ps) 0(ps)
Min Fall buffer Tran :22.1(ps) 0(ps)
Min Rise sink Tran :21.5(ps) 0(ps)
Min fall sink Tran :28.2(ps) 0(ps)

Clock:atclk_i
Nr. of subtrees :5
Nr .of sinks :70
Nr of buffers :1
Nr of level :2
(Actual) (Required)
Fall phase delay :187.9~330.6(ps) 0~10(ps)
Trig. Edge skew : 179.3(ps) 300.7(ps)
Max. Fall buffer Tran : 35(ps) 80(ps)
Max fall sink Tran : 70.9(ps) 80(ps)
Min Fall buffer Tran :35(ps) 0(ps)

Clock:pclkdbg_i
Nr. of subtrees :7
Nr .of sinks :68
Nr of buffers :1
Nr of level :2
(Actual) (Required)
Fall phase delay :189.2~340.8(ps) 0~10(ps)
Trig. Edge skew : 170.1(ps) 300.7(ps)
Max. Fall buffer Tran : 41.6(ps) 80(ps)
Max fall sink Tran : 70.5(ps) 80(ps)
Min Fall buffer Tran :41.6(ps) 0(ps)

Command :analyzeclocktreespec
Description: analyzes the loaded clock tree specification file, runs timing analysis
,and generates a timing report that can be used to access whether a clock tree
specification file is reasonably correct before actually running clock tree synthesis.
Summary report:
Clock coverage: 99.666%
Total number of buffers added during CTS : 437
Command :checkPlace
core.
Summary report:
Place :216854
Fixed :19331
Unplaced :0
Utilization :76.14%
CTSopt checks

Summary report:
Design summary:
Design Statistics:
I/O port summary:


information.
Summary report:
Command :timeDesign -postCTS -setup
Summary report:
Setup analysis:
WNS(ns) -2.175 -0.434 -0.443 -2.175
TNS(ns) -1065.6 -255.676 -22.252 -794.572
All paths 36842 34733 1524 907
DRVs Real Total

Max_cap 0(0) 0.000 0(0)
Max_tran 1(3) -0.084 1(3)
Max_fanout 2009(2009) -55 2123(2123)
Density : 71.29%
Endpoint: ../ RC_CGIC_INST/EN (^) checked with leading edge of clk_a5
Begin point: axi_clk_sel_i[1] (^) triggered by leading edge of clk_a5
Other end arrival time : -0.956
- Clock gating setup : 0.060
+ input delay : 1.128
+Drive adjustment :0.007

+ Network insertion delay : 1.243
=Beginpoint arrival time : 2.379
Command : timeDesign -postCTS -hold
path groups.
Summary report:
Hold analysis:
WNS(ns) -0.737 -0.001 0.050 -0.737
TNS(ns) -0.739 -0.001 0.000 -0.737
All paths 36841 34732 1524 907
Endpoint: a5_axi_clk_o (^) checked with leading edge of clk_a5
Begin point: a5_clk_i (^) triggered by leading edge of clk_a5
+ External delay :0.500

- Arrival time : -0.590
+ Source insertion delay : -1.191
=Beginpoint arrival time : -1.191
Description:
Summary report:
Gates : 2108746
Cells : 205698
Area :1079023 um^2
Utilization : 71.29%
Route checks
Summary report:
Design summary:
Design Statistics:
I/O port summary:


information.
Summary report:
Placement Density : 71.3%
Command :timeDesign -postRoute -setup
Summary report:
Setup analysis:
WNS(ns) -2.239 -0.529 -0.493 -2.239
TNS(ns) -2559.0 -1663.3 -122.190 -804.638
All paths 36842 34733 1524 907
DRVs Real Total

Max_cap 0(0) 0.000 0(0)
Max_tran 19(79) -0.117 19(79)
Max_fanout 2009(2009) -55 2123(2123)
Density : 78.71%
Total number of glitch violations:1

Command : timeDesign -postRoute -hold
path groups.
Summary report:
Hold analysis:
WNS(ns) -0.762 -0.041 0.044 -0.762
TNS(ns) -6.594 -5.832 0.000 -0.762
All paths 36841 34732 1524 907
Description:
Summary report:
Gates : 2108746
Cells : 205698
Area :1115948 um^2
Command :VerifyConnectivity
Description: reports connectivity and unconnected pin information
Summary report:
Layer Object
PWELL VSS
Violations regarding PWELL more than 1000

Command :VerifyGeometry
Description: reports all DRC issues like samenet, wiring, antenna, shorts and
overlap.
Summary report:
Cells :862
Samenet :112
Wiring :0
Antenna :0
Shorts :26
Overlap :0
Routeopt checks

Summary report:
Design summary:
Design Statistics:
I/O port summary:

information.
Summary report:

Placement Density : 70.7%
Command :timeDesign -postRoute -setup
Summary report:
Setup analysis:
WNS(ns) -2.117 -0.396 -0.448 -2.117
TNS(ns) -1408.2 -611.559 -60.073 -752.929
All paths 36842 34733 1524 907
DRVs Real Total

Max_cap 0(0) 0.000 0(0)
Max_tran 147(615) -0.186 147(615)
Max_fanout 2012(2012) -55 2012(2012)
Density : 70.7%

path groups.
Summary report:
Hold analysis:
WNS(ns) -0.767 -0.306 0.011 -0.767
TNS(ns) -61.339 -60.572 0.000 -0.767
All paths 36841 34732 1524 907
Summary report:
Gates : 2100754
Cells : 203515
Area :1115948 um^2
Summary report:
Layer Object
PWELL VSS
overlap.
Summary report:
Cells :83
Samenet :409
Wiring :360
Antenna :0
Shorts :225
Overlap :0
Routeopt_hold checks
Command :timeDesign -postRoute
Description:
Summary report:
Setup analysis:
WNS(ns) -2.182 -0.585 -0.508 -2.182
TNS(ns) -2180.7 -1321.3 -102.891 -785.998
All paths 36842 34733 1524 907
DRVs Real Total

Max_cap 0(0) 0.000 0(0)
Max_tran 174(1290) -0.212 174(1290)
Max_fanout 2012(2012) -55 2126(2126)
Density : 78.72%
path groups.
Summary report:
Hold analysis:
WNS(ns) -0.752 -0.005 0.048 -0.752
TNS(ns) -0.778 -0.027 0.000 -0.752
All paths 36841 34732 1524 907
Summary report:
Gates : 2109120
Cells : 208146
Area :1116146 um^2
Utilization : 78.72%{without filler cells}
Summary report:
Layer Object
PWELL VSS

overlap.
Summary report:
Cells :862
Samenet :112
Wiring :0
Antenna :0
Shorts :26
Overlap :0

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List of checks:

Note: checkDesign, check_timing, timeDesign, checkPlace,

Summary report: checkNetlist , checkplacement, dontUsecell, floating

Total standard cell number (cells) : 203886

Total Block cell number (cells) : 15

Total I/O pad cell number (cells) : 0

Total standard cell area (um^2) : 474749.91

Total Block cell area (um^2) : 564569.85

Number of Instances : 203901

Number of nets : 234858

Average number of pins per Net : 3.18

Maximum number of pins in Net : 24224

I/O port summary:

Number of primary I/O ports : 718

Number of input ports : 364

Number of output ports : 354

Number of Bidirectional ports : 0

Number of power/Ground ports : 0

Description: checksplacement gives any place and unplaced instances

Number of placed instances : 0

Number of unplaced instances : 203901

Placement Density : 69.9% (1039320/1486935)

Floating I/O pins:

High fanout Nets : 35

Command : timeDesign -prePlace -setup

Worst Violated path summary :

Endpoint: a5_axi_clk_o (^) checked with leading edge of clk_a5_test

Begin point: axi_clk_sel_i[0] (v) triggered by leading edge of clk_a5_test

Analysis View: ACT_INIT .ss0p99vm40c.cworest.setup.setup

Other end arrival time : 0.000

- External delay :35.000

+ Phase shift :50.000

= Required time :15.000

- Arrival time :30.308

Clock Rise Edge : 0.000

+ Input delay :30.000

+ Drive adjustment : 0.005

=Beginpoint arrival time :30.005

Command : timeDesign -prePlace -hold

Physical cells checks:

Tabcells: tabcells are present in design. cell to cell distance is 30um.

Endcapcells : Endcap cells are present design.

PowerGating: power gating cells are present in design. Aon(always on )

Description: whether the netlist is unique or not information

Summary report: 1 means netlist is unique.

Description: checks the quality of the floorplan to detect potential problemsbefore

No.of regular pre-routes not on tracks : 0

Descrption: checks the generated partition and I/O pins

Total pins : 718

Legally assigned pins : 718

Report: checkNetlist , checkplacement, dontUsecell, floating IO,floatingIopins,

Total standard cell number (cells) : 219358

Total I/O pad cell number (cells) : 0

Total standard cell area (um^2) : 490311.91

Total Block cell area (um^2) : 564569.85

Total I/O pad cell area (um^2) : 0.00

Number of Instances : 219373

Number of nets : 234862

Average number of pins per Net : 3.19

Maximum number of pins in Net : 24224

I/O port summary:

Number of primary I/O ports : 718

Number of input ports : 364