EXERCISE – II

Subject: Digital Electronics (EC1306)

1. Design a 2-to-4 line decoder with active HIGH enable and active LOW outputs.

2. Combine two 2-to-4 line decoders with active LOW enables and active LOW outputs and
design a 3-to-8 line decoder.

3. Combine two 4:1 multiplexers and design an 8:1 multiplexer.

4. Combine two 4:1 multiplexers and design an 8:1 multiplexer (use multiplexer tree).

5. Using 4:1 multiplexers, design a 16:1 multiplexer.

6. Design (i) a NOT gate (ii) 2 input XOR gate

7. Using 4:1 multiplexer(s), realize the following:

(i) A full adder. Implement the LSB at the inputs of the multiplexer.

(ii) 3-bit odd parity checker. Implement the 2 right most bits at the inputs of the
multiplexer.

(iii) F ( A, B, C ) = ∑ m ( 2, 3, 5, 6 ) . Implement A at the inputs of the multiplexer.

(iv) F ( A, B, C ) = ∑ m ( 0, 3, 5, 7 ) . Implement B at the inputs of the multiplexer.
(v) F ( P, Q, R, S) =∑ m (1, 2, 3, 6, 8, 11, 12, 13, 15 ) . Implement P and Q at
the inputs of the multiplexer.

(vi) F ( w, x, y, z ) = ∑ m ( 2, 4, 5, 6, 9, 10, 11, 13, 14 ) . Implement y and z at the

inputs of the multiplexer.

(vii) F=A+BC . Implement C at the inputs of the multiplexer.

8. In a 4:1 multiplexer, select inputs are B and C. Inputs of the multiplexer are connected as
given below:
I0 =I 2 =A , I1 =I3 =A
Show that the function the multiplexer implements is F ( A, B, C ) =A ⊕ C
9. Design a 2 to 4 line decoder using 4:1 multiplexers.

10. Design a 4 to 2 line priority encoder.

11. Derive and draw the circuit of a 3-bit carry look ahead adder.

12. Draw the circuit of the following, prepare their (i) characteristic table and (ii) excitation
table:
(a) SR latch (b) D latch (c) JK latch (d) T latch

13. What is the drawback of an SR latch? How is this overcome?

14. What is the problem associated with a JK latch? Mention three methods to overcome it.

15. Perform the following conversions:

(i) SR flip-flop to D flip-flop

(ii) SR flip-flop to JK flip-flop

(iii) SR flip-flop to T flip-flop

(iv) D flip-flop to JK flip-flop

(v) D flip-flop to T flip-flop

(vi) JK flip-flop to D flip-flop

(vii) JK flip-flop to T flip-flop

(viii) T flip-flop to D flip-flop

(ix) T flip-flop to JK flip-flop

(x) JK flip-flop to SR flip-flop* (*Is this possible? Justify)

16. Draw the circuit of a master-slave JK flip-flop. Why is this circuit preferred over an
ordinary JK latch?

17. What is the difference between a latch and a flip-flop? Which one is preferred over
another and why?
18. In the following plot, draw the output wave form of Q for different triggering conditions
as mentioned: