ECE 371 Exam #2 Test Notes

Period = 1 / 11.6271973 Hz = 0.0860052491sec

Question # 10 (RTI What is counter value)
6. Solve for either the Counter (as shown) or the timing of
! DoIt(), using this equation:
Given!the!following!register!settings!in!the!9S12!
!
RTICTL = 0x26 Timing (sec) / Period (sec) = Counter
CRGINT = 0x92 => .699 s / 0.0860052491sec = 8.12741091
CRGFLG = 0x8A So C must be 8.
and a core clock frequency of 10.14 MHz,

how often (in ms) is DoIt() run in the following RTI interrupt handler?

void RTI_ISR(void) Question # 10 (RTIWhatIsFrequency)

{ static int counter = 0;

CRGFLG |= 0x80;
Given!the!following!register!settings!in!the!9S12!
counter++; !
if (counter >= 254) RTICTL = 0x5F
{ counter = 0; CRGINT = 0x80
DoIt(); CRGFLG = 0xCB
}
} and a core clock frequency of 1.08 MHz
Answer
what is the RTI frequency in Hz?
Selected Answer: 359.0 Answer

Correct Answer: 4.1 ± 1%

Question # 10 (RTI What is counter value)

Given!the!following!register!settings!in!the!9S12!
1. CRGINT and CRGFLG are ignored, as they only initialize the
! register.
RTICTL = 0x74
CRGINT = 0x92 2. Use RTICTL to find RTI frequency with the following
CRGFLG = 0x8A
formula:
and a core clock frequency of 3.81 MHz,
RTI freq. = Core Clock freq. / Prescale
what does C in the following RTI interrupt handler need to be to
=> Prescale = 1024 * 2^ ([RTICTL bits 6:4] - 1) *
run DoIt() every 699 ms?
([RTICTL bits 3:0] + 1)
void RTI_ISR(void)
{ static int counter = 0; = (1.08 * 10^6) / (1024 * 2 ^ (5-1) * (15 + 1) = 4.12
CRGFLG |= 0x80;

counter++; Question # 10 (RTIWhatIsRTICTL)

if (counter >= C)
{ counter = 0;
DoIt();
} Given!that!we!want!to!produce!a!9S12!RTI!frequency!as!close!to!50!Hz!as!
} possible,!what!does!the!value!of!RTICTL!need!to!be!given!the!core!
frequency!is
1. Ignore CRGINT. 2^21!Hz?
!
2. Ignore CRGFLG. (Give!your!answer!in!hex,!without!using!the!0x!prefix.)
Answer
3. Using RTICTL to get Prescale:
(Clock divisor so that the RTI can produce interrupts at a certain
0x44
frequency)
0x39

Prescale = 1024 * 2^ ([RTICTL bits 6:4] - 1) * ([RTICTL bits

3:0] + 1) 1. The formula for this problem is given as:
= 1024 * 2^6 * 5 = 327 680
RTI freq. = Core frequency / Prescale
4. Divide Core Clock by Prescale to find Scaled Clock => Prescale = 1024 * 2^ ([RTICTL bits 6:4] - 1) *
([RTICTL bits 3:0] + 1)
Scaled Clock = (3.81 * 10 ^6 Hz)/ 327 680 = 11.6271973 Hz
2. Find RTICTL bits 6:4 and 3:0 that make the equation as close
5. Period = 1 / Scaled Clock to the RTI frequency as possible
 Using equation: 2^21/(1024*2^(X-1)*(Y+1)) = 50
…… 0xXY = 44 or 39 2. Period of TCNT = 1 / TCNT rate

3. Total Time (until overflow) = Period of TCNT * Count

Question # 11 (EdgeDetection)
=> Count = (2 ^ 16) - 1

Given the register settings below, what type of signal will produce and input
capture on Pin 0? Question # 11 (OutputCompareLevels)
TCTL1 = 0x82
TCTL2 = 0xBE Given the register settings below, what will happen to Pin 4 upon a successful
TCTL3 = 0x6C output compare of Timer Channel 4?
TCTL4 = 0x78
TCTL1 = 0x27
Correct Answer: TCTL2 = 0x8D
TCTL3 = 0xC9
Disabled TCTL4 = 0xCC
1. This problem deals with edge detection, so use TCTL3 for Correct Answer:
channels 7:4 and TCTL4 for 3:0. It will be set to 1

2. Compare the two bits corresponding to the channel (either

from TCTL3 or 4) to the chart to determine what happens upon 1. This problem deals with output compares, so use TCTL1 for
successful comparison. channels 7:4 and TCTL2 for 3:0.

2. Compare the two bits corresponding to the channel (either

from TCTL1 or 2) to the chart to determine what happens upon
successful comparison.

Question # 11 (MaxCountCalc)

A 9S12 has a core clock frequency of 2.4 MHz. How long (in ms) would it
take the free-running counter to overflow (assuming an initial value 0x0000)
given the following register settings? Question # 11 (SquareWaveCalc)
TSCR1 = 0x97;
TSCR2 = 0x16; A 9S12 has a Bus clock frequency of 9.3 MHz. What is the period of the square
TCTL1 = 0x46; wave (in ms to two decimal places) generated with the following code?
TCTL2 = 0x45;
TCTL3 = 0x16; TSCR2 = 0x91;
TCTL4 = 0x02;
TIOS = TIOS | 0x01;
Correct Answer: TCTL2 = (TCTL2 & 0xFC) | 0x01;
3,495.25 ± 1% TFLG1 = 0x01;
TC0 = TCNT + 7,858;
1. TCNT Rate = Bus Rate / (2 ^ Prescale)
while(1)
=> Bus Rate = Core Clock Rate / 2 {
while((TFLG1 & 0x01)==0);
=> Prescale = TSCR2[2:0] (lower three bits of TC2 = TC2 + 7,858;
TSCR2) TFLG1 = 0x01;
}
-Bus rate = 2.4 * 10^6 / 2 Correct Answer: 3.38 ± 1%
-Prescale = lower three bits of TSCR2 are 110 = 6

2
 NOTE: You must enable the enhanced timer capture so that it will be able to set
1. TCNT rate = Bus Rate / (2 ^ Prescale) flags. The flags it sets are always on Port T (or whatever FFEE corresponds to)

-4 * 10^6 / 2 = bus rate = 2*10^6

=> Bus Rate = Core Clock Rate / 2 -Prescale = lowest three bits of TSCR2 = 3
=> Prescale = TSCR2[2:0] (lower three bits of TSCR2) -Free running timer resolution (TCNT freq) = 2*10^6 / (2^prescale) =
250,000
-Free running timer period (TCNT period) = 1/f = 1/ 250,000 = 4 *
2. Period of TCNT = 1 / TCNT rate 10^-6

3. Period (of the Square Wave) = Period of TCNT * COUNT * -Multiple timer period by 26,890 because timer must get to that before
the alarm goes off
2 -Interrupt must be called 61 times before the port T signal is toggled
so multiply by 61
=> 2 for the toggle (for a square wave, a rise and a fall) -Port T output is toggled… Two toggles are needed to make a square
so multiply by 2
-So answer = 13.122 s
= ([(9.3 * 10 ^ 6) / (2^1)] ^ -1) * 7858 * 2 = .00338 = 3.38ms
Question # 11 (TimerFrequencyCalc)

Question # 11 (SquaeWaveCalcWithOverflow)

A 9S12 needs a timer clock frequency of 11.1 MHz. What would the core
A 9S12 has a core clock frequency of 4 MHz. What is the period of the square
clock frequency (in MHz to three decimal places) need to be given the
wave (in seconds to three decimal places) generated with the following code?
following register settings?
int main(void)
TSCR1 = 0x87;
{
TSCR2 = 0x91;
TIOS |= 0x01;
TCTL1 = 0x22;
TSCR2 = 0x83;
TCTL2 = 0x36;
TFLG1 |= 0x01;
TC0 = TCNT + 26,890; TCTL3 = 0x17;
SETVECT(0xFFEE, oc0_isr); TCTL4 = 0x32;
TIE |= 0x01; Answer
ENABLE();
Correct Answer: 44.400 ± 1%

while (1);
}

1. Use the following equation to solve this problem:

void oc0_isr(void)
{ static count = 0;
Timer clock frequency = Bus frequency / (2 ^ Prescale)

if (++count >= 61) => Bus frequency = Core clock frequency / 2

{ count = 0;
PTT ^= 0x01;
=> Prescale = TSCR2[2:0]
}
TC0 = TC0 + 26,890;
TFLG1 |= 0x01; Question # 11 (TimerPeriodCalc)
}
A 9S12 needs a timer clock period of 1.9 micro seconds. What would the core
Answer
clock frequency (in MHz to three decimal places) need to be given the following
Correct Answer: register settings?
13.122 ± 1%
TSCR1 = 0x98;
TSCR2 = 0x62;
1. Bus Rate = Core Clock Rate / 2 TCTL1 = 0x58;
TCTL2 = 0x98;
2. TCNT rate = Bus Rate / (2 ^ Prescale) TCTL3 = 0x52;
TCTL4 = 0x61;

=> Bus Rate = Core Clock Rate / 2

=> Prescale = TSCR2[2:0] (lower three bits of TSCR2) Correct Answer: 4.211 ± 1%

3. Period of TCNT = 1 / TCNT rate 1. Use the following equation to solve this problem:
4. Period (of the square wave) = Period of TCNT * COUNT * 2 Timer clock period = 1 / [Bus frequency / (2 ^ Prescale)]
* OverflowCount
=> Bus frequency = Core clock frequency / 2
=> COUNT = count from main function (TCNT + COUNT) => Prescale = TSCR2[2:0]
=> OverflowCount = count from if statement (++count >=
OverflowCount) Question # 11 (PreScaleAndCount)
=> 2 for the two square wave toggles

3
A 9S12 has a bus clock frequency of 8.0 MHz. Give the values necessary for the 4. Prescale can be any value between 0 and 7, inclusive. Test
code below to produce a square wave on channel 0 with a period of 5 ms. each of these values, and try to find a resulting value for Count
TSCR2 &= ~(BIT_3 | BIT_1 | BIT_0); that is closest to an integer. (If multiple reasonable answers
TSCR2 |= PreScale; exist, usually select the largest Prescale value.)
while(1)
{
Question # 13 (CFORC)
while((TFLG1 & BIT_0)==0);
TC0 = TC0 + Count;
TFLG1 = BIT_0;
}
Give a single C instruction which will cause the designated output compare
PreScale = [a] (As a decimal number.) action already programmed for channel 6 to occur immediately (but not
Count = [b] (As a decimal number.) produce an interrupt.) (Leave a single space between all variables and/or
operators and use no parentheses.)
Correct Answers for: a Answer
5
Selected Answer: CFORC = 0x40;
Correct Answers for: b 625

A 9S12 has a bus clock frequency of 8.0 MHz. Give the values necessary for the
code below to produce a square wave on channel 0 with a period of 5 ms. Give a single C instruction which will cause the designated output compare
action already programmed for channel 5 to occur immediately (but not
TSCR2 &= ~(BIT_3 | BIT_1 | BIT_0); produce an interrupt.) (Leave a single space between all variables and/or
TSCR2 |= PreScale; operators and use no parentheses.)
Answer
while(1)
{ Correct Answer: CFORC = 0x20
while((TFLG1 & BIT_0)==0);
TC0 = TC0 + Count;
TFLG1 = BIT_0; 1. Answer is almost always in this form:
}

PreScale = [a] (As a decimal number.) CFORC = 0x___;

Count = [b] (As a decimal number.) (In the blank, enter a hex value with 1’s for the channels you
want to use, 0’s otherwise)
Correct Answers for: a 5

Correct Answers for: b 625 Question # 13 (DelayCount)

A 9S12 has a core clock frequency of 1.0 MHz. Give the values necessary
for the code below to produce a square wave on channel 0 with a period
of 28 micro seconds. Assuming that the Bus clock is 9.5 MHz, what is the minimum delay count
value that can be used in DLYCT (as a single decimal digit) to insure the
TSCR2 &= ~(BIT_3 | BIT_1 | BIT_0); input capture system ignores pulses shorter than 76.5 micro seconds?
TSCR2 |= PreScale; (Answer '0' if DLYCT count cannot be large enough to ignore the signal.)
Answer
while(1)
{ Correct Answer: 3
while((TFLG1 & BIT_0)==0);
TC0 = TC0 + Count;
TFLG1 = BIT_0;
} 1. Answer will be 0, 1, 2, or 3. See slide 13.18. Only the lowest
two bits of the register matter.
Prescale = [a] (As a decimal number.)
Count = [b] (As a decimal number.)

Correct Answers for: a 0

Correct Answers for: b 7

1. Bus rate = Core clock rate / 2

2. Timer clock period = {1 / [Bus rate / (2 ^ Prescale)]} * 2 *

Count

=> 2 for toggle (square wave)

=> Prescale = TSCR2 [2:0]

3. Rearrange formula to find equation:

(2 ^ Prescale) * (Count) = (Timer clock period) * (Bus Rate) / 2

4
 3. The register OC7M selects the channels which can
2. Bus rate = Core clock rate / 2 POTENTIALLY be changed.
=> 1 selects the channel (pin)
3. Bus period = 1 / Bus rate => 0 leaves it alone (so 0x11 would select pins 4 and 0)

4. Time (of pulses to ignore) / Bus period = Delay
5. Look up delay on the chart, return its corresponding binary
value (0, 1, 2, or 3)
NOTE: You must pick a value equal to or LARGER than your
answer, never smaller.
4. The register OC7D then clears and sets ONLY pins in PTT
that have been selected by OC7M.
=> 1 sets a pin that has been selected by OC7M
=> 0 clears it (the unselected pins are untouched, even if OC7D
is high for them)
5. If PTT is NOT given, and pin 7:0 output is desired, unknowns
may occur anywhere that OC7M did not select.

Question # 13 (OC7M-OC7D)
Question # 14 (FindPWMClockFreq)

Given!the!following!Bus!Clock!frequency!and!register!settings!for!the!9S12,!give!
Give!the!values!for!OC7M!and!OC7D!so!that!the!following!channels!will!be!
the!PWM!clock!frequency!(in!kHz!to!3!decimal!places)!for!channel!2.!
affected!as!described!below!by!a!successful!output!compare!on!Channel!7.!
!
!
fBus = 9.50 MHz
Channel 4 Sets to 1
Channel 3 Sets to 1
Channel 1 Sets to 1
PWMPRCLK = 0x14
Channel 0 Clears to 0
PWMSCLA = 0x49
PWMSCLB = 0x6A
PWMCLK = 0x79
OC7M = [a];
Answer
OC7D = [b];
Selected Answer: 4750
Correct Answers for: a 0x1B
1B
ALGORITHM FOR FINDING PWM CLOCK
1B
FREQUENCY
Correct Answers for: b 0x1A
1A 1. Bus frequency = Core clock frequency / 2
1A
2. Determine which clock is being used, according to which
channel is under inspection:
Given!the!code!below,!what!will!be!the!new!state!(0,!1,!or!Unknown)!of!each!
Port!T!pin!listed!below!after!the!Channel!7!timer!system!has!had!a!successful!
output!compare?! => Clock A or SA: channels 0, 1, 4, 5
! => Clock B or SB: channels 2, 3, 6, 7
DDRT = 0xFF
TIOS = 0xFF 3. PWM Clock = Bus frequency / (2 ^ Prescale)
PTT = 0xD8
TCTL1 = 0x3C
TCTL2 = 0xF4 => For clock A, Prescale = PWMPRCLK [2:0]
TCTL3 = 0x45 => For clock B, Prescale = PWMPRCLK [6:4]
TCTL4 = 0xD3

OC7M = 0x6C 4. Determine whether the clock type is “S” or not

OC7D = 0xE5

Pin 7 = [a] 1
=> Look at the PWMCLK register, at the pin
Pin 6 = [b] 1 corresponding to the observed channel
Pin 5 = [c] 1 - If pin = 1, use “S” variant
Pin 4 = [d] 1 - If pin = 0, use clock A or B
Pin 3 = [e] 0
Pin 2 = [f] 1
Pin 1 = [g] 0
5. If clock is an “S” variant, i.e. SA or SB, then apply another
Pin 0 = [h] 0 scaling with this formula:

New PWM Clock = PWM Clock A (or B) / (2 * PWMSCLA (or

B))
1. Ignore the four TCTL registers, the DDRT and the TIOS (if
Note: PWMSCL value is full register value (between 0
present).
and 255)
2. PTT (if given) is the starting condition for the pins in Port T.
6. Whether Step 5 was performed or not, this PWM Clock value
is the frequency of the PWM clock. It’s the answer!

5
 Given!the!following!Core!Clock!frequency!and!register!settings!for!the!9S12,!
Question # 14 (FindPWMPER) supply!the!parameters!for!the!PWM!waveform!produced!on!Channel!1.!
!
fCore = 12.7 MHz
Given!the!following!Bus!Clock!frequency!and!register!settings!for!the!9S12,!
provide!the!settings!for!PWMPERn!and!PWMDTYn!in!order!to!produce!a!PWM!
waveform!on!Channel!3!with!the!given!parameters.! PWMPRCLK = 0x63
! PWMSCLA = 0xC4
fBus = 0.85 MHz PWMSCLB = 0x30
PWMCLK = 0xB7
PWMPER1 = 0xCA
PWMPRCLK = 0x04 PWMDTY1 = 0x95
PWMSCLA = 0xD3 PWMPOL = 0x4B
PWMSCLB = 0x1F PWMCAE = 0xAC
PWMCLK = 0x01
PWMPOL = 0x75
PWMCAE = 0x7E (Give all answers to nearest integer)

PWM Period = 300 micro s For Channel 1:

PWM Duty Factor = 85 % PWM Period = [a] micro s
PWM Time High = [b] micro s
PWM Duty = [c] %
PWMPER3 = [a]
PWMDTY3 = [b] Correct Answers for: a 99759

Correct Answers for: a 0x7F Correct Answers for: b 73585

7F
Correct Answers for: c 74
127

Correct Answers for: b 0x13

1. Use the same formulas and algorithm as found in the previous
13 question.
19
=> PWMPER and PWMDTY must be converted from hex to
1. Use the algorithm to find the PWM Clock frequency, save for decimal
part 4.
2. Time High = Duty % * PWM Period
=> Found in FindPWMClockFreq
Question # 14 (PWM-CON)
2. Given PWM Period, if PWMCAE is 1 at the observed
channel’s bit, divide it by 2. Given!the!following!Core!Clock!frequency!and!register!settings!for!the!9S12,!
supply!the!parameters!for!the!PWM!waveform!produced!on!Channel!3.!
3. Calculate PWM Waveform frequency = 1 / PWM Period !
(new period, possibly divided in part 2) fCore = 12.0 MHz

4. Solve the following equation relating PWM freq., waveform PWMPRCLK = 0x72
freq., and PER, for PER: PWMSCLA = 0x16
PWMSCLB = 0xBB
PWMCLK = 0x11
PWM Waveform frequency = PWM Clock frequency / PER PWMPOL = 0x1D
PWMCAE = 0xF4
5. PER = PWMPER PWMCTL = 0x20
PWMPER0 = 0x7A PWMDTY0 = 0x5A
PWMPER1 = 0xD7 PWMDTY1 = 0xA9
6. Now to determine the PWMDTY, first check the PWMPOL PWMPER2 = 0x72 PWMDTY2 = 0x64
bit corresponding to the observed channel. Then solve the PWMPER3 = 0xBD PWMDTY3 = 0x8F
PWMPER4 = 0x7A PWMDTY4 = 0x5F
resulting equation for PWMDTY: PWMPER5 = 0x93 PWMDTY5 = 0x6E
PWMPER6 = 0xCB PWMDTY6 = 0xA6
=> If the polarity is 1: 100 * PWMDTY / PWMPER = Duty PWMPER7 = 0xCC PWMDTY7 = 0xAB
Factor %
=> If the polarity is 0: 100 * (PWMPER - PWMDTY) / (Give all answers to nearest integer)
PWMPER= Duty Factor %
For Channel 3:
NOTE: If you end up with a value that is not an integer, PWM Period = [a] ms
round PWM Time High = [b] ms
PWM Duty = [c] %

Question # 14 (FindPWMPeriod) Correct Answers for: a 627

6
 PWMCLK = 0x66
Correct Answers for: b 549 PWMPER7 = 0xB5
PWMDTY7 = 0x24
Correct Answers for: c 88 PWMPOL = 0x28
PWMCAE = 0xB8

1. This problem is to be solved exactly as the previous problem,

with one variation:

=> PWMCTL is high at the observed channel. This means that

two channels are going to be concatenated…. bit 7 means
registers 6 and 7; bit 6 means registers 4 and 5; bit 5 means
registers 2 and 3; bit 4 means registers 0 and 1.
=> The lower number register will always be the more
significant byte in the 16 bit number. Then combine the hex
numbers of the two registers, PER and DTY. For instance, PER0
= 0x45 and PER1 = 0x93 would become PER = 0x4593, a 16 bit
number.
2. Having found the new PER and DTY values, solve exactly as
the previous question.
Question # 14 (PWMCTL)
Give a single C instruction which will stop all PWM counter in "freeze
mode." (Leave exactly one space between each variable/symbol.)
Answer
Selected Answer: PWMCTL = 0x04;
Give a single C instruction which will create a 16-bit PWM channel on pin 5
of Port P. (Leave exactly one space between each variable/symbol.)
Answer
Selected Answer:
PWMCTL = 0x40;
1. Use the following chart to answer questions about the
PWMCTL register:
.
1. There are three important pieces of information:
=> PWMPOL: If the polarity is 1, the signal starts off high. If
the polarity is 0, the waveform starts off low.
=> PWMCAE: If it is center aligned (1), the picture must be
symmetrical.
=> Duty Factor %: Determine the duty factor. The waveform
should be high for that percentage of the period.
If the polarity is 1, then the duty percentage is
100 * PWMDTY / PWMPER.
If the polarity is 0, then the polarity is
100 * (PWMPER – PWMDTY) / (PWMPER).
Question # 14 (WhatPWMScale)
Given!the!following!Core!Clock!frequency!and!register!settings!for!the!9S12,!give!
the!values!for!PCKA!and!PWMSCLA!which!create!the!desired!PWM!waveform!
frequency!for!Channel!0!asked!for!below.!
!
fCore = 9.000 MHz
fPWM Waveform = 15.980 Hz
PWMPER0 = 100
PWMCAE = 0x11
(Give all possible combinations of settings as decimal
numbers. List in order of lowest PCKA value first. If
there are more blanks than possibilities, enter a 0 in
each.)

PCKA = [a] 2 PWMSCLA = [b] 176

PCKA = [c] 3 PWMSCLA = [d] 88
PCKA = [e] 4 PWMSCLA = [f] 44
PCKA = [g] 5 PWMSCLA = [h] 22
PCKA = [i] 6 PWMSCLA = [j] 11

1. Use the equation below:

PWM Waveform (* 2 if center aligned) = Bus Rate / (2 *

(2^PCKA) * PWMSCLA * PWMPER)

2. Manipulate it so that it has the form:

Question # 14 (WhatPWMForm) PWMSCLA = Bus Rate / (2 * (2^PCKA) * PWMPER * PWM

Waveform (* 2 if center aligned))

Given!the!register!settings!below,!what!form!below!best!describes!the! 3. Test the 8 possible values of PCKA (0:7) and write down any
waveform!created!on!PWM!Channel!7?!!
values of PCKA such that PWMSCLA turns out to be an integer
!
PWMPRCLK = 0xD9 less 256 (as well as the corresponding PWMSCLA values).
PWMSCLA = 0x6C PWMSCLA must be very close to an integer (must be able to
PWMSCLB = 0xA1 round to .99 or .01)

7
 >>Write a C instruction to reset the interrupt flag for pin 7 of Port H. Correct
Answer: PIFH = PIFH | 0x80;

>>Write a single C instruction using a bitwise operator that toggles pin 7 on

Port H without affecting the value of any other pin. Correct Answer:
PTH = PTH ^ 0x80;
Chap 9 (Interrupts): Chap 10 (RTI General):
>>There are two types of interrupts which are determined by their timing.
What clock is the RTI frequency directly based off? Oscillator Clock
An example of a[n] [a] interrupt is a timer used to write to a display at
specified periodic intervals: synchronous
What bit in the 9S12 tell whether or not the RTI has expired? RTIF
>>Interrupts can be divided into two types: [a] which can be turned on or off
If the Core Clock freq is 17.5 MHz, that is the ECLK freq? 8.75
through the clearing or setting of certain register bits, and [b] which can be
turned on in software, but cannot be turned off with software. Correct
If the ECLK freq is 8 MHz, what is the Core Clock freq? 16
Answers for: a maskable Correct Answers for: b non-maskable
SO ECLK freq = bus clock freq
>>To have the processor run runit() when timer channel five produces an
interrupt we would run the following instruction: SETVECTOR([a], [b]); What bit in the 9S12 turns on or off the RTI? RTIE
Correct Answers for: a 0xFFE4 Correct Answers for: b runit
Given the following register settings in the 9s {RTICTL = 0x00; CRGINT =
>> [a] interrupts can occur in three ways: an interrupt request on the [b] pin, 0x92; CRGFLG = 0x8A;} and a core clock frequency of 10 MHz, what is
an unimplemented software instruction trap, or a software interrupt the RTI frequency is Hz: 0 ( or “disabled”)
instruction, [c]. Correct Answers for: a non-maskable Correct Answers
for: b XIRQ Correct Answers for: c SWI Chap 11(Timers General):
>>An interrupt vector is [a] bits in the 9S12: 16
What 9S12 integrated functionality counts clock pulses until an input signal
>>A[n] [a] is an exception which does not save the state of the processor changes state? Input Capture
before executing its service routine: reset
What 9S12 integrated functionality works like a “stop watch”: input capture
>>A[n] [a] is an exception with a “one-way ticket” : reset
What 9S12 functionality works like a “Alarm Clock” output compare
>>Exception – a break in program flow either an interrupt or reset.
Which timer channel can affect all other tuner channels’ behavior? Channel 7
>>Interrupt Vector → 16 bits
What is the highest value possible in the TCNT register? 0xFFFF
>> [a] interrupts can be disabled and enabled through software: maskable
When does the TOF bit get set? When the free-running counter goes from
>>To have the processor run doit() when pin 1 of Port H goes low, we would 0xFFFF to 0
run the following instruction: SETVECTOR([a], [b]); (Chart given) Correct
Answers for: a 0xFFCC Correct Answers for: b doit How many input capture channels are there on the 9S12? 8

>>To have the processor boost the priority of an interrupt on timer 7, we How many Output Compare channels are there on the 9S12: 8
would put a value of [a]in the [b] register. Correct Answers for: a 0xE0
OUTPUT COMPARE (has edge define)
Correct Answers for: b HPRIO INPUT CAPTURE (Has edge detect)

>>To have the processor run doatod() when timer the A/D 1 produces an What signal values/transitions can the Output compare system produce at a
interrupt we would run the following instruction: SETVECTOR([a], [b]); pin? {High Value, Low Value, Toggle}
Correct Answers for: a 0xFFD0 Correct Answers for: b doatod
What signal values/transitions can input capture be initialized to detect?
>>HPRIO = “boosts” priority of an interrupt source {Rising Edge , Falling Edge}

>>When the X-bit of the CCR is [a], the non-maskable interrupt is disabled: RTIE turns on or off the RTI
1 (or “one”) 16 bit registers: {TCNT, TC4,TC5}

>>The x bit in the CCR controls the non-maskable interrupt of the 9S12
>>The X-bit of the CCR cannot be set to 1 through software.
>>Timing Errors—(synchronous: in time; asynchronous: not in time)
Give a single C statement to set the Enhanced Capture System of a 9S12 to
produce the following transitions on the following pins of Port T given a
successful output compare. {Pin 7 = timer disconnected from pin; Pin 6 = Set
Line; Pin 5 = Toggle; Pin 4 = Clear Line). Correct answer: TCTL1 = 0x36;

>>Types of Resets --(Clock monitor: the clock slows or stops; Power-On: a

low-active reset pin is activated at startup to guaruntee a known initial state;
External: low-active reset pin is activated by switch; Watchdog: computer
resets under blackout, brownout, or infinite loop conditions)

>>Write a single C instruction to reset the interrupt flags for every pin on
Port H. Correct Answer: PIFH = 0xFF;