SR FLIP - FLOP

Introduction

The SR flip - flop is one of the fundamental parts of the sequential circuit logic. SR flip
- flop is a memory device and a binary data of 1-bit can be stored in it. SR flip -flop has
two stable states in which it can store data in the form of either binary zero or binary one.
Like all flip - flops, an SR flip - flop is also an edge sensitive device.

SR flip - flop is one of the most vital components in digital logic and it is also the most
basic sequential circuit that is possible. The S and R in SR flip - flop means ‘SET’ and
‘RESET’ respectively. Hence it is also called Set - Reset flip - flop. Below the
symbolic representation of the SR Flip Flop is shown:

Symbolic Representation of SR Flip Flop

Working

SR flip – flop works during the transition of clock pulse either from low – to – high or
from high – to – low (depending on the design) i.e. it can be either positive edge
triggered or negative edge triggered.

For a positive edge triggered SR flip – flop, suppose, if S input is at high level (logic 1)
and R input is at low level (logic 0) during a low – to – high transition on clock pulse,
then the SR flip – flop is said to be in SET state and the output of the SR flip – flop is
SET to

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1. For the same clock situation, if the R input is at high level (logic 1) and S input is at
low level (logic 0), then the SR flip – flop is said to be in RESET state and the output
of the SR flip – flop is RESET to 0.

The SR flip – flops can be designed by using logic gates like NOR gates and NAND
gates. Unclocked or simple SR flip – flops are same as SR Latches. The two types of
unclocked SR flip – flops are discussed below.

Construction and Operation.

I) S-R Flip Flop Using NAND Gate

SR flip flop can be designed by cross coupling of two NAND gates. It is an active low
input SR flip – flop. The circuit of SR flip – flop using NAND gates is shown in
below figure

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Working

Case 1:
When both the SET and RESET inputs are high, then the output remains in previous
state i.e. it holds the previous data.

Case 2:
When SET input is HIGH and RESET input is LOW, then the flip flop will be in
RESET state. Because the low input of NAND gate with R input drives the other
NAND gate with 1, as its output is 1. So both the inputs of the NAND gate with S
input are 1. This will cause the output of the flip – flop to settle in RESET state.

Case 3:
When SET input is LOW and RESET input is HIGH, then the flip flop will be in SET
state. Because the low input of NAND gate with S input drives the other NAND gate
with 1, as its output is 1. So both the inputs of the NAND gate with R input are 1.
This will cause the output of the flip – flop to settle in SET state.

Case 4:
When both the SET and RESET inputs are low, then the flip flop will be in undefined
state. Because the low inputs of S and R, violates the rule of flip – flop that the
outputs should compliment to each other. So the flip flop is in undefined state (or
forbidden state).

The table below summarizes above explained working of SR Flip Flop designed with
the help of a NAND gates
(or forbidden state).

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II) S-R Flip-Flop Using NOR Gate

SR flip flop can also be designed by cross coupling of two NOR gates. It is an active
high input SR flip – flop. The circuit of SR flip – flop using NOR gates is shown in
below figure.

The operation is same as that of NOR SR Latch.

Working

Case 1:

When both the SET and RESET inputs are low, then the output remains in previous
state i.e. it holds the previous data

Case 2:
When SET input is low and RESET input is high, then the flip flop will be in RESET
state. Because the high input of NOR gate with R input drives the other NOR gate
with 0, as its output is 0. So both the inputs of the NOR gate with S input are 0. This
will cause the output of the flip – flop to settle in RESET state.

Case 3:

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When SET input is high and RESET input is low, then the flip flop will be in SET
state. Because the low input of NOR gate with S input drives the other NOR gate with
1, as its output is 1. So both the inputs of the NOR gate with R input are 1. This will
cause the output of the flip flop to settle in SET state.

Case 4:
When both the SET and RESET inputs are high, then the flip flop will be undefined
state. Because the high inputs of S and R, violates the rule of flip flop that the outputs
should complement to each other. So the flip flop is in undefined state (or forbidden
state).

The table below summarizes above explained working of SR Flip Flop designed with
the help of a NOR gate.

Even though simple SR flip – flops and simple SR latches are same, both the terms
are used in their respective contexts.

The problem with simple SR flip – flops is that they are level sensitive to the control
signal (although not shown in figure) which makes them a transparent device. In order
to avoid this, Gated or Clocked SR flip – flops are introduced (whenever the term SR
flip – flop is used, it usually refers to clocked SR flip – flop). Clock signal makes the
device edge sensitive (and hence no transparency).

III) Clocked SR Flip – Flops

Two types of clocked SR flip – flops are possible: based on NAND and based on
NOR. The circuit of clocked SR flip – flop using NAND gates is shown below

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This circuit is formed by adding two NAND gates to NAND based SR flip – flop. The
inputs are active high as the extra NAND gate inverts the inputs. A clock pulse is
given as input to both the extra NAND gates.

Hence the transition of the clock pulse is a key factor in functioning if this device.
Assuming it is a positive edge triggered device, the truth table for this flip – flop is
shown below.

The same can be achieved by using NOR gates. The circuit of clocked SR flip – flop
using NOR gates is shown below.

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The figure suggests a structure of RS flip – flop (as R is associated to the output Q),
the functionality of SET and RESET remain the same i.e. when S is high, Q is set to 1
and when R is high, Q is reset to 0.

Application.
SR flip – flops are very simple but are not widely used in practical circuits because of
their illegal state where both S and R are high (S = R = 1). But they are used in
switching circuits as they provide simple switching function (between Set and Reset).
One such application is a Switch de – bounce circuit. The SR flip – flops are used to
eliminate mechanical bounce of switches in digital circuits. SR Flip flop is used in the
Digital Logic circuit for the switch or the circuit breaker to hold the closed state even
the input controlling signal disappears. As a Digital latching relay it can be used.
As a switching mechanism for alarm circuit, that is when an alarm is pressed it will
not get reset until the reset button is pressed.

Comparison Between JK Flip Flop and S-R Flip Flop.

i) When both S and R inputs are 1,output goes to a metastable state but when both the
inputs of J and K are 1 output is in toggle state wrt previous state.

ii) JK flip flop often termed as Universal flip flop because all other flips like D,T and
SR can be derived from that while this is not the case wrt SR flip flops.

iii) SR flip flops when used as latch can be help in the bounce elimination of the
switches which is one of its major advantages while this is not the case with JK flip
flops.

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iv)There are problems associated with JK flip flop too where in the case when both J
and K input are 1,output can change more than once in a single clock cycle which
gives rise to race condition. One more problem occurs with JK flip flop is that
propagation delay of flip flop is less than the propagation delay of clock pulse width.

Advantages

I) Simple Circuit

II) SR flip-flops when used as latch can be help in the bounce elimination of the
switches.

Disadvantages

I) Cannot have input 1.

II) Both inputs shouldn't be HIGH when the clock is triggered. This is considered an
invalid input condition, and the resulting output isn't predictable if this condition
occurs.

III) According to the truth table, When both S and R input are 0, there is no change in
output and it holds the previous state.When S is 0 and R is 1, output is on reset
state.When S is 1 and R is 0, output is in set state.However, When both the inputs are
1, output is in invalid state and it goes in a metastable state where the output cannot be
predict.

Conclusion.

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As a conclusion, the function of the S – R flip-flop is to store a bit value of either 0 or
1 for later use based on the S and R input values. When S is high, the flip-flop stores a
logic value of 1and stores a logic 0 when input R is high. The output of the S – R
flip-flop is not meaningful when S and R have the same logic levels. The critical race
condition occurs when both inputs of the S – R latch change from high to low
simultaneously. In such condition, the final output of the latch depends entirely on
which output can propagate its value to the feedback input faster than the other can.
Thus,sequential circuit designers avoid race conditions by making sure that logic 1 is
never applied to both inputs simultaneously.

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 NAME:
SHARVIN A/L RAVI

STUDENT ID :
53106116180

CLASS:
4AEM4

SUBJECT:
DIGITAL TECHNIQUE (MECHANICAL)
 LECTURER:
ROSLAM BIN IDERIS