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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPWRD.2016.2519604, IEEE
Transactions on Power Delivery
Power Testing of Pre-Insertion Resistors:
Limitations and Solution
Helmut Heiermeier, Member, IEEE, and Rosy Balaram Raysaha
 (separation of arcing contacts), the PIR switch will open
Abstract—Pre-Insertion Resistors (PIR) are used in
combination with circuit breakers to absorb switching transients
and come into effect during the “closing” operation of the
breaker. It is mainly used for rated voltages equal to or higher
than 420 kV for line lengths above 200 km. Although it is an
important component, power testing of complete PIR is very
complicated and not well-defined. Therefore, an attempt has been
made in this paper to provide alternative test methods for power
testing of PIR without compromising on its important
parameters. Due to high energy requirement and limitations of
the test laboratory, a multipart testing of PIR is necessary to
prove its thermal capability and dielectric behavior. Before
proceeding with the complete PIR test, the critical parameters of
PIR like Mechanical Insertion Time (MIT), Rate of Decay of
Dielectric Strength (RDDS) of interrupter and PIR switch, etc.,
should be verified by testing. These test procedures are also
explained in detail along with a method to theoretically evaluate
Electrical Insertion Time (EIT) for different network conditions.
The series PIR configuration for metal enclosed SF6 system has
been considered in this paper.
Index Terms— electrical insertion time, mechanical insertion
time, pre-strike, RDDS, series PIR, shunt PIR, thermal energy
I. INTRODUCTION
P RE-INSERTION Resistors (PIR) are used in combination
with Circuit Breakers (CB) to absorb switching transients
and come into effect during the “closing” operation of the
breaker [1], [2], [3], [4]. PIR consists of a resistor stack and a
switch, which will be called PIR switch in this paper.
Depending upon the position of the PIR switch with respect to
the interrupting chamber/CB, there can be a series or a parallel
PIR configuration. Series PIR configuration is widely used in
Dead Tank Breakers (DTB) and Gas Insulated Switchgear
(GIS) while parallel PIR configuration is widely used in Live
Tank Breakers (LTB). Basically, both configurations can be
used in DTB and GIS, depends upon bay layout, cost, etc.
In parallel/shunt PIR configuration (fig. 1a), the PIR switch
is in series with the resistor stack and both are in parallel with
the interrupter. The interrupter operation follows the PIR
switch operation, i.e., during “closing” operation (first
mechanical arcing contact touch), the PIR switch will close
followed by the interrupter and during “opening” operation
Helmut Heiermeier is with ABB Switzerland, CH-5401 Baden, Fabrikstrasse 13,
(email: helmut.heiermeier@ch.abb.com)
Rosy B. Raysaha is with ABB India, Maneja, Vadodara - 390013, Gujarat.
(email: rosy.raysaha@in.abb.com)
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1
followed by the interrupter. During “closing” operation, the
pre-strike in PIR switch must occur before it happens in the
interrupter. Depending on the design, PIR switch may remain
fully closed during normal operation. In a series PIR
configuration (fig. 1b), the PIR switch is in series with the
interrupter but in parallel with the resistor stack. It can be seen
from table 1 that different configurations experience different
stresses. Depending upon GIS bay layout, the series PIR
configuration might use less space and could be less expensive
than shunt PIR configuration.
There are several literatures available on the usage of PIR
for mitigation of switching overvoltages [5], [6], [7], [8], [9],
[10], [11], [12], [13]. An alternative to PIR is “Controlled
Switching” [13], [14], which is especially used for
applications like reducing inrush current in transformers and
overvoltages during capacitive switching. However, recent
advances in PIR technology [11], [12] have also made it
equally efficient for the latter applications keeping it cost
competitive with a relatively simple design. In addition,
literature is available on the replacement of PIR by pre-
insertion reactors [13] and also by surge arrestors [15], [16].
However, PIR continues to remain a reliable solution [2], [11]
and its performance needs to be confirmed by testing. The
amount of literature available on PIR testing is very limited
[17], [18] and even in international standards [18], no detailed
test procedure is mentioned. The power testing of complete
PIR is very complicated and less defined as compared to other
power tests for circuit breakers [18]. Therefore, an attempt has
been made in this paper to explain in detail the test procedure
of PIR since power testing of PIR requires special methods
and considerations. These test procedures need to take into
account the different stresses (based upon PIR configuration)
that will occur under various network conditions. Due to all
these factors, the power testing of PIR will finally result in a
multipart testing.
(a) Parallel PIR (b) Series PIR
Fig. 1. Schematic of PIR configuration
II. COMPARISON OF PIR ENERGY FOR DIFFERENT NETWORK
CONDITIONS
For PIR, there is a minimum “Electrical Insertion Time”
(EIT) specified, which is defined by network conditions. The
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2

resulting energy forms the basis for PIR dimensioning and

hence, is of prime importance. The maximum EIT, as well as, TABLE 1. Comparison of series and shunt PIR
number of operations is limited by the energy capability of the Switch Parallel PIR configuration Series PIR configuration
condition Interrupter PIR Interrupter PIR switch
resistor stack itself. Various network conditions have to be switch
considered to determine the most critical case for defining the “Close” closes last closes closes first closes last
resistor stack. For a given rated voltage and resistance, the operation and closes first and closes and
energy to be absorbed by PIR is defined by the Rate of Decay against full and closes against closes
short circuit against resistor against full
of Dielectric Strength (RDDS) of interrupter and PIR switch, current resistor current short
as well as, Mechanical Insertion Time (MIT). current circuit
In fig. 2, a series PIR configuration has been considered as current
an example with interrupter closing on Out-of-Phase (OoP) “Open” extinguishes opens extinguishes opens after
operation the short prior to the short interrupting
condition, i.e., it pre-strikes at the voltage peak which is 2 p.u.
circuit the circuit process of
(where 1 p.u. is peak phase voltage). In these figures, rectified current interrupter current the
voltage is plotted only for ease of calculation. The figure will interrupter
be explained in detail in section IV A. The MIT is defined as Closed must carry no must carry must carry
position nominal nominal nominal nominal
the time delay between the first mechanical arcing contact
current current to current current
touch of interrupter and PIR switch as shown in fig. 2a. The be carried
intersection of interrupter RDDS with source wave shows the Open must must must must
pre-strike instant in interrupter while the intersection of PIR position withstand withstand withstand withstand
RDDS with the voltage drop across PIR gives the pre-strike full full full max.
dielectric dielectric dielectric voltage
instant in PIR. The difference between these two pre-strike ratings ratings ratings drop across
instant gives EIT, i.e., the time for which the PIR will be resistor
inserted in the circuit. Fig. 2b shows the current through the during
interrupter and PIR after the respective switches are closed, operation
During PIR need to withstand the energy (heat), as well as, the
whereas the cumulative PIR energy is shown in fig. 2c. The operation dielectric stress along the resistor blocks
simulation is carried out using Alternative Transient Program
(ATP) and the simulation details will be explained in section
IVA.
A. Possible Network Conditions
Based upon network conditions, the maximum PIR energy
will be determined, which will then decide the dimension of
the resistor stack.
1) Closing against 100% Terminal Fault (TF)
This is a condition where highest short circuit current will
be provided by the network. However, the applied voltage will
be the nominal system voltage. Depending on the making
angle of the first switching device, this will lead to a different
energy input to the resistor stack. The probability of
occurrence of this stress during service is very low.
2) Closing against Out-of-Phase (OoP) Fig. 2. CB closing on OoP condition (series PIR) (a) Ucb and Upir represents
This condition is related to the highest voltage stress across voltage across interrupter and resistor respectively after corresponding
switches are closed, RDDS_cb is RDDS of interrupter, RDDS_pir is RDDS of
either the resistor stack or interrupter (depends upon PIR PIR (b) Ipir and Icb represents current through resistor and interrupter
configuration), which may lead to longest EIT. The respectively after PIR switch is closed (c) Cumulative PIR energy
probability of occurrence of this stress during service is also
very low.
3) Closing against Pre-Charged Line (PCL) B. Comparison of Stress for Different Network Conditions
This condition will produce high voltage stress for the For comparison, calculations have been performed for a
resistor stack, as well as, for the switching devices. Since in series PIR configuration with interrupter closing at different
this case, the PIR energy is related to the length of the line and network conditions. The results are given in table 2 and it
its natural capacitance, it will be comparatively low. The shows the different stresses occurring across PIR switch based
probability of occurrence of this stress in service is high since on the following ratings as an example:
this is a normal switching operation for a line circuit breaker. rated network voltage (Ur): 420 kV (r.m.s, line-to-line)
rated short circuit current (Ir): 63 kA (r.m.s,)
This condition can produce voltage stress higher than OoP
rated frequency (f): 60 Hz
since while closing on to a PCL, if a single phase fault occurs
DC time constant (): 45 ms
then the total voltage appearing across PIR switch in the
MIT : 10 ms
healthy phases can go up to 2.4 p.u. (for neutral grounded
RDDS of interrupter: -100 kV/ms
system). RDDS of PIR: -130 kV/ms

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PIR resistance: 425  current), the voltage drop across the resistor will reduce. This
Line length: 591 km may result in different EIT for a given MIT and hence, may
Line capacitance: 4.38 µF lead to different PIR energy as shown in fig. 4 depending upon
switching condition. This means that testing of PIR in such
TABLE 2. Comparison of stress across PIR switch based on rated conditions laboratories may confirm its behavior for values which are
Interrupter Source CB pre- Max. voltage Energy EIT
closing on peak strike across PIR much lower than the actual scenario. Hence, such stand-alone
voltage voltage contacts tests cannot be relied upon and therefore, to confirm the PIR
(kV) (kV) (kV) (MJ) (ms) behavior, both from dielectric and thermal point of view,
100%TF 514 514 514 4 13.6 multipart testing is needed. However, before undergoing
actual tests, critical parameters of PIR which determines its
OoP 686 686 681 7 14.3
energy should be verified through testing and this will be
PCL with discussed in the next section.
line at +343 343 686 600 1.3 15.5
kV peak
III. VERIFICATION OF CRITICAL PARAMETERS FOR PIR
ENERGY
Additional calculations have been performed by taking into
The critical parameters needed for evaluation of PIR energy
account the available power of testing laboratory for different
network conditions, which are interrupter closing on: irrespective of any network conditions are: RDDS of
i) 100 % Terminal Fault (TF) with kpp = 1.5 interrupter and PIR switch, as well as, MIT. These parameters
ii) Out-of-Phase condition (OoP) with kpp = 2 should be verified by individual testing before proceeding
iii) Pre-Charged line (PCL) with kpp = 1 with complete PIR testing. This is necessary because if any of
where, kpp is first pole to clear factor. these parameters have values different from the calculated,
then PIR energy may exceed its limit, leading to destruction of
resistor discs. The MIT can be easily verified through testing
and therefore, is generally specified by the customer.
The other important parameter is the RDDS of both
interrupter and PIR switch whose verification by testing is a
little complicated. Although, they are dependent on the closing
speed of the interrupter, there will be some tolerance on the
RDDS value even for a given closing speed. If the RDDS
value is beyond this range, then the calculated PIR energy may
exceed its limit, leading to destruction of resistor discs. In
addition, theoretically calculated RDDS will be slightly
different from the practical scenario due to following reasons:
i) actual surface finish of active conductors might be different
or worse than that considered in theoretical analysis
Fig. 3. Max. Voltage stress across PIR switch ii) the influence of particle contamination is not considered in
theoretical analysis
iii) In gas (SF6) circuit breakers, there will be overpressure or
under pressure regions created during the movement of arcing
contacts, which will influence the breakdown value in those
regions
iv) Dimensional tolerance of the conductors
Therefore, theoretically calculated RDDS must be verified by
testing. This is valid for both PIR switch, as well as,
interrupter.
There are several methods of evaluating the RDDS through
testing and they are broadly classified into static and dynamic
methods. In the Static method, the arcing contacts are moved
to a desired contact position and then a voltage is applied high
enough to lead to a voltage breakdown between the contacts.
This method has to be repeated several times in order to get
Fig. 4. Comparison of PIR energy the curve for all possible voltage condition and polarities.
Several dynamic methods are known to determine the
It is seen from fig. 3 that depending on the available power RDDS. The easiest method is just to close against an applied
of the testing laboratory, the voltage drop across the resistor power frequency voltage. This method, however, will not lead
will change. With lower available power (lower short circuit to a complete RDDS since the device will prestrike only in a
certain region of the RDDS. The second method consists of

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closing against an applied D.C. voltage. If the D.C. voltage 343 kV is shown in fig. 7. The source peak voltage Vp
can be adjusted in small steps then a complete RDDS may be applied was calculated by using (1). The source impedance Zs,
reachable. The third method is to apply a voltage pulse of high resistance Rs and inductance Ls was calculated by using (2),
frequency depending on contact position. This method will (3) and (4) respectively. The capacitance of line shown in fig.
also lead to a complete RDDS but requires more complicated 7 was calculated by using (6).
test procedures and triggering devices [19].
In either method, the contact position at which the
breakdown occurs between the arcing contacts should be
noted along with the time needed to reach that contact
position. The above steps are repeated for different voltage
levels to get a curve of breakdown voltage versus time. The
most linear portion of the curve should be used to evaluate the
RDDS, which will be in “kV/ms”. Fig. 5. Circuit for closing on OoP and 100 % TF

IV. MULTIPART TESTING PROCEDURE OF PIR

Once the critical parameters needed for PIR energy are
verified, the actual capability of PIR, i.e., PIR energy rating,
should be confirmed by testing for worst network condition.
This basically consists of the proof of the thermal capacity
(required EIT) of the resistor stack and dielectric withstand
capability of the PIR switch. Testing of the complete PIR
along with interrupter is impossible due to the amount of Fig. 6. Schematic of actual circuit for closing on OoP
power needed to perform such tests. Therefore, the only
possible way to show evidence is a combination of
calculations and power tests, which is the proposed multipart
testing method of PIR. The different steps involved in
multipart testing are explained in sections A to D, which
should be compiled to give a complete picture of the whole
device.
A. Determination of EIT and PIR Energy Fig. 7. Circuit for closing on PCL at 343 kV
The EIT needs to be calculated for different network
conditions in order to determine the maximum PIR energy. V p  k pp U r 2/3
For a given MIT, resistance and RDDS of both interrupter and (1)
PIR switch, the EIT depends on the making/pre-strike instant where, Ur is the rated line-to-line (root mean square) voltage.
of the interrupter (series PIR) and power of the network.
However, this EIT cannot be tested, as will be explained in the
following sections, but only calculated. In this paper,
Zs  V
p
 2 I
r

calculations and results have been shown for a series PIR (2)
configuration as an example. The simulations are carried out where, Ir is the rated (root mean square) short circuit current.
in ATP wherein the interrupter is made to pre-strike at voltage
peak under different network conditions, which are listed in
section II B. Similar calculations can be carried out for
Rs  Z
s
1 X  s
R
s
2
interrupter pre-striking at different voltages but has not been (3)
shown in this paper. The main reason being that most where, (Xs/Rs) was calculated by using (5).
customers demand for interrupter closing on voltage peak.
Additional calculations have been done by considering the Ls   R
available source power of testing laboratories and the (4)
calculated source resistance and inductance are given in table
3 whereas EIT and PIR energy are shown in table 4 X R  2 f 
corresponding to comment column “Test Lab. 1” and “Test s s
Lab. 2. (5)
The circuit for closing on OoP and 100 % TF is shown in where, f is source frequency

 r kc   3 I c 
fig. 5. The actual scenario for closing on OoP is shown in fig.
6 wherein two sources at 180 degree out-of-phase will be Xc  U
present. However, for simplicity of calculation, a single source (6)
has been considered in ATP with source peak of same where, Ic = 400 A and kc = 1.4 as per [18].
magnitude without affecting the accuracy of the results. The In fig. 5, fig. 6 and fig. 7, the switches S1 and S2 represent
ATP circuit for closing on PCL (represented by capacitor C) at interrupter and PIR switch respectively, whereas R represents

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PIR resistance. The closing of S1 and S2 represent making proves the PIR behavior for an energy level, which is lower
instant in interrupter and PIR switch, respectively. The results than the actual network condition. Since the energy involved
for interrupter closing on OoP, 100 % TF and PCL at 343 kV in actual network condition (Case-1, Case-4 and Case-6 in
is shown in fig. 2, fig. 8 and fig. 9 respectively. In these table 3) is very high, no testing laboratory can simulate such
figures, rectified voltage is plotted only for ease of calculation. conditions. Hence, a multipart testing of PIR becomes
The PIR energy is calculated in two steps and as an example, necessary such that’s its thermal, as well as, dielectric
it will be explained for the network condition shown in fig. 8. behavior is proven for conditions similar to actual scenario.
In the first step, the EIT is calculated as shown in fig. 8a. The
interrupter is made to close at 1 p.u, (peak phase voltage),
Table 3. List of cases for EIT and PIR energy calculation in ATP
which is shown by the intersection of RDDS_cb with voltage
drop across interrupter Ucb. Then the pre-strike instant in PIR
is calculated by the intersection of RDDS_pir and voltage drop
across resistor Upir. In the second step, as shown in fig. 8b, the
PIR switch is closed at the PIR pre-strike instant to calculate
the total PIR energy, which is plotted in fig. 8c.

Table 4. EIT and PIR energy calculation in ATP for CB closing at voltage
peak

Fig. 8. CB closing on 100 % TF (Series PIR) (a) Ucb and Upir represents
voltage across interrupter and resistor respectively after corresponding
switches are closed, RDDS_cb is RDDS of interrupter, RDDS_pir is RDDS of
PIR (b) Ipir and Icb represents current through resistor and interrupter
respectively after PIR switch is closed (c) Cumulative PIR energy

Table 5. Comparison of EIT and PIR energy versus making instant of

interrupter using source model of Case-4 from table 3

Fig. 9. CB closing on Pre-Charged Line at 343 kV (Series PIR) (a) Ucb and
Upir represents voltage across interrupter and resistor respectively after
corresponding switches are closed, RDDS_cb is RDDS of interrupter,
RDDS_pir is RDDS of PIR (b) Ipir and Icb represents current through resistor
and interrupter respectively after PIR switch is closed (c) Cumulative PIR
energy
The calculated PIR energy for all the cases considered is
given in table 4. It can be observed from these results that
when the available source power of the testing laboratory is
lower than the required value (lower short circuit current), it
results in lower voltage drop across resistor compared to the
actual network condition. Thus, testing in such laboratories
B. Determination of Critical Condition for PIR
For a given design of interrupter and PIR, the maximum
PIR energy is decided by the network condition. It is observed
from table 4 that maximum PIR energy occurs for closing on
OoP (Case-4) and the minimum PIR energy occurs for closing
on PCL with 343 kV (Case-6). In addition, it is seen that
maximum EIT need not always correspond to maximum PIR
energy. For example, comparison of case-1, case-4 and case-6
from table 4 shows that maximum EIT of 15.5 ms occurs

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when interrupter closes on PCL whereas maximum PIR
energy occurs when interrupter closes on OoP condition. This
is because PIR energy depends not only on EIT but also on the
maximum voltage drop across the resistor. Here the maximum
voltage drop across resistor occurs when interrupter closes on
OoP condition. However, for a given network condition, MIT,
RDDS and available power of testing laboratory, maximum
EIT will correspond to maximum PIR energy as can be seen
from table 5.
Further, for a given network condition, the maximum PIR
energy will depend upon the making instant of the interrupter.
This is because the making instant of the interrupter will not
only decide the EIT but also the maximum voltage drop across
the resistor. As an example, the variation of EIT and PIR
energy with respect to the making instant of interrupter is
given in table 5 using source model of Case-4 from table 3.
The making instant of the interrupter is given in column 1 and
is represented as “Per Unit (p.u.)” at which the interrupter pre-
strikes. The voltage across interrupter arcing contacts during
pre-strike is given in column 2. It can be observed that the
maximum EIT and PIR energy need not correspond to
interrupter pre-strike at peak, which is 2 p.u. in this case. Here
the maximum EIT and PIR energy, which is 14.8 ms and 7.75
MJ respectively, occurs when interrupter closes at 1.9 p.u.
This majorly depends on MIT, as well as, individual RDDS
value.
The most critical case for the resistor stack (means
maximum energy and voltage drop) thus needs to be
determined from the definition of test values. Type testing of
the complete breaker, however, comprises the following test
[18]:
1) 100% Terminal Fault Switching
This test will include one closing operation under full
prestrike, where the interrupter will pre-strike at voltage peak
(for shunt configuration, PIR switch will close at voltage
peak). The second closing operation will be made at voltage
zero wherein the aim is to have current with highest
asymmetry and peak magnitude.
2) Out-of-Phase Switching
This test will include only one closing operation under full
prestrike, where the breaker will pre-strike at voltage peak (for
shunt configuration, PIR switch will close at voltage peak).
Testing for such conditions in laboratory generally includes
applying 2 p.u. (1 p.u. = peak phase voltage) on one side of the
breaker, as shown in fig. 5. Since this network condition
involves maximum PIR energy, the resistor discs need
minimum cooling time (typically some hours) depending upon
the thermal time constant of the disc material.
3) Pre-Charged Line Switching
This test is not required by [18] since CB has to undergo a
large number of operations (whether C1/C2 class CB) during
capacitive switching tests and this will lead to an abnormally
high PIR energy in a short time for which the PIR is not
designed. However, as explained in section IIA, this network
condition may lead to a maximum voltage stress across the
interrupter and should therefore, be verified through testing.
The interrupter will close at voltage peak (for shunt
configuration, PIR will close at voltage peak). Depending
upon customer requirement, there may be demand for more
than one closing operations. Since the energy involved in this
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test is very less, the thermal stability of the resistor stack is not
an issue.
The calculations for closing on PCL explained in section
IV A was based on a line without shunt compensation. In case
of a shunt compensated line, a higher overvoltage may be seen
by the interrupter or PIR switch depending upon PIR
configuration. However, as can be observed from the results in
table 4, the energy requirement for PIR is defined by OoP and
not by closing on PCL. Nevertheless, EIT and dielectric stress
across PIR switch/interrupter should be checked in such
situations.
C. Test of Pre-Arcing Behavior of PIR Switch
Based on the design (series or shunt PIR configuration),
PIR switch will experience a pre-arc with full short circuit
current or with resistor current. Both conditions need to be
shown and evaluated. Depending on the available power and
voltage output of the test laboratory, it may be possible to
perform the closing operations with resistor current (in case of
shunt PIR configuration) in a direct test circuit. The closing
with full short circuit current (in case of series PIR
configuration) together with required applied voltage is not
possible to be performed in a direct test circuit. In such cases,
it is necessary to perform this test using synthetic test methods
[20].
After the performed making operations, the dielectric
withstand capability of the PIR arcing contact gap (i.e., PIR
switch in fully open position) should be verified. For a series
PIR configuration, it is enough to check this gap with a
maximum voltage of 2 p.u. This is due to the fact that when
both interrupter and PIR switch are in complete open position,
the dielectric stress, if any, will always occur across
interrupter first since the PIR switch is shunted by the resistor
as shown in fig. 1b. Further, the 2 p.u. will always occur
in a relatively shortened PIR switch gap since the PIR contacts
will travel some distance during the time when the resistor is
inserted in the circuit. For shunt PIR configuration, the test
voltage should be as per the value mentioned in [18] i.e.,
dielectric integrity test values (80 or 90 % of switching
impulse). This is due to the fact that PIR switch is in parallel
to interrupter and hence, in open position, same voltage will
be seen by both interrupter and PIR switch as shown in fig. 1a.
D. Test of Resistor Stack
The resistor stack will experience a high thermal stress
within a very short time when closing against OoP or TF. This
withstand capability has to be proven by means of testing. It is
often not possible to test the complete resistor stack due to
lack of power in test laboratories. In addition, only direct tests
and no synthetic tests are possible because voltage, as well as,
power must be supplied at the same time by a single source
only. Therefore, one possibility to perform such tests is by
considering only a part of the complete resistor stack (pro-rata
section).
The main aim of this test is to stress a part of the resistor
stack as it would be when performing a test on the complete
stack. This means that the energy input, as well as, the time in
which the required energy input is needed should correspond
to that of a direct test. In order to do so, attention needs to be
given to the available short circuit power since this defines the
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corresponding voltage drop across the resistor as shown in
table 4. It is recommended to perform calculations by varying
the closing instant over the whole half wave of the source in
order to find the maximum PIR energy as shown in table 5.
In situations where the available test voltage of the
laboratory is less than the required voltage, the test should be
performed
with a reduced number of resistor discs since it is not possible
to do the test with the complete breaker. The reason for this is
that the MIT is not changeable and will therefore, lead to a
completely different EIT and hence, different PIR energy. As
an example, such a case has been shown in fig. 10, wherein
the test laboratory has only 50% of the voltage needed to close
on actual OoP condition (case-4 of table 4). Since only 50% of
the rated voltage is available, only half of the resistor stack is
considered so that 50 % of PIR energy should be tested, which
is 3.5 MJ (half of PIR energy needed for case-4 of table 4).
However, with the given RDDS and MIT, the outcome of such
a test would result in lower PIR energy of 2.7 MJ with EIT of
13.5 ms.
Fig. 10. CB closing against 50% OoP condition (Series PIR) (a) Ucb and Upir
represents voltage across interrupter and resistor respectively after
corresponding switches are closed, RDDS_cb is RDDS of interrupter,
RDDS_pir is RDDS of PIR (b) Ipir and Icb represents current through resistor
and interrupter respectively after PIR switch is closed (c) Cumulative PIR
energy
Fig. 11. CB closing on OoP with increased EIT (Series PIR) (a) Ucb and Upir
represents voltage across interrupter and resistor respectively after
corresponding switches are closed, RDDS_cb is RDDS of interrupter (b) Ipir
and Icb represents current through resistor and interrupter respectively after
PIR switch is closed (c) Cumulative PIR energy
0885-8977 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
7
One way to overcome this problem is by testing the resistor
stack itself, mounted on its own structure. In this case,
energization of PIR and by-passing of PIR will then have to be
done by means of auxiliary breakers. In order to do so, it is
absolutely necessary to use very precise auxiliary breakers and
furthermore, RDDS of the used auxiliary breakers must be
exactly known. This is explained in fig. 11a wherein the
RDDS of PIR switch no longer plays any role. Here the EIT is
increased to 17.3 ms to get PIR energy of 3.5 MJ and this is
achieved with the help of auxiliary breakers. Also in situations
where the test laboratory is able to supply the full voltage but
only limited power, i.e., lower short circuit current, the EIT
should be increased by means of auxiliary breaker in order to
achieve the required PIR energy.
Another important aspect is the test arrangement itself,
which should be as close as possible to the real conditions of
the circuit breaker. Special considerations should be given to
the heat transfer from the resistor blocks to the surrounding
metallic parts since these parts may acts as a heat sink. Of
course, the test should be performed in an atmosphere with
normal operating condition. For example, testing of PIR inside
SF6 breakers should be performed with SF6 gas at required
pressure. In addition, special attention must be paid to the
dielectric condition during test if the resistor blocks are in
close vicinity of conductive parts and therefore, dielectrically
stressed. Also, in case of testing with pro-rata section, special
care must be taken for the decision about the length of the
resistor stack in order to be as close as possible to the original
assembly.
V. INFLUENCE OF TOLERANCE ON PIR STRESS
The most important aspect of PIR design is to make sure
that the EIT should be within limits in order not to exceed the
energy rating of the resistor disc. The tolerances of the
following parameters majorly influences MIT, which decides
EIT:
i) Closing speed
ii) Drive condition (in case of hydraulic drive, there may be
several lock-out conditions which will define the closing
speed)
iii) Dimensional tolerance
iv) RDDS of interrupter and PIR switch
Also, the measured MIT of a breaker may vary within the
production tolerances. Therefore, to evaluate the range of MIT
for a given breaker design, a rigorous tolerance chain
calculation should be done of the complete circuit breaker
including PIR. Out of the various methods used for tolerance
chain calculation like linear, non-linear, production weight,
etc., whichever is applicable, the method that gives the
maximum or worst tolerance should be considered. This will
then decide the range of MIT and hence, EIT needed for PIR
energy calculation.
An alternative method to approximately take into account
the effect of the above tolerances on PIR energy is the
following: For a given RDDS of interrupter and PIR switch,
calculate EIT and PIR energy with different MIT values for
the worst network condition (for example, closing on OoP).
The analytical method to do so is explained in section IVA
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPWRD.2016.2519604, IEEE
Transactions on Power Delivery
and the calculations should begin with the nominal value of
MIT and must be done for both, higher and lower MIT values.
In any case, the calculated maximum energy per disc should
not exceed the limits specified by the resistor disc
manufacturer.
VI. CONCLUSION
PIR is an important component of power system, however,
complete testing of PIR is very complicated and less defined.
This is due to the large amount of power involved and limited
capability of testing laboratory. Therefore, a multipart testing
method for PIR is proposed and consists of the following in
the
given sequence:
1) Verification of critical parameters (MIT & RDDS) by
testing which determines PIR energy
2) Calculation of maximum PIR energy and EIT deciding
worse network condition to be tested
3) Calculation of new EIT and resistor stack length needed for
equivalent PIR testing based upon available source power of
test laboratory
4) Testing of new EIT and equivalent PIR energy
5) Testing of “pre-arcing” behavior of PIR switch
6) Testing of dielectric withstand capability of PIR switch.
A detailed procedure has been presented for the evaluation
of the most critical parameters of PIR along with an
explanation of all the above test procedures. This enables the
user to judge about the application of PIR, possible limitations
of PIR testing or needed action with regard to operating
conditions.
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Helmut Heiermeier was born in Hamm
Germany in 1956. He studied electro
technique with focus on energy technique
at University Gesamthochschule
Paderborn in Germany. He joined
BBC/ABB Switzerland in 1981 as
development Eng. for high voltage circuit
breaker. During this time he led several
development projects and was involved
in the evaluation of circuit breaker related problems in service.
He is involved in several international working groups such as
IEC MT 36 (IEC 62271-100),MT28 ( IEC 62271-101),IEC
62271-310, IEEE, C37.04,06,09. He is the chair of the IEEE
PC 37.010 (circuit breaker application guide). Presently he is a
Senior Principal Eng for breaker development.
Rosy B. Raysaha was born in Mumbai,
India in 1981. She is an electrical engineer
and obtained her Ph.D in Electrical Engg.
(High Voltage Engg.) from Dept. of
Electrical Engg., Indian Institute of
Science (IISc), Bangalore in 2011. She
has been working on GIS product line
since then and joined ABB India in Nov.
2012 in High Voltage Technology Centre.
During this time, she has led the project for 420 kV GIS PIR
on which a Patent has been approved. At present, she is a
R&D Engineer majorly involved with PIR and circuit breaker
development for GIS.