Beruflich Dokumente
Kultur Dokumente
BY
RISHI RATAN
THESIS
Urbana, Illinois
Adviser:
ii
To my family and friends, for their love and support.
iii
ACKNOWLEDGMENTS
iv
and friends in graduate school: Da Wei, Xu Chen, Tom Comberiate, Romesh
Nandwana, Mrunmay Talegaonkar, Yubo Liu, Ahmed Elkholy, Saurabh Sax-
ena, Tejasvi Anand, Guanghua Shu, Woo-Seok Choi, Drew Newell, Xinying
Wang, Jerry Yang and Maryam Hajimiri for always being patient to answer
all my questions, solving arcane problems during the simulation and design
process. These fine graduate students have stood by me since day one, pro-
vided constructive criticism on my work, painstakingly critiqued every figure
and most importantly constantly pushed me towards striving for nothing
short of excellence.
Furthermore, I am extremely grateful to Professor Steven Franke, Profes-
sor Christopher Schmitz, Professor Milton Feng, Professor Elyse Rosenbaum,
Professor Naresh Shanbhag, Professor Venugopal Veeravalli and Dr. Chan-
drashekhar Radhakrishnan for supporting me throughout my educational ca-
reer at UIUC and mentoring me every step of the way. Even when the chips
were down, they always believed in me and helped me gain an opportunity
to pursue my graduate studies.
I thank my family for always being by my side, motivating me to move
forward whenever I was faced with roadblocks. Lastly, I am eternally grateful
to my friends Ian Wetherbee, Rohan Bambery, Eric Iverson, Pourya Assem,
Sai Zhang, Min-Sun Keel, Anish Chivukula, Eclair Hanjing Gao, Dennis
Yuan, Jerry Sun, Nishant Nookala and Eric Kim for always standing by
me throughout my ECE career at UIUC. I am positive I have missed a few
people from the above list but I truly am very thankful to all those who I
have interacted with throughout my time at UIUC. Additionally, I am very
grateful for getting an opportunity to work with wonderful undergraduates
Rushabh Mehta, Ishita Bisht, Brady Salz, Ankit Jain, Haodong Guo, and
Pradyut Paul who have worked very diligently in getting the High Speed-
SerDes Design project off the ground from scratch.
v
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
vi
CHAPTER 8 DISCUSSION . . . . . . . . . . . . . . . . . . . . . . . 87
8.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
vii
CHAPTER 1
INTRODUCTION
1.1 Motivation
Over the last 50 years, advances in Semiconductor Fabrication Technology
(SFT) coupled with innovations in Integrated Circuit (IC) technology scal-
ing have fueled an unparalleled growth in computing. This aggressive scaling
has revolutionized every aspect of modern society and triggered an insatiable
demand for faster data rates and higher processing power resulting in clock
frequencies and corresponding data rates approaching multi-GHz and multi-
Gbps ranges in everyday computing devices like personal computers, mobile
devices, entertainment consoles and other such devices. Access to informa-
tion promptly and efficiently in terms of power and portability/ease of use
is the major driver pushing the limits of IC technology. Thus, the need
for robust, high-speed, low-power and highly integrable compact systems-
on-chip (SOCs) is paramount for inter-IC communication interfaces such as
network switches, processor/memory interfaces across backplane channels.
In order to meet this growing demand for wideband systems, the Input/Out-
put (I/O) links need to scale proportionally with the increased data-rate
scaling; however in reality the off-chip I/O bandwidth (BW) has not scaled
appropriately and has become a major bottleneck in the overall system per-
formance. Furthermore, along with the off-chip I/O BW limitations, the
channel as well as package/connector interfaces have not scaled with SFT
making the design of high-speed I/O links extremely challenging due to the
increased transmission line loss, crosstalk, and signal distortion resulting in
intersymbol interference. As the demand for high data-rate interfaces has
skyrocketed, the clock-frequencies needed to realize such systems have corre-
spondingly reached the multi-GHz range necessitating the use of phase-locked
loops (PLLs) for on-chip clock synthesis.
1
Figure 1.1: IO Link Signaling Data-Rate Trends
Figure 1.1 shows the trends in data-rate scaling of I/O high-speed signal-
ing links as forecasted by the International Solid State Circuits Conference
(ISSCC) 2011 annual semiconductor roadmapping report [5]. The key take-
away from this graph is that the data-rates in inter-IC communication links
are scaling by a factor of 2X every 4 calendar years while IO channel BW
remains the same. The I/O BW scaling problem aside, the ability to design
robust, low-jitter on-chip clock synthesizer circuits is in itself an extremely
challenging task. Though research in the field of integrated high-frequency
clocking circuits has been going on for the past two-decades and lots of in-
novative designs have come into existence, one common facet missing from
the whole paradigm is complete documentation on process of simulation us-
ing the Electronic Design Automation (EDA) tools [6]. Most of the literary
works in this area primarily focus on novel system level designs for PLL based
clock synthesizers and some go into transistor-level details of the sub-blocks;
however very rarely do any of the prominent works describe the actual sim-
ulation process. As the clock-frequencies scale and demand for robustness
in the on-chip synthesizers increases, circuit designers also need to be aware
of potential Signal-Integrity (SI) problems associated with their intricate de-
signs. Since the channel BW is essentially the same at high-frequencies of
operation the PCB traces act as transmission-lines (TLs) leading to severe
degradation in signal quality due to reflections, ringing and cross-talk ef-
fects. Thus, every integrated circuit designer will invariably face SI problems
in their design which until recently was not a concern as the frequencies
were low enough that digital design did not require a formal understand-
2
ing of signal integrity during the development as well as verification process.
Therefore, the motivation for this thesis is to bridge the gap between cir-
cuit design and simulation for signal-integrity engineers who need the basic
expertise in mixed-signal design process to be able to provide the required
assistance to IC designers on designing high-speed SI aware systems.
1.2 Outline
This thesis is organized to serve as a training manual for students pursu-
ing mixed-signal integrated circuit design as their field of study in graduate
school. The goal is for this thesis to be their go-to guide to grasp a high-level
understanding of high-speed links and learn the simulation setup/procedure
to validate PLL based clocking circuits using the popular EDA tool Cadence
Virtuoso.
3
6. Chapter 6 describes the procedure for behavioral modeling and simu-
lation using Verilog-AMS for the clock-generator circuit described in
Chapter 5.
4
CHAPTER 2
5
circuit whose purpose is to sample the received data-bit stream from the
channel and recover, both the transmitted data as well as the clock. Once
the receiver recovers the transmitted serial bit-stream it is sent to the Dese-
rializer block whose job as the name suggests is to convert the received serial
data back to its original parallel form for future interfaces.
6
various kinds of microwave losses due to impedance discontinuities between
connectors, substrate loss, cross-talk effects, reflections and ringing, all which
are difficult to predict and model [1].
Figure 2.3 [2] shows an example of the I/O link interface for a 10Gbps serial
link across a backplane channel. Notice that a clean signal when transmit-
ted across a backplane channel incurs tremendous amounts of loss from the
channel at an operating speed of 10Gbps making the signal at the receiver
virtually indistinguishable from noise and thus virtually garbage. In order
to limit the degradation of signal quality during transmission and reception,
the goal of mixed-signal designers is to design fast high-frequency clocks with
minimum timing skew at the TX end and minimal sampling errors at the RX
end.
7
them incompatible with modern processes [6]. Thus, in order to mitigate this
performance limitation and supply voltage scaling problems posed by conven-
tional parallel-link design the industry has shifted to electrical point-to-point
serial link interfaces.
Serial links occupy small area on chip and require very few I/O pins as
compared to case of parallel links because the number of pins is not directly
proportional to the number of data input/output signals. In serial commu-
nication links clock-skew is not a problem at the receiver since TX clock is
typically not forwarded to the RX. In parallel links, on the other hand clock-
skew is the major source of signal degradation at the RX side since the TX
clock and data are transmitted separately. Furthermore, cross-talk effects are
minimized in serial links due to the absence of multiple conducting channels
in parallel that each have varying signals transmitted, whereas in parallel
links this is a major problem due to the presence of capacitive/inductive
coupling between multiple conducting parallel interconnect channels.
In the consumer electronics industry, serial links have found widespread ac-
ceptance in the form of USB (Universal Serial Bus) that connects peripheral
electronic systems to computer, and SATA (Serial Advanced Technology At-
tachment) which connects the computer motherboard with mass storage de-
vices (e.g. hard disk) and PCI-Express (Peripheral Component Interconnect)
that is used to connect cards (sound, video or other) to the motherboard.
Therefore serial communication has become the solution to higher and more
efficient data transmission in order to meet the demands and trends of the
higher capacity of communication technology [7].
2.3.1 Serializer
The serializer circuit, as the name suggests, converts the input parallel-bus
data into a serial bit-stream form. It is a completely digital block and it pre-
cedes the TX driver circuit. At a fundamental level, a serializer is essentially
a Multiplexer circuit whose driving clock for the serialization process is the
TX CLK signal generated by the TX PLL.
8
2.3.2 Driver Amplifier
Driver amplifiers are found both at the TX as well as RX ends. The DA
(Driver Amplifier) is used to amplify the input serial bit-stream before it is
sent to the receiver through the channel. Another important task accom-
plished by the DA is that it provides impedance terminations that terminate
the channel input/output with 50Ω impedance.
sK
IN W& W
/W >&
sdZ>
REF
DIV рE
OUT
9
output signal outputs digital pulse-width modulated (PWM) signals to the
CP which essentially converts these digital pulses into an analog current
signal. The LF then takes the CP output current signal, low-pass filters the
high-frequency noise components and outputs a control voltage that drives
the VCO. The VCO is the most-critical component within the PLL as it is
the circuit-block that generates the final output clock that is used to drive
the digital circuits of the link. Thus, a low phase-noise VCO is of paramount
importance in the PLL as the VCO phase-noise is the dominant noise-form
in the PLL. Finally, the divider is used in the feedback loop back to the PFD
as the VCO output needs to be brought back down to the same frequency
level as the reference clock so that the loop can dynamically drive all static-
phase errors between reference clock and divider clock to zero such that
fOU T = αfREF , where α is the multiplying factor and the loop is “locked”
to output a stable clock at the desired frequency of operation. The various
intricacies involved in PLL design are covered in the remainder of the thesis.
2.3.4 Channel
Figure 2.5 [3] shows the attenuation levels a typical serial link channel incurs
as a function of operating frequency. Figure 2.6 and 2.7 show the eye diagram
outputs from a backplane channel interface at 1Gbps and 10Gbps data-rates
respectively. Notice that the eye is fully open at 1Gbps but at 10Gbps the
signal is almost indistinguishable from the noise at the receiver side due to
10
the tremendous loss and distortion incurred along the channel. The HSSL
designers need to be able to account for such losses when designing the blocks
of the HSSL at both a system as well as circuit level. As stated earlier, the
channel induced degradation is the primary limiting factor during the entire
link-design process.
In−phase Signal
Amplitude (AU)
1
−1
0 2 4 6
Time (s) −10
x 10
Figure 2.6: 1Gbps Backplane Link Eye Diagram
In−phase Signal
1
Amplitude (AU)
−1
0 2 4 6
Time (s) −11
x 10
Figure 2.7: 10Gbps Backplane Link Eye Diagram
2.3.5 Equalization
Equalization is a method of combatting the detrimental effects of intersym-
bol interference (ISI) caused by the bandlimited channel. Equalizers are
typically implemented as linear or non-linear adaptive filters. Equalization
performed before the channel is referred to as pre-emphasis and basically
involves passing the TX signal through a filter whose transfer function is the
inverse of the channel transfer function. Conversely, equalization at the RX
end is used to undo the distortion incurred in the received signal due to the
channel loss and dispersion. Most RX equalization schemes are adaptive and
11
are implemented using DSP techniques to cancel out the channel loss from
the received data-bits.
12
2.3.7 Deserializer
The deserializer circuit, as the name suggests, converts the input serial bit-
stream data back into its original parallel bus form. It is also a completely
digital block and it succeeds the RX driver circuit. Basically, the deserializer
is just a demultiplexer circuit that is driven by the clock that is recovered by
the CDR.
13
tion techniques are the biggest design challenges in HSSLs today. Robustness
therefore is the most important metric of performance for link designers. The
primary figures-of-merit (FOM) for HSSLs are bit-error-rate (BER), jitter,
crosstalk analysis and timing/noise analysis [1].
BER in modern HSSLs is typically between 10−12 and 10−15 and it is the
main metric used to signify the integrity of the received data-bits. A BER of
10−12 means that 1 bit will incur an error along the link when we transmit a
total of 1012 bits. Measurement/Estimation of BER is one of the fundamental
challenges faced by link designers because in order to accurately conclude
that the link actually has a BER of the order 10−12 , one needs to simulate a
random sequence of at least 1012 bits which even in current state-of-the art
simulators is next to impossible. Therefore, most simulators use statistical
means to collectively analyze the effects of deterministic noise sources such as
Intersymbol Interference (ISI), supply-noise, timing-jitter as well as random
noise sources like white-thermal noise and random jitter when estimating the
system BER.
A common method to measure timing jitter is to use eye-diagrams. Eye
diagrams are constructed by slicing the time-domain signal waveform into
small sections and overlaying them on top of each other such that the re-
sulting shape resembles an ‘eye’. The horizontal axis of the eye diagram
represents time and is typically one or two symbols wide, and the vertical
axis represents the amplitude of the signal. Ideally, we want the eye to be as
“open” as possible, since a larger eye opening signifies that there is a large
enough margin to meet any voltage and timing requirements needed by the
system. Quantitatively speaking, the minimum height and width of the data
at the receiver are key metrics for evaluating link performance. As link de-
signers, we want the receiver eye to be wide enough to provide adequate time
to satisfy the setup and hold requirement of the flip-flops used, and have suf-
ficient height to ensure that the voltage levels meet vil and vih requirements
of the system in the presence of multiple noise sources. Figure 2.9 [6] shows
an example of what sampling an eye with and without jitter means.
14
Figure 2.9: Eye Diagram Terminology and FOMs
15
Finally, the last major metric in calculating the timing margin of a HSSL
is the jitter. Characterization of deterministic as well as random timing jitter
in a clock output is very important to a link designer. Essentially, jitter is
the time-domain variation in the clock-signal as shown in Figure 2.10 [10].
A commonly used method for jitter calculation is to close either side of the
eye horizontally by the amount of peak clock jitter. While this method can
be helpful in evaluating the effects of jitter at the receiver end, we will show
in this paper that this is an overly optimistic approximation of noise margin
degradation for transmitter jitter. Due to the need for integration of clock
generators such as PLLs in large digital chips, clock jitter is dominated by
power-supply and substrate noise, both of which do not scale with technol-
ogy. Therefore, as data rates increase, bit-periods become shorter and the
performance of multi-gigabit links will be limited by the clock jitter, thereby
initiating the importance of accurately analyzing the effects of clock jitter on
high-speed serial links. Figure 2.11 [5] provides a summary of common jitter
profiles in a typical serial link.
16
CHAPTER 3
17
PD serves as an “error’-amplifier” in the feedback loop, thereby minimizing
the phase-difference, ∆φ, between the reference signal, Vref (t) and the os-
cillator output signal, Vout . The loop is considered to be “locked” if ∆φ is
constant with time, a result of which is that the input and output frequen-
cies are equal. In locked condition, all the signals in the loop have reached
steady state and the PLL operates as follows. The phase detector produces
an output whose DC value is proportional to ∆φ. The low-pass filter sup-
presses high-frequency components in the PD output, allowing the DC value
to control the VCO frequency. The VCO then oscillates at a frequency equal
to the input frequency and with a phase-difference equal to ∆φ. Thus, the
LPF filter generates the proper control voltage for the VCO. The VCO phase
can be seen to be an initial condition of the system, as it is independent of
the initial conditions in the LPF. Whenever two frequencies become equal
at a point in time and ∆φ has not established the required control voltage
for the VCO, the loop will continue the transient, temporarily making the
frequencies unequal again. In other words, both “frequency-acquisition” and
“phase-acquisition” must be completed. This behavior is to be expected be-
cause for lock to occur again, all the initial conditions of the system, including
the VCO output phase, must be updated [15].
The biggest pitfall of using just a PD is that it does not capture any step
changes in frequency; thus, in order to be able to track both phase and
frequency we need to use a phase-frequency detector (PFD). The purpose of
a PFD is to compare the reference clock signal and the VCO output clock
after division in both phase and frequency. These frequencies are generally
denoted by FREF and FV CO respectively. The basic structure can be divided
into logic control part and a charge pump. The charge pump is a current
source in series with a current sink and the output node is like a switch
that resides in between the source and sink. The logic part consists of two
D-Flip-Flops (DFFs) and the outputs of these DFFs control the switch of
the charge pump. Conceptually the PFD can be viewed as a state machine
with three states. The initial state is 0 and both DFFs will be reset if VCO
and reference signal are both high. In state -1 only current sink is turned
on and sinks charge out of the load, thereby decreasing the output voltage;
in state 0 current source and current sink are turned off so no charge is
injected or extracted out of the output node, thereby keeping the output
voltage unchanged. In state 1 only current source is turned on so charge can
18
be injected into the output node, thereby increasing the output voltage. The
state transitions are controlled by the edges of VCOs output and reference
signal; thus it is clear that the PFD is a purely digital circuit.
(a) (b)
Figures 3.1 and 3.2 show the block diagram of a PFD and demonstrate its
functionality. Essentially, when the reference clock is faster than the divider
clock, UP signal is High, DN signal is Low and vice versa. Note that when
both the reference and divider clocks are synchronized both UP and DN
signals are set to be High. The phase frequency detector (PFD) is a circuit
that linearly translates the phase difference into voltage signals. The ideal
average input/output relationship should be:
Ve = KP D × φe (3.1)
19
3.2.2 Charge-Pump (CP)
The charge pump is the device that translates the digital voltage signals
generated from PFD into a current signal. Since the voltage controlled os-
cillator needs a stable voltage to control the oscillating frequency, a charge
storage capacitor is needed. In order dump enough charge into the capac-
itor, a charge pump is needed here. Together with the PFD the s-domain
transform becomes the following:
iCharge P ump
KP F D = (3.2)
2π
20
Zt Zt
φout (t) = ωout (τ )dτ = KV CO vctrl (τ )dτ (3.5)
0 0
φout (s) KV CO
HV CO (s) = = (3.7)
vctrl (s) s
3.2.5 Divider
A frequency divider is needed to produce a clock signal that runs many times
faster than the reference clock. The PFD input clock and reference clock have
to be synchronized for PLL to be in locked condition. In order to perform
this task we use a fractional-N divider circuit, which divides the VCO clock
by the highest power of 2 factor to synchronize reference clock signal and the
divider output clock.
21
the loop-gain, and thus an indicator of the gain-bandwidth product of the
loop. The damping factor is inversely proportional to the loop gain. Typi-
cally, in a well designed second order system, ζ is usually greater than 0.5
√
and preferably equal to 22 so as to provide an optimally flat response. Thus,
√
K and ωLP F cannot be chosen independently; for example if ζ = 22 , then
K = ωLP 2
F
. If s → 0, we note that H(s) → 1; i.e. a static phase shift at the
input is transferred to the output unchanged. We can examine the “phase
s2 +2ζωn s
error transfer function” defined as He (s) = 1 − H(s) = ΦΦine (s)
(s)
= s2 +2ζω n s+ωn
2
22
CHAPTER 4
ĭin hW
PFD
/W
sK
ĭref E sdZ>
Z
Ͳ/W Ϯ
ϭ
ĭdiv ĭout
рE
Figure 4.1 shows the basic building blocks of a CPLL. Charge-Pump PLLs
offer many advantages over the classical voltage phase-detector PLL including
an infinite pull-in range and zero steady-state phase error. CPLLs also allow
one to use a passive filter and still have many of the benefits of using an
active filter with the voltage phase detector. The exception to this case is
when the VCO tuning voltage needs to be higher than the PLL can supply;
in this case, an active filter is necessary [15].
Phase-frequency detectors with charge-pump combination offer several ad-
vantages over the voltage charge pump and have all but replaced it. The PFD
and CP blocks are universally present in every PLL based synthesizer chip.
Using this approach completely bypasses issues of steady-state phase error
and hold-in range [10].
23
4.2 CPLL Linear Model and Analysis
W&нW
ĭe(s)
>& sK
+ Vctrl (s) <sK
ĭREF (s) + <W &;ƐͿ
Ɛ ĭOUT (s)
-
Vctrl (s)
Z
Ϯ
ϭ
Figure 4.2 shows the linear s-domain model for CPLLs. From the previous
section we can now define the open loop transfer function as follows:
KV CO
LG(s) = KP D · F (s) · (4.1a)
s
1
s + RC
= KP D · KV CO · 1
(4.1b)
C 1 +C2
C2 s2 s + RC 1 C2
1 C1 + C2
ωz = ; ωp1 = ωp2 = 0; ωp3 = (4.2)
RC1 RC1 C2
where ωugb is the open loop unity gain bandwidth and ωz < ωugb .
In order to achieve maximum phase margin, the value of C1 and C2 have
to be chosen carefully. To calculate the expression of φM max we take the
first order derivative of Eq. 4.3 with respect to ωugb and equate the result to
zero, such that: r
C1
ωugb = ωz +1 (4.4)
C2
24
Subsequently,
r
C1 1
φM max = arctan( + 1) − arctan( q ) (4.5)
C2 C1
+1
C2
C1
q
Kc = = 2(tan2 (φM ) + tan(φM tan2 (φM ) + 1)) (4.6)
C2
1 C1
C1 = ; C2 = ; (4.8)
ωz R Kc
It is vital to analytically confirm that the PLL will indeed lock when there
is a frequency step applied at the input. Without loss of generality assume
there is input frequency step ωin = ∆ω s
, then Φin (s) = ∆ω
s2
. First, obtain the
closed loop transfer function:
LG(s)
HP LL (s) = (4.10)
1 + LG(s)
Φerror (s) 1
= He (s) = 1 − HP LL (s) = (4.11)
Φin (s) 1 + LG(s)
25
Applying the final value theorem, we get the steady state error to be:
ΦFssstep
error = lim s · He (s) · Φin (s) (4.12a)
s→0
1 ∆ω
= lim s · · 2 (4.12b)
s→0 1 + LG(s) s
[RC1 C2 s2 + (C1 + C2 )s]∆ω
= lim (4.12c)
s→0 RC1 C2 s3 + (C1 + C2 )s2 + KV CO KP D s + 1
0
= (4.12d)
1
=0 (4.12e)
Eq. 4.12(a) to 4.12(e) indicate that the PLL we have designed can eliminate
any steady state phase error and relock when a frequency step is applied at
the input [8].
SΦiCP
OU T
= SiCP |N T FCP (s)|2 (4.18)
SΦΦOU
V CO
T
= SΦV CO |N T FV CO (s)|2 (4.20)
1
GLP F (s) = s (4.21)
1+ ωLP F
26
KP D KV CO
H(s) = s (4.22)
ωLP F
+ s + KP D KV CO
27
Figure 4.5: CPLL Output Noise Simulation
Figure 4.3 [8] shows the typical loop-gain and phase-margin plot for a
CPLL. Recall that phase-margin is the difference in phase between −180 ◦ C
and the phase value corresponding to ωugb . Figure 4.4 shows the typical
noise-profile for each component in a CPLL based Integer-N synthesizer [12].
Figure 4.5 shows the noise-transfer function characterization for the PLL
using the above equations implemented in MATLAB. The beauty of this
analysis is that it accurately predicts what the noise-profile for the PLL will
look like so that the designer can determine the BW specifications for the
PLL from which the rest of the Loop-Filter and VCO specifications can be
determined.
28
CHAPTER 5
5.1 PFD
Figure 5.1 shows the NAND PFD implementation used in the design of the
PLL used in this thesis. In Figure 5.2 the transistor-level implementation for
each of the circuits shown in Figure 5.1 are displayed with the appropriate
sizing.
sZ&
hW
Z^d
E
s/s
sZ& hW
s/s W&
E
29
8µm 8µm 8µm
0.18µm 0.18µm 0.18µm
8µm
4µm 0.18µm
0.18µm
4µm
0.18µm
16µm
12µm 0.18µm
0.18µm
12µm 16µm
0.18µm 0.18µm
12µm 16µm
0.18µm 0.18µm
16µm
0.18µm
One of the major challenges during the design of an efficient PFD circuit is
the “dead-zone” problem. “Dead-zone” is refers to the region wherein there
is no output for inputs. It is equal to the sum of the on-times of the pull-
up/pull-down switches in the charge-pump and is typically a problem because
the presence of dead-zone causes the PLL to operate in “open-loop” when the
phase-error is zero. One method to overcome the dead-zone issue is to ensure
that the PFD generates equal UP/DN pulses whose width is larger than the
switch-on time of the CP switches. The NAND-PFD implementation is one
example of a PFD circuit where the dead-zone issue is avoided. The D-Flip-
Flops are designed using cross-coupled NAND-latches and even though this
uses up a lot of on-chip area and burns a lot of power in the PFD circuit, the
large delay in UP/DN feedback paths allows the pulse-widths to be just larger
than the switch-on time of the PMOS/NMOS transistors that act as the pull-
up/pull-down switches in the CP. The maximum operating frequency of a
1
PFD circuit is determined by the reset path delay such that Fmax < 2TRST .
In the case of a NAND PFD circuit, TRST = 2TN AN D2 + TN AN D4 , where we
intentionally design the NAND4 circuit to have a high delay to minimize the
reset period.
30
5.2 CPs
Figure 5.3 shows the CP implementation used in the design of the PLL used
in this thesis. The transistor-level implementation is also displayed with the
appropriate sizing.
s
s
M0 M2 M0 M1
16µm 16µm 8µm 8µm
0.18µm 0.18µm 0.18µm 0.18µm
sKhd
M2 M3
M4 M6 8µm 8µm
16µm 16µm sн 0.18µm 0.18µm sͲ
hW 0.18µm 0.18µm hW
iW ITAIL = 3mA
M5 M8
8µm 8µm
E 0.18µm 0.18µm E
M1 M3
8µm 8µm
0.18µm 0.18µm
s
hW
/W
iW
/W
E
hW iW
W
E
31
to design a CP circuit that has equivalent pull-up and pull down currents and
equal on-time for the PMOS/NMOS switches. Though several CP architec-
tures exist, a ‘Bootstrapped’ CP design is used in the clock-generating PLL
studied in this thesis. The advantage of the Bootstrapped architecture is
that it allows differential current steering, it can operate with low-swing UP,
DN signals. It is thus very prominent in PLLs that use high-speed reference
clock signals. The term ‘bootstrapped’ are appropriate because the voltage
following op-amp between the pull-up and pull-down current networks en-
sures that an equal voltage level is maintained on either ends such that the
pull-up current is equal to the pull-down current.
5.3 LF
R = 5kΩ
C2 = 561.27fF
C1 = 72.766pF
>&
Figure 5.4: Loop-Filter Implementation
32
5.4 VCOs
s
M8 12µm M9 3µm
0.18µm 0.18µm
sĐƚƌů
M0 M2 M4 M6
12µm 12µm 12µm 24µm
0.18µm 0.18µm 0.18µm 0.18µm
sŽƵƚ
M1 M3 M5 M7
5µm 5µm 5µm 10µm
0.18µm 0.18µm 0.18µm 0.18µm
s
M8 12µm M9 3µm
0.18µm 0.18µm
sĐƚƌů
sŽƵƚ
sĐƚƌů ĨŽƵƚ
33
5.5 Divider
s
M0 M2 M3 M5
8µm 8µm 8µm 8µm
0.18µm 0.18µm 0.18µm 0.18µm
M1 M7 M9 Y
8µm 4µm 4µm
>< 0.18µm 0.18µm 0.18µm Y
M6 M8 M10 M11
4µm 4µm 4µm 4µm
0.18µm
0.18µm 0.18µm 0.18µm
Y Y
DFF
>< Y Y
The divider circuit consists of 3-DFFs that are connected together in the
manner shown in Figure 5.7 to realize a divide-by-8 operation. Division in
binary is essentially a left-shift operation; thus, tying the outputs of each
DFF to clock input of the next while connecting the input to the inverse of
output in a feedback ensures a left-shift operation. Since the PLL output
frequency is in the GHz range, the DFF design is very critical. To realize a
fast DFF with low clock-skew and delay a TSPC (True-Single Phase Clock)
architecture (as shown in Figure 5.6) is employed. The basic idea is that
when CLK is high transistors M1 and M9 are ON/OFF respectively and vice
versa, thereby preserving the state except when CLK goes from low to high,
in which case the output follows the data-input signal denoted by D.
34
CHAPTER 6
35
key advantage of circuit modeling using Verilog-AMS is that it provides a
single language and simulator ecosystem that can be shared between ana-
log, digital and system-level designers. Verilog-AMS leverages the superior
speed and capacity offered by traditional Verilog and allows event-driven
capabilities within analog model simulation, making it an attractive choice
when simulating highly complex mixed-signal circuits such as PLLs, CDRs,
ADCs, and DACs. The only pitfall of using Verilog-AMS is that it cannot re-
place traditional transistor level SPICE simulation completely as it does not
have synthesis capabilities like its digital counterpart Verilog. However, at
the onset of the design phase, using Verilog-AMS for circuit modeling is very
powerful for a mixed-signal circuit/system design engineer as it offers fast
prototyping/verification for behavioral level simulation, thereby expediting
the time-to-market for the system.
Verilog-AMS combines both Verilog-D and Verilog-A including a few ad-
ditional mixed-signal constructs to provide a HDL language capable of per-
forming truly mixed-signal simulation. Cadence has been the front-runner
in promoting the language making it an industry standard, and has led the
majority of the advancement efforts ever since its release in 2003. The power
of Verilog-AMS simulator in Cadence Virtuoso is that it can perform co-
simulation among behavioral analog/digital blocks described by correspond-
ing Verilog-A and Verilog-D models respectively as well as transistor-level
circuit blocks by running the Spectre simulation. When a circuit consist-
ing of transistor-level circuit elements, analog behavioral modules written
in Verilog-A and digital behavioral modules written in Verilog-D is simu-
lated, the AMS simulator in Cadence partitions the testbench into analog
and digital components. The simulator then merges the analog simulation
results from Spectre with the digital simulation results from NC-SIM and
the resulting output is plotted just like that in the case of traditional Spectre
simulation [4].
36
Figure 6.1: Verilog-AMS Sample Code
In the first line of the sample code shown in Figure 6.1 [4], we include
the ‘disciplines.vams’ header file. This file is a collection of physical signal
types that are commonly used in Verilog-AMS and are thus referred to as
‘natures’. Electrical disciplines consist of ‘voltages’ and ‘currents’ and are
used most commonly during mixed-signal system modeling where ‘voltage’
and ‘current’ are ‘natures’. Every Verilog-AMS component is defined as a
‘module’ and modules are the basic building blocks of any given Verilog-
AMS files as they describe the component being modeled. Ports are the
points where connections are made to the given component. Every port is
required to have a direction associated with it, and by default in Verilog-
AMS language there are three types of ports: input, output and inout.
The keyword electrical signifies that the signals associated with the ports
described as electrical are of ‘voltage’ and ‘current’ natures. Additionally,
analog is the keyword after which point the Verilog-AMS compiler starts
actual modeling as the logic/process starts after the ‘analog begin’. Finally,
every Verilog-AMS component code should end with the word endmodule
as it signifies the point at which the compiler stops parsing of the code [4].
37
6.4 PLL Simulation in AMS Using Cadence Virtuoso
6.4.1 PFD+CP
1. Create a new library and name it ‘PLLBehav’. Now within the Library
Manager window, click on F ile → N ew → Cell V iew and call the new
VerilogAMS file pf d. Choose the ‘VerilogAMSText’ option from the
drop-down Menu as shown in Figure 6.2. Click ‘OK’ and a text editor
window will open up.
2. Figure 6.3 shows the ‘PFD’ code used in the design. The PFD is
a completely digital circuit; thus, this code is essentially in Verilog-
D syntax where the UP, DN signals are generated by comparing the
rising edges of the flip-flops that have a CLK signal of FREF and FDIV
respectively.
38
Figure 6.3: PFD Verilog-AMS Code
3. Once you have written the code as shown in Figure 6.4, save and exit
the text editor. A pop-up window like Figure 6.4 will open up. Click
‘Yes’ to generate the symbol for the ‘pfd’.
39
Figure 6.5: PFD Verilog-AMS Schematic
40
shown in Figure 6.8(b), so click on ‘Save’ and press ‘Open’. Now a
window like the schematic view will open up but this time it will have
config in the title.
(a) (b)
8. Make sure you first ‘Check and Save’ your config file and click on
Launch → ADE to open up the ADE window.
41
9. Click on Setup → Simulator to make sure the Simulator is set to AMS.
Select the output nodes and choose a transient simulation for 100ns as
shown in Figure 6.9.
10. In the final output waveform shown in Figure 6.10 it is clear that the
PFD is functioning correctly. Notice that the UP,DN pulses are ap-
propriately modulated as ‘REF’ and ‘DIV’ signals diverge from one
another.
42
Figure 6.10: PFD Verilog-AMS Simulation Output
11. Within the ‘PLLBehav’ library follow the steps described earlier to
create a model for the CP as shown in Figure 6.11 and save the file as
‘cp’.
12. Figure 6.12 shows the ‘PFD+CP’ testbench schematic. Create a new
schematic named ‘cp test’ as well as a config file following the same
procedure as the PFD. When simulating using the ADE AMS simulator
follow the procedure similar to that shown in Figure 6.9.
43
Figure 6.12: PFD+CP Verilog-AMS Testbench
14. The purpose of the charge-pump is to convert the digital PWM signal
outputs from the PFD into a current. As seen in the code and from
the final output waveform shown in Figure 6.14, it is clear that the
44
‘PFD+CP’ is functioning correctly. When UP is high the current the
pull-up current source is on and when DN is high the pull-down current
source is on.
6.4.2 LF
We use the analog loop-filter as shown in Figure 5.4.
6.4.3 VCO
1. The VCO is the most critical component of the PLL we try to model
using Verilog-AMS because it allows us to behaviorally estimate the
jitter specifications. Within the ‘PLLBehav’ library follow the steps
described earlier to create a model for the VCO as shown in Figure
6.15 and save the file as ‘vco’. Only the white-noise jitter is considered
in this design and it is modeled by a Gaussian white-noise probability
distribution function.
45
Figure 6.15: VCO Verilog-AMS Code
2. Figure 6.16 shows the ‘VCO’ testbench schematic. Create a new schematic
named ‘vco test’ as well as a config file following the same procedure as
the PFD. When simulating using the ADE AMS simulator follow the
procedure similar to that shown in Figure 6.9.
3. Just like in the case of the ‘CP’ in the ‘config’ testbench file, if you
click on the ‘VCO’ block and press q, a window as shown in Figure
6.17 will appear. Enter the appropriate value VCO design parameters
as per the design objectives.
46
Figure 6.17: VCO Verilog-AMS Testbench Variable Setup
47
Figure 6.18: VCO Verilog-AMS Simulation Output
6.4.4 Divider
1. Divider is essential when designing a clock-generating circuit as we need
to scale down the VCO output clock to the reference frequency level
such that the two signals can be compared. Within the ‘PLLBehav’
library follow the steps described earlier to create a model for the Di-
vider as shown in Figure 6.15 and save the file as ‘div’. Figure 6.19
shows the code to implement the divider in Verilog.
48
Figure 6.19: Divider Verilog-AMS Code
3. Just like in the case of the ‘CP and VCO’, in the ‘config’ testbench file
if you click on the ‘Divider’ block and press q, a window as shown in
Figure 6.21 will appear. Enter the appropriate value of divide ratio as
per the design objectives.
49
Figure 6.21: VCO Verilog-AMS Testbench Variable Setup
50
6.4.5 Complete PLL Analysis with Jitter
1. Create a new schematic within the ‘PLLBehav’ library and name it
‘PLL’. Your schematic should look that shown in Figure 6.23. Now
create a config file for this setup and at the end your configuration
window should look like Figure 6.24.
2. Using the steps described earlier in this chapter, configure your ADE
window as shown in Figure 6.25 and simulate the circuit.
51
Figure 6.25: PLL Verilog-AMS ADE Setup
3. The PLL circuit outputs are shown in Figure 6.26. It is clear that
the PLL achieves lock within the first 100ns because in the testbench
we provide an initial condition of Vctrl = 0.9V and keep the currents
at the loop-filter capacitors at an initial condition of 0A. These initial
conditions are provided to ensure that the simulation time is small.
From the final output waveforms it is clear that the ‘PLL’ is indeed
functioning correctly.
52
4. To simulate the jitter at the VCO output during lock-condition, se-
lect the vout waveform, click on M easurements → EyeDiagram and
configure the setup as shown in Figure 6.27. Your final output should
look like that shown in Figure 6.27 once you click on ‘Plot Eye’. The
simulated edge-to-edge jitter is 0.96ps which is extremely good. How-
ever, it is important to note that this number is not realistic as we
have only accounted for random jitter caused by white-noise and the
model is only behavioral so any transistor-level non-idealities are not
captured. Nevertheless, behavioral modeling is very powerful in per-
forming rapid prototyping of the PLL circuit elements and performs a
system level noise/timing budget for the design before delving straight
into transistor level design.
53
CHAPTER 7
54
7.3 Transient, PSS and PNoise Simulation Overview
Transient response is the time-domain simulation response for a given circuit
and is used to study the time-domain behavior of voltages and currents at
any given node in a network. It is a powerful analysis method to study
amplifier circuits; however, in the case of oscillators it falls short in being
able to accurately characterize the harmonic behavior of the outputs. Thus,
to study oscillator, mixer circuits or for that matter any circuit that has a
time-varying or periodic nature, the Periodic Steady State (PSS) analysis is
the preferred method of simulation.
PSS is a large-signal analysis tool and is powerful in accurately determin-
ing the approximate small-signal period of the circuit being analyzed. It
uses the Iterative Shooting Newton method to algorithmically determine the
fundamental frequency of the circuit/system based on the input-source fre-
quency excitation. In PSS, a circuit is evaluated for one period of the target
frequency and this period is dynamically adjusted until all node voltages and
branch currents fall within a specified tolerance level. Thus, when simulating
large networks the PSS simulation often fails to converge and the time-step
needs to be manually adjusted. It is also possible that the simulator is just
not robust enough for PSS to converge if the time-step is made too small.
The first step in a PSS simulation is to perform a transient simulation on the
1
network from time t = 0 to t = ff und . The next step is then to adjust the
time-step adaptively such that the voltage and currents at stabilize within
the threshold levels set for the start and stop times of the shooting interval.
Figure 7.1 further describes this phenomenon graphically. Note: It is critical
to remember that PSS simulation is only valid, and thus will only work, if
the circuit/system being analyzed is periodic as the fundamental assumption
of PSS analysis is periodicity.
55
As discussed in earlier chapters, when studying oscillators and PLL circuits
the phase-noise is a very important parameter to calculate/simulate. Phase
noise is the most significant source of noise in oscillators, and since it is
spectrally centered around the fundamental oscillation frequency, methods
like filtering cannot eliminate it. PNoise analysis engine within Spectre is
equipped to predict the phase-noise, as well as the total-noise profile which
includes thermal, flicker and shot noise. Once the PSS simulation for the
circuit being analyzed has been completed, the PNoise analysis can be started
and it computes the frequency convention, noise-folding and aliasing effects
for the circuit/system.
56
‘analogLib’ library. You will notice all the components housed within
the ‘tsmc18rf’ library listed. The key trick to know is that you can
search for a specific component from the ‘Filter’. Search for ‘nmos2v’
and follow the steps outline in Figure 7.2.
(a)
(b)
57
3. Similarly, following the same steps as (2), add a PMOS transistor to
your schematic by choosing the ‘pmos2v’ transistor from the ‘tsmc18rf’
library. Your schematic should now look like Figure 7.3.
(a)
(b)
58
(a)
(b)
(c)
59
5. It is often advisable to add ‘Pin’ names to each of the IO terminals
in a circuit. Thus, to add pins to your schematic press P from your
keyboard or click on the pin symbol as shown in Figure 7.5 and make
appropriate connections across all IO ports. Figure 7.5 demonstrates
the steps involved in labeling wires with a circuit schematic.
Note: The ‘VDDA’ and ‘GNDA’ pins should be chosen to be ‘InputOut-
put’ when selecting the ‘Direction’ during pin creation.
6. Finally your schematic should look like Figure 7.6. Now click on ‘Check
and Save’ icon (as shown in Figure 7.7) in the toolbar so that you can
move onto the next step of creating a symbol for the inverter schematic.
60
7.4.2 Creating a Symbol
1. When dealing with large circuits its often advisable to generate symbols
for each sub-circuit in the design and perform all simulations by plac-
ing the corresponding symbols in a testbench. Figure 7.8 summarizes
the steps involved in generating a symbol from the inverter schematic
designed in the previous section.
(a)
(b)
2. Once you create the symbol it will pop up in a new window. By de-
fault Cadence will generate a rectangular symbol, but you can edit the
61
generated symbol as per your needs. In our case we will edit the sym-
bol shape to make it resemble the traditional inverter symbol used in
conventional system design (as shown in Figure 7.9). To edit the shape
use the ‘Edit Pallete’ as shown in Figure 7.9(a) via a red highlighted
box.
(a)
(b)
62
2. Create a new schematic and save it as ‘pfd’. Place the ‘nand2’,‘nand3’,‘nand4’
and ‘inv’ symbols in the schematic and connect the four components
in the NAND-PFD form as shown in Figure pf d.
3. Create a new schematic and save it as ‘bias amp’. Now recreate the
biasing op-amp that is part of the charge-pump schematic shown in
Figure 5.3.
4. Create new schematic and save it as ‘cp’. Place the biasing amplifier
created in the previous step and recreate the charge-pump circuit shown
in Figure 5.3 from section 5.2.
6. Create a new schematic and save it as ‘vco’. Recreate the VCO circuit
shown in Figure 5.5 from section 5.4.
7. Create a new schematic and save it as ‘dff’. Now recreate the biasing
D Flip-Flop that is part of the divider schematic shown in Figure 5.6.
from section 5.5.
63
(a) (b)
(c)
64
Figure 7.11: PFD+CP+Filter Testbench
Now create a new schematic and name it ‘Tb vco’. This will be the test-
bench schematic from which we will run all our simulations to test that the
VCO is functioning as expected. Insert ‘vdc’, ‘gnd’ and two ‘vdc’ from the
Component Library by navigating to the ‘Analog Parts’ library. The initial
conditions to be set for VDD are same as shown in Figure 7.10(a), while for
the second ‘vdc’ source the DC voltage should be set to a parametric variable
‘vctrl’. Figure 7.12 shows what your testbench schematic should look like at
the end of this step.
Finally, create a new schematic and name it ‘Tb div’. This will be the
testbench schematic from which we will run all our simulations to test that
the VCO is functioning as expected. Insert ‘vdc’, ‘gnd’ and a ‘vpulse’ from
the Component Library by navigating to the ‘Analog Parts’ library. The
initial conditions to be set for VDD are same as shown in Figure 7.10(a),
while for the second ‘vpulse’ source they are shown in Figure 7.13. Figure
7.14 shows what your testbench schematic should look like at the end of this
step.
65
Figure 7.13: Vpulse configuration for Divider
66
7.4.5 Circuit Simulation Using Spectre
2. Make sure you first ‘Check and Save’ your testbench schematic and
click on Launch → ADE to open up the ADE window as shown in
Figure 7.15.
(a)
(b)
67
4. Now click on Setup → M odel Libraries to configure the Spectre model
files. Figure 7.16 shows the path you need to browse to in order to get
the correct model files for the PDK. You most likely would not need to
manually type the model file paths as Virtuoso should take care of it,
but in case you do the path is listed.
(a)
(b)
68
2. In ADE window click on the AC,DC,Tran icon on the right pane.
Choose the ‘tran’ simulation type, pick the stop time to be 100ns and
choose ‘moderate’ in the ‘Accuracy details’.
3. Click on V ariables → Copy F rom Cellview and insert the filter pa-
rameters as shown in Figure 7.17.
4. Click on the green ‘Play’ button to run the simulation and the plots
should automatically pop up in a new output window. If you right click
on the name of the signal listed in the left panel, you can navigate to
options that change the thickness and color of the output waveform.
Additionally, right-clicking anywhere on the output window and navi-
gating to ‘Graph Properties’ allows you to alter the background color
as well.
5. Your final output waveform should look like that shown in Figure 7.18.
Notice that the UP,DN pulses are appropriately modulated as ‘REF’
and ‘DIV’ signals diverge from one another; thus, the PFD is indeed
functioning correctly.
69
Figure 7.18: PFD Spectre Simulation Output
3. Click on the green ‘Play’ button to run the simulation, and the plots
should automatically pop up in a new output window. If you right-click
on the name of the signal listed in the left panel, you can navigate to
options that change the thickness and color of the output waveform.
Additionally, right-clicking anywhere on the output window and navi-
gating to ‘Graph Properties’ allows you to alter the background color
as well.
70
Figure 7.19: VCO Testbench ADE Window
4. Your final output waveform should look like that shown in Figure 7.20.
Notice that the output node voltage ‘vout’ is oscillating thus the VCO
is indeed functioning correctly.
71
Figure 7.21: Vctrl Parametric Analysis Setup
To run the parametric analysis, click on the ‘Play’ within the Parametric-
Analysis window. This setup is basically going to run the transient
simulation TStepSize
o−F rom
times by varying the control-voltage input to the
VCO.
6. To plot frequency vs. Vctrl and KV CO vs. Vctrl we need to use the
‘Calculator’ tool in-built within ADE. Click on T ools → Calculator.
The Calculator window as shown in Figure 7.22 will open up and within
it now you should select ‘Vt’ from the toolbar. The schematic will
open up, so within the schematic select the ‘vout’ node. From the
‘Function-Panel’ within the Calculator window choose the ‘frequency’
and ‘average’ functions to make up the function shown in Figure 7.22.
Now go back to the ADE window, click on the right-pane and select
the ‘Pick-Outputs’ button. A window will pop up so within it select
‘Get-Expression’ and name it ‘freq’. This will bring the expression you
just created in the Calculator so that you can plot it. Conversely, you
can also click on the ‘plot’ button shown in the red-box in Figure 7.22
to plot the expression; however, doing so makes the title of plot look a
little too crammed.
72
Figure 7.22: ADE Calculator
Figure 7.23: Frequency vs. Vctrl and KV CO vs. Vctrl Simulation Plots
73
The KV CO calculated in Figure 7.23 is the value used to calculate the
required charge-pump current as well as C1 and C2 values from the
loop-filter. In our case, the VCO output frequency is 1.675GHz with a
Vctrl=0.9V and a KV CO = 652.106MHz/V.
9. To run the PNoise simulation, in the ADE window click on the AC,DC,
Tran icon on the right pane. Choose the ‘pss’ simulation type, pick the
parameters using those shown in Figure 7.24(b). Its critical to note that
the phase-noise in the VCO is only dominant in the low-pass thus we
limit our simulation frequency range to be from 1kHz to 10MHz as after
the 10MHz the phase-noise will not cause any significant degradation
to oscillator output performance. Note: To view the PNoise simulation
results in the main ADE window click on Results → Direct P lot →
M ain F orm at which a window like Figure 7.25. Choose ‘Phase-Noise’
and click on the ‘Plot’ button.
74
(a) (b)
The output waveform for the simulated phase-noise will look like Figure
7.26. In our case, we find that the Phase-Noise at a 1MHz offset is
equal to -94.32dBc/Hz, which is very reasonable for a ring-oscillator
type single-ended VCO topology.
75
Figure 7.26: VCO Phase-Noise Simulation Plot
3. Click on the green ‘Play’ button to run the simulation and the plots
should automatically pop up in a new output window.
76
(a)
(b)
4. Your final output waveform should resemble Figure 7.27. Notice that
each half-wave of the output pulse comprises of four half-pulses of the
input, meaning the period of the output pulse is one-eighth of the input
pulse period. Thus, our divider is functioning properly in that it divides
the input pulse frequency by 8 with a small setup-time delay of 209ps.
77
7.4.10 Complete PLL Schematic and Testbench
1. Using the steps mentioned in the subsections above create new schematic
and save it as ‘PLL’.
2. Place the ‘pfd’, ‘vco’ and ’div’ symbols in the schematic, connect the
components in together and generate a symbol for the full PLL schematic
as shown in Figure 7.28.
3. Create a new schematic and save it as ‘Tb PLL’. Design the testbench
schematic as shown in Figure 7.29.
4. In the PLL testbench choose the ‘Vref’ using the ‘Vpulse’ source within
analogLib and configure it as shown below in Figure 7.30.
78
Figure 7.30: Vpulse Configuration for PLL Testbench
79
3. Click on the green ‘Play’ button to run the simulation and the plots
should automatically pop-up in a new output window.
4. Your final output waveform should look like that shown in Figure 7.32.
Notice that the VCO input control voltage ‘vctrl’ is essentially flat and
settled thus the PLL is in steady-state lock state.
80
Figure 7.33: PLL Vctrl Voltage before Lock
81
you just created in the Calculator so that you can plot it.
7. To run the PNoise simulation, in the ADE window click on the AC,DC,
Tran icon on the right pane. Choose the ‘pss’ simulation type, pick the
parameters using those shown in Figure 7.35(b). It is critical to note
that the phase-noise in the VCO is the dominant source of phase-noise
in the complete PLL, and since VCO noise is typically most prominent
at a 1MHz offset, we limit our simulation frequency range to be from
1kHz to 10MHz as after the 10MHz the phase-noise will not cause
any significant degradation to oscillator output performance. One key
difference between the PNoise setup and VCO is that now the phase-
noise of interest is of the 8th relative harmonic to the fundamental
reference frequency because we have a divider ratio of 8 in our PLL.
82
(a) (b)
The output waveform for the simulated phase-noise will look like Figure
7.36. In our case, we find that the Phase-Noise at a 1MHz offset is
equal to -113.31dBc/Hz, which is very reasonable for an Integer-N clock
synthesizer PLL with an output frequency of 1.6GHz in steady-state.
83
Figure 7.36: PLL Phase-Noise Simulation Plot
8. Since clock generator circuits are responsible for generating the system
master-clock, the timing (deterministic) jitter as well as random jitter
are key figures-of-merit to minimize clock-induced timing errors during
transmission as well as reception of digital data bits. In order to char-
acterize the deterministic timing jitter we plot the PLL eye diagram
for a small time-interval once the PLL is in lock condition. Similar
to the frequency measurement, we plot the eye diagram by exporting
the ‘vout’ curve into Calculator and using the ‘eyeDiagram’ function
as shown in Figure 7.37.
In Figure 7.38 we see that the output voltage eye for the PLL has some
deterministic timing jitter associated with it.
84
Figure 7.38: PLL Output Eye Diagram Plot
85
with jitter, navigate to Results → Direct P lot → M ain F orm from
the main ADE window and a window like Figure 7.40 will pop up.
Choose ‘Jee’ and pick an event-time at a point where PLL is in steady-
state lock. You can also choose a specified BER. In modern links the
BER is typically 10−12 , but we plot the jitter over various BER ranges
as shown in Figure 7.41.
86
CHAPTER 8
DISCUSSION
8.1 Conclusion
Overall, thus far in this thesis the foundational motivation for the use of
High-Speed Serial Links has been described, fundamentals of PLLs as well
as Charge-Pump PLLs have been covered, and an in-depth step-by-step tu-
torial on design/simulation of an on-chip clock synthesizer at both a be-
havioral level using Verilog-AMS and transistor level using Cadence Spectre
have been described. The designed PLL based clock-generator circuit de-
scribed in Chapter 5 operates at an output frequency of 1.6GHz at lock with
-113dBc/Hz phase-noise, 5.62ps deterministic jitter and 5.27ps edge-to-edge
random jitter at a BER level of 10−12 . Although many design improvements
can be made at the circuit level to optimize the phase noise and jitter per-
formance of the clock-generator circuit, the motivation for this thesis was to
provide a tutorial style training manual for a student pursuing mixed-signal
IC design at the beginning of their graduate studies; thus, the circuits used
for the Integer-N synthesizer are very basic/standard. In this last chapter
to conclude the thesis, a summary of future design improvements for the
circuit designed/simulated in this thesis is outlined from both a system as
well as circuit architecture level. Lastly, an outline of the potential areas of
research to explore in the field of high-speed serial links design with a signal
integrity focus is presented. Often times when pursuing graduate work in
a diverse and mature field of Electrical and Computer Engineering such as
Mixed-Signal Circuit design, especially with a focus on Signal Integrity, a
new student needs some guidance and initial training to jump-start their ca-
reers. Therefore, the final section of this thesis concludes with a few words of
advice for new students pursuing this field of study to enable them in solving
unexplored areas within this field.
87
8.2 Future Work
88
7. The industry-wide trend is to move towards all-digital PLLs. Digital
PLLs offer many advantages over analog PLLs mainly in the fact that
they eliminate the need for an analog loop-filter as well as a charge-
pump, thereby saving area and power consumption. The disadvantage
currently however is that quantization noise associated with the Time-
to-Digital Converter (TDC) inside a digital PLL severely degrades the
phase noise of the system. Thus, even the current state-of-the-art
DPLLs are no match in terms of spectral purity performance at high-
speeds compared to the analog PLLs. However, with improvements
in transistor scaling and machine learning algorithmic noise-tolerance
methodologies in digital signal processing, as well as stochastically en-
hanced circuit design techniques, the future really lies in the study of
synthesizable DPLLs. Thus, this area of study should definitely be of
utmost priority while performing research on clocking circuit design for
high-speed serial link applications [11, 12].
89
which is actually random in nature. Furthermore, the frequency-dependent
dielectric-losses experienced along these PCB substrates are difficult to char-
acterize due to lack of the required sophistication in measurement techniques
as well as statistical modeling. Measurement is a challenge because for ac-
curate models the setup needs to be passive as well as causal, both of which
are very difficult to ensure in practice. Therefore, statistical modeling of the
substrate effects would be extremely valuable to enhance the understanding
of the channels used in high-speed interface systems. Recall that a backplane
or PCB trace can essentially be treated as a transmission line; thus, being
able to quantitatively characterize propagation delay, system characteristic
impedance, as well as discontinuities during high speed signaling will be very
valuable in easing out equalization requirements on both TX as well as RX
sides [13].
Overall link performance is analyzed in terms of the TX/RX timing jitter
as well as BER specifications. Since the channel is fixed, as mentioned earlier,
one prominent method to combat the jitter and ISI-inducing effects of the
channel is to perform equalization. Sophisticated TX pre-emphasis equaliza-
tion and RX side adaptive DFE are vital to link designers as the data rates
approach the Tb/s ranges over the upcoming years while the off-chip I/O
BW remains about the same. Lastly, formulation of a robust statistical BER
analysis and time-domain empirical jittery analysis framework involving all
interference sources for any given HSSL will be key to fully characterizing the
non-idealities present in links today without the need to over/under design
at a circuit level.
90
themselves with Behavioral modeling as well as basics of transistor-level de-
sign and simulation analysis so that they explore new HSSL architectures
that have high signal integrity even at multi-GHz to THz speeds.
Ideally, in order to make meaningful contributions in the field of HSSL
designs, a strong knowledge-base in fields of Integrated Circuits, Electromag-
netics, RF/Microwave theory and Digital Signal Processing is key. Thus, at
the onset of their graduate career students performing research in the area
of robust, fast-signaling HSSLs should take the fundamental graduate-level
courses in areas of Digital IC Design, Analog IC Design, Phase-Locked Loop
Design, Electromagnetics and DSP. Lastly, ability to exercise the EDA tools
like Cadence Virtuoso, Agilent ADS, Ansys HFSS as well as programming
in MATLAB and Verilog are essential in order to gain hands-on experience
and perform rapid-prototyping of new research ideas.
91
APPENDIX A
A.1 Introduction
The motivation for this manual is to provide a step-by-step tutorial on in-
stalling Cadence Virtuoso IC 6.15 tools from scratch, configuring the envi-
ronment and using the tool to design and simulate circuits. In this short-
tutorial users are exposed to the complete steps involved in configuring their
machine to run the Cadence Virtuoso IC 6.15 design environment along with
its ancillary softwares, converting their host computer into a server, remotely
connecting to it and launching the Virtuoso simulator engine from the termi-
nal window followed by a detailed guide to create their own custom circuits
and simulate them using the Cadence Spectre circuit simulator.
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A.2 Environment Setup
2. Once you have installed the OS, make a new directory under the path
/home/EEAPPS and name it C ADENCE INSTALL. In this tutorial
we will be installing ‘Virtuoso IC6.15’ suite, ‘MMSIM 11.1’ (required for
Spectre/Spectre-RF simulators), ‘IUS8’ (used for Verilog simulations in
Cadence Design Suite), ‘HSPICE’ and a few ‘PDKs’ (Process Design
Kit). Download the Cadence Virtuoso IC6.15 files (from your ftp file
sever) and store them in your computer under /home/EEAPPS/CA-
DENCE INSTALL/IC615 folder. This folder is the location where you
will keep the raw installation files during installation.
Note: When you are downloading your Cadence Virtuoso files from
your ftp server location they will most likely be in tar file formats.
You will have 7 files for Base version and 8 files for the Hotfix ver-
sion. First download them into your Downloads folder and then extract
the files one by one into the /home/EEAPPS/CADENCE INSTALL.
Make sure while you untar your files you ’untar’ each ‘Base’ file into
the same folder and each ‘Hotfix’ file into the same folder so at the
end of the whole process you will have two folders inside the ‘CA-
DENCE INSTALL’ folder named IC06.15.011 lnx86.Base and IC06.15.132-
615 lnx86.Hotfix . Although all the installation will be performed from
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the Hotfix files it is very important to also have the Base files ex-
tracted as a path to them will be needed during the installation setup.
94
Figure A.1: Installing Virtuoso from Installscape Step 1
8. You will now see the following instructions so follow the steps indicated
below very carefully:
9. Now a window like Figure A.1 will pop up so follow the instructions
shown in it to browse into the correct folder that contains the installa-
tion files.
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10. From this point onwards follow the instructions shown in Figures A.2
through A.14 very carefully to complete the installation process for
Virtuoso. Make sure you do exactly as shown in these figures to ensure
the software gets installed properly.
11. Once you reach the last step as shown in Figure A.14 hit ‘Done’.
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Figure A.3: Installing Virtuoso from Installscape Step 3
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Figure A.5: Installing Virtuoso from Installscape Step 5
98
Figure A.7: Installing Virtuoso from Installscape Step 7
99
Figure A.9: Installing Virtuoso from Installscape Step 9
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Figure A.11: Installing Virtuoso from Installscape Step 11
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Figure A.13: Installing Virtuoso from Installscape Step 13
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A.2.2 Installing MMSIM (Spectre/SpectreRF/HSpice)
1. Now that you have installed virtuoso in order to actually use the
HSPICE or Spectre simulation engines you need to install the MM-
SIM package.
2. Download the MMSIM installation files from your ftp server and keep
the tar files in the Downloads folder. You will have 3 files for Base ver-
sion and 3 files for the Hotfix version. Extract the files one by one into
the /home/EEAPPS/CADENCE INSTALL. Make sure that while you
untar your files you ‘untar’ each ‘Base’ file into the same folder and each
‘Hotfix’ file into the same folder so at the end of the whole process you
will have two folders inside the ‘CADENCE INSTALL’ folder named
MMSIM11.10.214 lnx86.Base and MMSIM11.10.617 lnx86.Hotfix [14].
Although all the entire installation will be performed from the Hotfix
files it is very important to also have the Base files extracted as a
path to them will be needed during the installation setup just like you
did during Virtuoso installation.
3. Open up the terminal window and create a new directory inside the
CADENCE INSTALL folder by typing in mkdir -p /home/EEAAPS/-
CADENCE INSTALL/MMSIM11.1/ . Now move the extracted Base
and Hotfix folders to the ‘MMSIM11.1’ folder you just created.
5. You will now see the following instructions so once again follow the
steps indicated below very carefully:
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6. Now a window like Figure A.15 will pop up so follow the instructions
shown in it to browse into the correct folder that contains the installa-
tion files.
7. From this point onwards follow the instructions shown in Figures A.16
through A.22 very carefully to complete the installation process for
Virtuoso. Make sure you do exactly as shown in these figures to ensure
the software gets installed properly.
8. Once you reach the last step as shown in Figure A.22 hit ‘Done’.
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Figure A.16: Installing MMSIM from Installscape Step 2
105
Figure A.18: Installing MMSIM from Installscape Step 4
106
Figure A.20: Installing MMSIM from Installscape Step 6
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Figure A.22: Installing MMSIM from Installscape Step 8
9. Now that you have installed both Virtuoso and MMSIM the most crit-
ical step is to configure the environment variables correctly. In order to
do so you will need to change your OS’s shell to bash. To figure out the
current shell of your OS open up a terminal and type in echo $SHELL.
To change the shell to bash if it is not set by default type in chsh -s
/bin/bash. If you actually were successful in changing the shell type in
echo $SHELL, and you should get /bin/bash as an output.
10. Open up your current bash file by typing gedit .bashrc & in the terminal
window. Now replace the text with that of Section 2.3. Save the
updated file and close it.
11. In the terminal window type in source .bashrc to update your bash
settings.
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A.2.3 Installing a PDK
1. Download the PDK from your foundry vendor and extract the files in
a new directory called P DK under the path: /home/EEAPPS .
3. Copy the cds.lib file from the PDK you installed above and open it up
in a text editor.
4. Make sure your ‘cds.lib’ has the following items before you launch vir-
tuoso. We have to do this to include the in-built libraries that come
with the Virtuoso software.
1. Windows OS Users:
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net/projects/xming/files/Xming-fonts/]
Note: Without installing Xming you will not be able to open Vir-
tuoso or for that matter any application with a GUI.
(c) Launch your SSH client, type ssh -X username@natcsi.ece.illinois.edu,
hit ‘Enter’. You will prompted to type in a password so type it in
and again hit ‘Enter’. Now you can follow the steps outlined in
Figure A.23.
(a) Install XQuartz 2.7.5 for Mac OSX if you are using OSX Moun-
tain Lion or later. If you have an older OS then you will already
have X11 pre-installed in your system. Check your ‘System Pref-
erences’ to check whether X11 is turned on.
Note: Without installing XQuartz or enabling X11 (depending
upon your OSX version) you will not be able to open Virtuoso or
for that matter any application with a GUI.
(b) Launch your SSH client and type ssh -X username@natcsi.ece.illinois.edu,
hit ‘Enter’. You will prompted to type in a password so type it in
and again hit ‘Enter’. Now you can follow the steps outlined in
Figure A.23.
3. Linux OS Users:
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A.2.5 Configuring Bash Environment
# . bashrc
# Source g l o b a l d e f i n i t i o n s
i f [ −f / e t c / b a s h r c ] ; then
. / etc / bashrc
fi
# User s p e c i f i c a l i a s e s and f u n c t i o n
a l i a s mat=‘cd /home/ r i s h i / matlab ; matlab &’
a l i a s c s c o p e =‘/home/EEAPPS/ Cscope / a i b i n / cscope ’
################# Hspice ###################
SYNOPSYS HOME=/home/EEAPPS
HSP HOME=$SYNOPSYS HOME/HSPICE
SCL HOME=$SYNOPSYS HOME/SCL
HSP BIN=$HSP HOME/ h s p i c e / bi n
SCL BIN=$SCL HOME/ l i n u x / bi n
export LM LICENSE FILE=/home/EEAPPS/HSPICE/ linmac . dat
export PATH=${HSP HOME}/ h s p i c e / bi n :$PATH
export PATH=/home/EEAPPS/ Cscope / a i b i n / :$PATH
################## IC ######################
export MMSIM ROOT=/home/EEAPPS/MMSIM
export OA HOME=/home/EEAPPS/ IC615 / oa
export CDSHOME=/home/EEAPPS/ IC615
export CDSDIR=/home/EEAPPS/ IC615
export CDS ROOT=/home/EEAPPS/ IC615
export CDS INST DIR=//home/EEAPPS/ IC615
export DD DONT DO OS LOCKS=SET
export CDS LIC FILE=5280 @cadence . w e b s t o r e . i l l i n o i s . edu
export CDS Netlisting Mode = ‘ ‘ Analog ”
e x p o r t PATH=${CDS INST DIR}/ t o o l s / bi n :$PATH
e x p o r t PATH=${CDS INST DIR}/ t o o l s / d f I I / bi n :$PATH
e x p o r t PATH=${CDS INST DIR}/ t o o l s / p l o t / b in :$PATH
e x p o r t PATH=${CDS INST DIR}/ t o o l s / d r a c u l a / bi n :$PATH
e x p o r t PATH=${CDS ROOT}/ t o o l s / bi n :$PATH
e x p o r t PATH=${CDS ROOT}/ t o o l s / d f I I / b in :$PATH
e x p o r t PATH=${CDS ROOT}/ t o o l s / d r a c u l a / bi n :$PATH
111
e x p o r t PATH=${CDS ROOT}/ t o o l s / p l o t / b in :$PATH
e x p o r t PATH=${CDS ROOT}/ t o o l s / i c c r a f t / b in :$PATH
e x p o r t PATH=/home/EEAPPS/ I n s t a l l S c a p e / i s c a p e / b in :$PATH
e x p o r t PATH=${MMSIM ROOT}/ t o o l s / d f I I / b in :$PATH
e x p o r t PATH=${MMSIM ROOT}/ t o o l s / s p e c t r e / bi n :$PATH
e x p o r t PATH=${MMSIM ROOT}/ t o o l s / u l t r a s i m / b in :$PATH
e x p o r t PATH=${MMSIM ROOT}/ t o o l s / bi n :$PATH
e x p o r t CDS AUTO 64BIT=ALL
e x p o r t CDS LOAD ENV=CSF
e x p o r t EDITOR=/u s r / bi n / g e d i t
################ IUS #######################
e x p o r t CADENCE CURR IUS=$SYNOPSYS HOME/ IUS08 . 2 0 . 0 1 5
e x p o r t PATH=${CADENCE CURR IUS}/ t o o l s . l n x 8 6 / bi n :$PATH
e x p o r t PATH=${CADENCE CURR IUS}/ t o o l s / bi n :$PATH
e x p o r t PATH=${CADENCE CURR IUS}/ b i n :$PATH
################## MATLAB ###########
e x p o r t PATH=/home/MATLAB/R2013b/ bi n :$PATH
Note: If you want to manually add a library that you copied from
an external source into your Cadence work directory you would need
to edit the cds.lib file found in your work directory folder by opening
it in a text-editor.
112
Figure A.24: Launch Instructions for Library Manager
113
(a) Create New Library
(a) (b)
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A.3 Common Troubleshooting Tips
Some of the most commonly recurring errors are discussed below along with
the possible solution to resolve them:
2. When sharing libraries among users within a server make sure you
add the library name in the ‘cds.lib’ file contained in your cadence
launch directory. Additionally, make sure while copying the files, the
destination user has write/edit privileges as lack of the write permission
will limit edit capabilities within virtuoso.
115
REFERENCES
[9] U.Ku-Moon. P.K. Hanumolu, “Effect of power supply noise on ring osc
phase noise,” 2004. [Online]. Available: http://web.engr.oregonstate.
edu/∼moon/research/files/newcas04 supply.pdf
116
[10] M. Mansuri, “Low-power low-jitter on-chip clock generation,”
Ph.D. dissertation, Univ. of California, Los-Angeles, 2003.
[Online]. Available: http://www.ece.tamu.edu/∼spalermo/ecen689/
pll thesis mansuri ucla 2003.pdf
[13] J. Fan et al., “Signal integrity design for high-speed digital cir-
cuits:progress and directions,” IEEE Transactions on Electromagnetic
Compatibility, vol. 52, no. 2, pp. 392–400, 2010.
installing cadence.pdf
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