Introduction to

Microprocessor

Presented By:-
Asish Ku Dash
Email-id:- asishsima@gmail.com
Digital Computer
 A digital computer is a programmable
machine specially designed for making
computation
 Its main components are
 CPU (Central Processing Unit)
 Memory
 Input device
 Output device
CPU
 The major sections of a CPU
 Arithmetic and Logic Unit (ALU)
 Accumulator
 General and Special purpose registers
 Timing and Control Unit
CPU
 The function of an ALU is to perform arithmetic
operations such as addition and subtraction; and
logical operations such as AND, OR and
EXCLUSIVE-OR
 Timing and control unit controls the entire operations
of a computer
 The accumulator is a register, which contains one of
the operands and stores results of most arithmetic
and logical operations
 General purpose registers are used for temporary
storage of data and intermediate results while
computer is making execution of a program
 Special purpose registers are used by the
microprocessor itself
Memory & I/O
 The memory is a storage device. It stores
program, data, results etc.
 The computer receives data and instructions
through input devices.
 The computer sends results to output
devices.
Microprocessor
 With the advent of LSI and VLSI technology it
became possible to build the entire CPU on a
single chip IC.
 A CPU built into a single LSI/VLSI chip is
called a microprocessor.
 A digital computer using microprocessor as
its CPU is called a microcomputer.
Microprocessor
 The term micro initiates its physical size; not
it’s computing power.
 Today the computing power of a powerful
microprocessor approaches that a CPU on
earlier large computer.
 The main sections of a microprocessor are:
ALU, timing and control unit, accumulator,
general purpose and special purpose
registers.
Early microprocessors
 PMOS technology – slow and interface with TTL family
 4 bit processor
 Instructions were executed in about 20 µs.
 Intel 4004 the first microprocessor introduced in the year 1971.It has
4K nibbles address space.
 Intel 8008 was introduced in the year 1972 which can manipulate a
whole byte.
 16Kbytes address space
 50,000 operations/second.
N-channel MOSFET
 1970.
 Faster than P-MOS.
 Work with +ve supply; easy to interface with TTL.
 1973 Intel 8080 MP.
 500,000 operations/second.
 64K bytes memory.
 Upward software compatible with 8008.
 Other brands are MC6800, Fairchild’s F-8 etc.
Basic types of MP
 Two types
 Single component microprocessors
 Bit sliced microprocessors
Single component M Computer
 Composed of
 A processor
 read only memory (for program storage)
 Read/Write memory (for data storage)
 Input/output connections for interfacing
 Timer as event counter
 Intel 8048, Motorola 6805R2.
 Oven, washing machine, dish washer etc.
Modern MP
 8, 16, 32, 64 bits are available.
 Intel 8085, Motorola 6800 – 8 bit word 16 bit
address.
 Intel 8088, 8086, Motorola 68000 – 16 bits word,
20 bits address.
 80186 – never used.
 286 – real mode and protected mode; 16MB
memory
 386 – paging, 4GB memory, 32 bits word
 486 – math coprocessor, L1 cache
Modern MP
 Pentium
 64 bits i/o off the chip but process 32bits word, exception floating
point processed 64 bits, cache doubled, instruction pipelining.
 Pentium Pro
 L2 cache, Improved pipelining
 Pentium MMX
 Multi-Media extensions, 57 new inter instruc mostly used for
multimedia programming
 Pentium II, III, IV
 Pentium pro with MMX tech, increased L2 cache, full 64 bit
operation
 RISC
 Reduced instruction set processor, uniform length instruc, faster
in operation, cannot perform may different thing as CISC.
8085 Microprocessor
 Intel 8085 is an 8-bit, N-channel Metal Oxide
semiconductor (NMOS) microprocessor
 It is a 40 pin IC package fabricated on a single
Large Scale Integration (LSI) chip
 The Intel 8085 uses a single +5V DC supply for its
operation
 Its clock speed is about 3MHz
 The clock cycle is of 320 ns
 The time for the clock cycle of the Intel 8085 is 200
ns
 It has 80 basic instructions and 246 opcodes
8085 Architecture
ALU
 The ALU performs the following arithmetic and
logical operations.
 Addition
 Subtraction
 Logical AND
 Logical OR
 Logical EXCLUSIVE OR
 Complement (logical NOT)
 Increment (add 1)
 Decrement (subtract 1)
 Left shift
 Clear
Register Set
General Registers
 The 8085 has six general-purpose registers to store
8-bit data; these are identified as B, C, D, E, H, and
L
 They can be combined as register pairs - BC, DE,
and HL - to perform some 16-bit operations
 The programmer can use these registers to store or
copy data into the registers by using data copy
instructions
 The HL register pair is also used to address memory
locations
 In other words, HL register pair plays the role of
memory address register
Accumulator & Pointers
 The accumulator is an 8-bit register that is a
part of arithmetic/logic unit (ALU)
 Program Counter - Deals with sequencing the
execution of instructions. Acts as a memory
pointer
 Stack Pointer – Points to a memory location
in R/W memory, called the stack
Instruction Register/Decoder
 The instruction register and the decoder are
considered as a part of the ALU
 The instruction register is a temporary
storage for the current instruction of a
program
 The decoder decodes the instruction and
establishes the sequence of events to follow
Flags
 The ALU includes five flip-flops, which are set
or reset after an operation according to data
conditions of the result in the accumulator
and other registers
 They are called Zero (Z), Carry (CY), Sign
(S), Parity (P), and Auxiliary Carry (AC) flags
Flags
 If the sum in the accumulator id larger than
eight bits, the flip-flop uses to indicate a carry
-- called the Carry flag (CY) – is set to one
 When an arithmetic operation results in zero,
the flip-flop called the Zero (Z) flag is set to
one
Flags
 These flags have critical importance in the decision-
making process of the microprocessor
 The conditions (set or reset) of the flags are tested
through the software instructions
 The thorough understanding of flag is essential in
writing assembly language programs
 The combination of the flag register and the
accumulator is called Program Status Word (PSW)
and PSW is the 16-bit unit for stack operation
Flags
Pin Diagram
Address & Data Bus
 Address Bus
 The 8085 has eight signal lines, A15-A8,
which are unidirectional and used as the high
order address bus
 Multiplexed Address/Data Bus
 The signal lines AD7-AD0 are bidirectional
 They serve a dual purpose
Address & Data Bus
 They are used as the low-order address bus as well
as the data bus
 In executing an instruction, during the earlier part of
the cycle, these lines are used as the low-order
address bus as well as the data bus
 During the later part of the cycle, these lines are
used as the data bus
 However the low order address bus can be
separated from these signals by using a latch
Control and Status Signals
Machine Cycle IO/M S1 S0 Control signals

Opcode Fetch 0 1 1 RD=0

Memory Read 0 1 0 RD=0

Memory Write 0 0 1 WR=0

I/O Read 1 1 0 RD=0

I/O Write 1 0 1 WR=0

Interrupt Acknowledge 1 1 1 INTA=0

Halt Z 0 0 RD, WR=z and INTA=1

Hold Z X X RD, WR=z and INTA=1

Reset Z X X RD, WR=z and INTA=1

Functional Description
 8085 MPU

Bus Driver
A15
or Buffer High-Order Address Bus
A7 Low-Order Address Bus

A0
Latch to
Demultiplex
AD7 – AD0 Chip Chip Port Port Select
Select Select Select Decoder
Decoder Decoder Decoder

IOW
IOR AND Gate AND Gate

8085
Microprocessor
(MPU) CS CS R/W EN Key EN LED
EPROM Memory Encoder Board Latch Display
RD RD WR
MEMR

MEMR
Bus
Control D7 Data Driver Data Bus
Logic Bus Bidirecti
D0
onal

MEMR

MEMR MEMW

MEMW
IOR
Gates
IOR IOW

IOW

8085 based Microcomputer

 Data Bus

Internal Data Bus

Memory

ALU Instruction B C 2000

Decoder
D E

H L

SP
2004
PC
2005 4F
4F

2005

Control Logic

RD

Data Flow
Timing Diagram
Opcode Fetch

T1 T2 T3 T4

CLX

A15
20H High-Order Memory Address Unspecified
A8
Low-Order

AD7
05H 4FH Opcode
AD0
Memory Address

ALE

IO/M Status IO/M = 0, S0 = 1, S1 = 1 Opcode Fetch

RD
Demultiplexing the bus AD7-AD0
A15 A15
A14
A13
A12
A11
8085
Microprocessor
A10
A9
A8
A8

ALE
A7
Enable
D FF A6
AD7
A5
A4
A3
A2
74LS373 A1
AD0
A0

D7
D6
D5
D4
D3
D2
D1
D0
Schematic to generate Control
Signals
8085

IO/M (M Active
Low
MEMR

RD (Active Low) (Active Low)

WR (Active Low) MEMW

(Active Low)

IOR

(Active Low)

IOW

(Active Low)
Timing for Execution of the
Instruction MVI A,32H
M1 Opcode Fetch M2 Memory Read
T1 T2 T3 T4 T1 T2 T3

CLX

A15
20H High-Order Memory Address Unspecifie 20H High- Order Memory Addresss
A8 d
Low-Order
AD7
00H 3EH Opcode 01H 32H Data
AD0
Memory Address Memory Address

ALE

IO/M
Status IO/M = 0, S0 = 1, S1 = 1 Opcode Fetch IO/M = 0, S1 = 1, S0 = 0 Status
S1, S0

RD
Addressing Modes
 Various ways of specifying the operands or various
formats for specifying the operands is called
addressing mode
 8-bit or 16-bit data may be directly given in the
instruction itself
 The address of the memory location, I/O port or I/O
device, where data resides, may be given in the
instruction itself
 In some instructions only one register is specified.
The content of the specified register is one of the
operands. It is understood that the other operand is
in the accumulator.
Addressing Modes
 Some instructions specify one or two
registers. The contents of the registers are
the required data.
 In some instructions data is implied. The
most instructions of this type operate on the
content of the accumulator.
Addressing Modes
 Implicit addressing
 CMA – Complement the contents of accumulator
 Immediate addressing
 MVI R, 05H
 ADI 06H
 Direct addressing – The address of the
operand in the instruction - STA 2400H, IN
02H
Addressing Modes
 Register addressing
 In register addressing mode the operands are in
the general purpose registers
 MOV A, B
 ADD B
 Register indirect addressing
 Memory location is specified by the contents of
the registers
 LDAX B, STAX D
Data Transfer Instructions
Types Examples
1. Between Registers 1. MOV B,D – Copy the contents of the
register B into Register D
2. Specific data byte to a register or a 2. MVI B,32H – Load register B with the
memory location data byte 32H
3. Between a memory location and a 3. LXI H, 2000H
register MOV B,M
From a memory location 2000H to register
B
4. Between an I/O device and the 4. IN 05H – The contents of the input port
accumulator designated in the operand are read and
loaded into the accumulator
Arithmetic Instructions
 ADD B – [A] <----- [A]+[B]
 ADD M - [A] <----- [A]+[[HL]]
 DAD B – [HL] <----- [HL]+[BC]
 SUB C – [A] <----- [A]+[C]
 SUI 76H – [A] <---- [A]-76H
 SBB M – [A] <----- [A]-[[HL]]-[C]
Logical Instructions
 ANA C – [A] <----- [A] ^ [C]
 ANI 85H – [A] <----- [A] ^ 85H
 ORA M – [A] <----- [A] v [[HL]]
 XRA B – [A] <------ [A] XOR [B]
Rotate Instructions
 RLC
 [An+1] <----- [An]
 [A0] <------ [A7]
 [CS] <----- [A7]
 RAR
 [An] <------ [An+1]
 [CS] <------ [A0]
 [A7] <------ [CS]
Complement Instructions
 CMP R
 CPI data
 CMA – [A] <---- [A]’
 CMC – [CS] <----- [CS]’
Transfer Instructions
 JMP 2050H – [PC] <----- 2050H
 JZ 3100H – [PC] <----- 3100H if Z=1,
otherwise [PC] <----- [PC]+1
 JNC 4250H – [PC] <----- 4250H if C=0,
otherwise [PC] <----- [PC]+1
CALL & RET
 CALL Addr
 [[SP]-1] <------- [PCH]
 [[SP]-1] <------- [PCL]
 [SP] <----- [SP]-2
 [PC] <----- Addr
 RET
 [PCL] <------ [[SP]]
 [PCH] <------ [[SP]+1]
 [SP] <------ [SP]+2
One Byte Instructions
Two Byte Instructions
Writing Assembly Language
Program
 Define the problem clearly and make the problem
statement.
 Analyze the problem thoroughly. In this step we
divide the problem into smaller steps to examine
the process of writing programs.
 Draw the flow chart. The steps listed in the
problem analysis and the sequences are
represented in a block diagram.
 Translate the blocks shown in the flowchart into
8085 operations and then subsequently into
mnemonics.
Conversion and Execution
 Convert the mnemonics into Hex code; we
need to look up the code in 8085 instruction
set.
 Store the program in Read/Write memory of a
single-board microcomputer. This may
require the knowledge about memory
addresses and the output port addresses.
 Finally execute the program.
Tri-State Buffers
 An important circuit element that is used
extensively in memory.
 This buffer is a logic circuit that has three
states:
 Logic 0, logic1, and high impedance.
 When this circuit is in high impedance mode it
looks as if it is disconnected from the output
completely.
The Tri-State Buffer
 This circuit has two inputs and one output.
 The first input behaves like the normal input for
the circuit.
 The second input is an “enable”.
 If it is set high, the output follows the proper circuit
behavior.
 If it is set low, the output looks like a wire
connected to nothing.

Input Output OR Input Output

Enable Enable
Interfacing Techniques
 Memory Interfacing
 8085 uses 16-bit memory addressing system allowing
a maximum of 64 KB size of memory
 The logical memory address range is 0000h-FFFFh
 These 64k addresses can be allotted separately to
RAMs & ROMs
 Some interfacing circuit examples can be found in the
following link
  I/O Interfacing
 To interface Input Devices Octal buffers
are used. These octal buffers are called as
input ports
 Octal buffers contain a set of eight buffers
for an 8-bit system data bus
 A buffer is basically a current amplifier
which amplifies the smaller magnitude
currents of input devices before being
supplied to the CPU
 The tri-state logic also provides the
addressing and control logic for the CPU
 To interface output devices Octal Latches
are used.
 A latch is basically a D Flip-Flop
 Latches are used to hold the output data
because information on system data bus is
available for a very small duration of time.
 There are three major types of data transfer
between the microcomputer and art I/O device.
They are-
 Programmed I/O : In programmed I/O the data
transfer is accomplished through an I/O port and
controlled by software.
 Interrupt driven I/O : In interrupt driven I/O, the I/O
device will interrupt the processor, and initiate data
transfer.
 Direct memory access (DMA) : In DMA, the data
transfer between memory and I/O can be performed
by bypassing the microprocessor.
 Some special purpose programmable
devices used with 8085 are listed in the table
of next slide.
 These devices are used in the system
according to the requirement.
Chip Select
 Usually, each memory chip has a CS (Chip Select) input.
The chip will only work if an active signal is applied on
that input.
 To allow the use of multiple chips in the make up of
memory, we need to use a number of the address lines
for the purpose of “chip selection”.
 These address lines are decoded to generate the 2n
necessary CS inputs for the memory chips to be used.
Chip Selection Example
 Assume that we need to build a memory system
made up of 4 of the 4 X 4 memory chips we
designed earlier.

 We will need to use 2 inputs and a decoder to

identify which chip will be used at what time.

 The resulting design would now look like the one

on the following slide.
DMA
 Device wishing to perform DMA asserts the
processors bus request signal.
 Processor completes the current bus cycle and
then asserts the bus grant signal to the device.
 The device then asserts the bus grant ack signal.
 The processor senses in the change in the state of
bus grant ack signal and starts listening to the
data and address bus for DMA activity.
DMA
 The DMA device performs the transfer from the
source to destination address.
 During these transfers, the processor monitors the
addresses on the bus and checks if any location
modified during DMA operations is cached in the
processor. If the processor detects a cached
address on the bus, it can take one of the two
actions:
 Processor invalidates the internal cache entry for the
address involved in DMA write operation
 Processor updates the internal cache when a DMA write is
detected
DMA
 Once the DMA operations have been
completed, the device releases the bus by
asserting the bus release signal.
 Processor acknowledges the bus release and
resumes its bus cycles from the point it left
off.