ATPG(Automatic Test Pattern Genrator)

| Pranav Dass |15102186 |

Name of Supervisor: Mr.Atul Kumar Srivastava

DEPARTMENT OF ECE
JAYPEE INSTITUTE OF INFORMATION TECHNOLOGY,
NOIDA
 TABLE OF CONTENTS

S.NO TOPIC PAGE NO.

1 Certificate 2
2 Acknowledgement 3
3 Introduction 4
4 Design testing in a VLSI desgin Flow 5
5 ATPG 5
6 D-Algorithm 6
7 PODEM 7
8 FAN 8
9 Pseudo Random Test 9
10 Reference 10
 CERTIFICATE
This is to certify that the work entitled “Automatic test pattern genrator(ATPG)”
has been completed and submitted by “Pranav Dass” in partial fulfillment
for the award of degree of B.Tech in ECE from JAYPEE INSTITUTE OF
INFORMATION TECHNOLOGY, NOIDA has been carried out under my
supervision. This work has not been submitted partially or completely to
any other University or Institute for the award of this or for any other degree or diploma.
 ACKNOWLEDGEMENT

Firstly, I would like to express my sincere gratitude towards my mentor Mr.

Atul Kumar Srivastava who has been my constant support during the entire span of
my term-paper and I sincerely thank for his guidance and encouragement which
helped me in carrying out this project so efficiently. Without him, finalization of
this project wouldn’t be possible.
I would also like to show my gratitude towards my college JAYPEE INSTITUTE
OF INFORMATION TECHNOLOGY for providing me such a large platform on
which I can examine myself and can showcase my knowledge to everyone.
 INTRODUCTION
Ever-growing scale, ever-increasing complexity, and ever-shrinking process feature
sizes make the design of VLSI circuits highly prone to design errors and their
fabrication to manufacturing defects. Therefore, VLSI design verification is needed
on the design side to determine whether a design is error-free, while VLSI testing is
needed on the manufacturing side to determine whether a fabricated VLSI circuit is
defect-free . VLSI testing is necessary because numerous causes in a manufacturing
process may potentially introduce such physical defects as shorts and opens into a
circuit fabricated from an error-free design. VLSI testing is conducted by applying
test stimuli to the circuit-under-test, measuring actual circuit responses, and
comparing them with expected circuit responses. The CUT is declared defective if
measured and expected circuit responses do not match with each other. When yield
improvement or reliability enhancement is required, detailed failure analysis needs
to be conducted to identify the location and the root-cause of the defects. Test
quality is mainly determined by the ratio of undertest and the ratio of over-test.
Under-test is mostly caused by inadequate contents of test stimuli, also referred to
as test patterns. Over-test is conventionally blamed on the circuit model difference
between test mode and functional mode, which causes some functionally-benign
defects to fail a circuit only during testing.
 Digital Testing in a VLSI Design Flow

Digital testing starts with the development of the specifications for the system from
the set of requirements, which includes functional characteristics, operating
characteristics,physical and environmental and other constraints like area, pin count,
etc. This is followed by an architectural design to produce a system level structure
of realizable blocks for the functional specifications. These blocks are then
implemented at resister transfer level (RTL) using some hardware definition
language like Verilog or VHDL.Depending on the type of circuit and the nature of
testing required, some additional circuitry, pin out, etc. need to be added with the
original circuit so that hardware testing becomes efficient in terms of fault coverage,
test time, etc. this is called design for testability (DFT).After logic synthesis, test
patterns are generated that need to be applied to the circuit after it gets manufactured.
Test patters are generally applied and analyzed using automatic test equipment
(ATE). Figure shows the picture of an ATE from Teradyne.

ATPG(Automatic Test Pattern Genrator)

Automatic Test Pattern Generation,or ATPG, is a process used in semiconductor electrical
testing wherein the vectors or input patterns required to check a device for faults are
automatically generated by a program. The vectors are sequentially applied to the device
under test and the device's response to each set of inputs is compared with the expected
response from a good circuit. An 'error' in the response of the device means that it is
faulty. The effectiveness of the ATPG is measured primarily by the fault coverage achieved
and the cost of performing the tet

A cycle of ATPG can generally be divided into two distinct phases:

1) creation of the test
2) application of the test.
During the creation of the test, appropriate models for the device circuit are developed at
gate or transistor level in such a way that the output responses of a faulty device for a
given set of inputs will differ from those of a good device. This generation of test is
basically a mathematical process that can be done in three ways:
1) by manual methods
2) by algorithmic methods
3) by pseudo-random methods
When creating a test, the goal should be to make it as efficient in memory space and time
requirements as much as possible.As such, the ATPG process must generate the minimum or
near minimum set of vectors needed to detect all the important faults of a device.The main
considerations for test creation are:
1) the time needed to construct the minimal test set
2) the size of the pattern generator, or hardware/software system needed to properly stimulate
the devices under test
3) the size of the testing process itself
4) the time needed to load the test patterns
5) the external equipment required

ATPG algorithmic methods that are in wide use today include

1) D-Algorithm
2) PODEM
3) FAN

Algorithmic pattern generation basically consists of the following steps:

1) fault selection, or choosing a fault that needs to be detected
2) initial assignment, or finding an input pattern that sets up a D or D' at the output of the
faulty gate
3) forward drive, or propagating a D or D' to an observable output using the shortest path
possible
4) justification, or assigning of values to other unassigned inputs in order to justify the
assignments made during the forward drive.

If an inconsistency arises during justification,backtracking or back propagation is performed,

i.e., forward drive is done again using an alternate path. This recursive cycle is performed
until the right set of input patterns needed to 'sensitize' a path and propagate the fault to an
observable output is determined.

D-Algorithm:
The D algorithm was the first true algorithm for ATPG. We can use it to generate
tests by combining what we know about the primitive elements of the circuit with
what we know about their interconnection network. The method that Roth proposed
is based on the intersection of dcubes, a notation for the difference calculus. Breuer
and Friedman’ give a good background treatment of the testing aspects of the D
algorithm in their text, while Roth offers a complete mathematical analysis in his
original paper. For our discussion, we examine Roths algorithm as a search of a
state space. We begin with the binary values 0 and 1 and add three new values. The
first added value is X, which denotes an unassigned node value. To describe the
difference between the good and faulty circuits,D and are introduced, denoting a
difference and a difference bar, respectively.
Path Sensitization Methods:
Path sensitization at the logic gate level of representation is currently the preferred
ATPG method. The approach consists of three steps:
1. Fault sensitization, in which a stuck-at fault is activated by forcing the signal
driving it to an opposite value from the fault value. This is necessary to ensure a
behavioral difference between the good circuit and the faulty circuit. Fault
sensitization is also known as fault activation or fault excitation.
2. Fault propagation, in which the fault effect is propagated through one or more
paths to a PO of the circuit. For some faults, it is necessary to simultaneously
propagate the fault effect over multiple paths to test it. In general, the number of
paths may rise exponentially in the number of logic gates in the circuit. Fault
propagation is also known as path sensitization.
3. Line justification, in which the internal signal assignments previously made to
sensitize a fault or propagate its effect are justified by setting PIs of the circuit.
PODEM:
In 1981, Goel proposed another way of looking at the search problem in ATPG. He
called the algorithm Podem, short for path-oriented decision making.3 Goel noticed
that the search graph used by the D algorithm includes every node in the circuit. For
combinational circuits, however, we really need to consider only nodes that are
primary inputs. All other nodes are a function of some set of the primary input nodes.
Thus, when we choose inputs as nodes in the search space, we will have no hidden
conflicts and each node can be assigned independently. Further, suppose that we
already have a set of primary input assignments and another primary input has been
assigned a value that causes a conflict. We would have to try only one other value
at that input (the complement of the current value) to determine if the current
assignment will ever be compatible with the goal. If the complementary value also
conflicts, then the goal cannot be achieved with the existing input assignments, and
we will need to backtrack further. Since we do not have to try any assignments
below this point, we can prune a large portion of the search graph and never search
it when such conflicts arise. The savings in computer time is enhanced because the
total search space is smaller than that of the D algorithm.
FAN:
The Fan-out Oriented (FAN) algorithm is a further improvement to PODEM with some
additional features. For instance, it utilizes circuit topology information to increase search
efficiency. FAN differs from PODEM in several ways, including the following: it stops
backtracking at certain internal lines; it performs multiple back-tracing; it allows both
backward and forward implications; and it immediately assigns uniquely-determined signals.
The test pattern generation algorithmic methods discussed in previous paragraphs are all
computation-intensive and can be quite expensive, not to mention the numerous difficulties
that may be encountered in complex cases.In fact, in some complex circuits, the use of such
algorithms is no longer feasible or practical.

Pseudo-random test:
Pseudo-random test pattern generation coupled with fault simulation is a simpler alternative to
algorithmic methods. This involves the generation of input vectors using a relatively
inexpensive pseudo random number generator and the performance of fault simulations to
determine if these vectors will lead to the detection of the target fault. The characteristics of
the target fault has a great influence on how well pseudo-random test generation will work.
It is typically used in the beginning of the test generation process to cover easy-to-detect
faults from the list of faults to be covered.Faults that were not covered by the pseudo-
random test generation may be covered by algorithmic methods.
 Refrences

1. Tom Kirkland, M. Ray Mercer, “Algorithms for Automatic Test Pattern

Generation”, IEEE Design & Test of Computers ,vol-5, issue-3, pp. 43-55, June
1988.
2. Sami A. AI-Arian, Martin Nordenso, “FUNTEST: A Functional Automatic Test
Pattern Generator for Combinational Circuits”, Proceedings. 'Meeting the Tests of
Time'., International Test Conference, PP(945-946), Aug. 1989.
3. Manoj Sachdev, “Multi Giga Hertz Digital Test Challenges and Techniques”,
Proceedings. International Test Conference, pp. 1231, Oct. 2002
4. P. Goel, “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic
Circuits,” IEEE Trans. on Computers, vol. C-30, no. 3, pp. 215–222, Mar. 198 1.