LG 50pa4500-Sf - Ch. Pb21a PDF

Internal Use Only
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PLASMA TV
SERVICE MANUAL
CHASSIS : PB21A
MODEL : 50PA4500 50PA4500-SF

CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL67341904 (1201-REV00) Printed in Korea

CONTENTS
CONTENTS . ............................................................................................. 2
SAFETY PRECAUTIONS ......................................................................... 3
SPECIFICATION........................................................................................ 4
ADJUSTMENT INSTRUCTION................................................................. 5
BLOCK DIAGRAM................................................................................... 12
EXPLODED VIEW .................................................................................. 13
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
AC Volt-meter
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
such as WATER PIPE,
shock. CONDUIT etc.
To Instrument's 0.15u
exposed
Leakage Current Cold Check(Antenna Cold Check) METALLIC PARTS
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC 1.5 Kohm/10W
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
This spec sheet is applied all of the PDP TV with PB21A chassis.
2. Requirement for Test

Each part is tested as below without special appointment.
(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
(5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test method
(1) Performance: LGE TV test method followed
(2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC
4. Model General Specification

No Item Specification Remark
1 Receiving System 1) SBTVD / NTSC / PAL-M / PAL-N 50A6500-SA
50A4900-SA
2) DVB-T 42/50PA4500-DF
2 Available Channel 1) VHF : 02~13 50A6500-SA
2) UHF : 14~69 50A4900-SA
3) DTV : 07-69 (VHF high/UHF)
4) CATV : 02~135
1) VHF : 02~13 42/50PA4500-DF
2) UHF : 14~69
3) DTV : 14~69 (UHF)
4) CATV : 02~135
3 Input Voltage 1) AC 100 ~ 240V 50/60Hz
4 Market Brazil / chile / Peru / Venezuela / Costarica / Uruguay
5 Screen Size 42 inch Wide(1024 × 768) 42PA all model
50 inch Wide(1024 × 768) 50PA4 all model
6 Aspect Ratio 16:9
7 Tuning System FS
8 Module PDP42T4#### (1024 × 768) 42PA all model
PDP50T4#### (1024 × 768) 50PA4 all model
PDP50R4#### (1920 × 1080) 50PA6 all model
PDP60R4#### (1920 × 1080) 60PA6 all model
9 Operating Environ- 1) Temp : 0 ~ 40 deg
ment 2) Humidity : ~ 80 %
10 Storage Environ- 1) Temp : -20 ~ 60 deg
ment 2) Humidity : ~ 85 %
ADJUSTMENT INSTRUCTION
1. Application Range 4. PCB Assembly Adjustment
This spec. sheet applies to PB21A chassis applied PDP TV all 4.1. Using RS-232C
models manufactured in TV factory. - A
djust 3 items at 3.1. PCB assembly adjustments
" 4.1. ■ Adjustment sequence" one after the order.
2. Specification ■ Adjustment sequence

(1) Because this is not a hot chassis, it is not necessary to Order command Set response
use an isolation transformer. However, the use of isolation
transformer will help protect test instrument. 1. Inter the aa 00 00 a 00 OK00x
Adjustment
(2) Adjustment must be done in the correct order. But it is mode
flexible when its factory local problem occurs.
2. C
hange the XB 00 40 b 00 OK40x (Adjust 480i Comp1 )
(3) The adjustment must be performed in the circumstance of Source XB 00 60 (Adjust 1080p Comp1)
25 °C ± 5 °C of temperature and 65 % ± 10 % of relative b 00 OK60x (Adjust 1080p RGB)
humidity if there is no specific designation.
3. Start ad 00 10
(4) The input voltage of the receiver must keep AC 100-240 Adjustment
V~, 50/60 Hz.
4. Return the OKx ( Success condition )
(5) Before adjustment, execute Heat-Run for 5 minutes.
Response NGx ( Failed condition )
■ A fter Receive 100% Full white pattern (06CH) then 5. R

ead ( main ) (main : component1 480i, RGB 1080p)
Adjustment ad 00 20 000000000000000000000000007c007b006dx
process Heat-run data ( main ) (main : component1 1080p)
(or “8. Test pattern” condition of Ez-Adjust status) ad 00 30 000000070000000000000000007c00830077x
6. Confirm ad 00 99 NG 03 00x (Failed condition)
■ How to make set white pattern Adjustment NG 03 01x (Failed condition)
1) Press Power ON button of Service Remocon NG 03 02x (Failed condition)
2) Press ADJ button of Service remocon. Select “10. Test OK 03 03x (Success condition)
pattern” and, after select “White” using navigation 7. End of ad 00 90 d 00 OK90x
button, and then you can see 100% Full White pattern. Adjustment
< See ADC Adjustment RS232C Protocol_Ver1.0 >

* In this status you can maintain Heat-Run useless any
pattern generator
* Notice: if you maintain one picture over 20 minutes
(Especially sharp distinction black with white ■ Necessary items before Adjustment items
pattern – 13Ch, or Cross hatch pattern – 09Ch) ● Pattern Generator : (MSPG-925FA)
then it can appear image stick near black level. ● Adjust 480i comp1
(MSPG-925FA:model :209, pattern :65) - comp1 Mode
● Adjust 1080p comp1
(MSPG-925FA:model :225 , pattern :65) - comp1 Mode
3. Adjustment items ● Addjust RGB (MSPG-925FA:model :225 , pattern :65)
3.1. PCB Assembly adjustment - RGB-Pc Mode
■ Adjust 480i Comp1
■ Adjust 1080p Comp1/RGB * If you want more information then see the below Adjustment
● If it is necessary, it can adjustment at Manufacture Line method (Factory Adjustment)
● You can see set adjustment status at “9. ADJUST
CHECK” of the “In-start menu” ■ Adjustment sequence
● aa 00 00: Enter the ADc Adjustment mode.
● xb 00 40: change the mode to component1 (No actions)
3.2. Set Assembly Adjustment ● ad 00 10: Adjust 480i comp
■ EDID (The Extended Display Identification Data ) ● ad 00 10: Adjust 1080p comp
■ Color Temperature (White Balance) Adjustment ● xb 00 60: change to RGB-Pc mode(No action)
■ Make sure RS-232C control ● ad 00 10: Adjust 1080p RGB
■ Selection Factory output option ● xb 00 90: Endo of Adjustmennt
5. Factory Adjustment
-> PU21A/PB21A : USE INTERNAL ADC(LM1) : using internal
pattern.
5.1. Auto Adjust Component 480i/1080p RGB

1080p
■ Summary : A djustment component 480i/1080i and RGB
1080p is Gain and Black level setting at Analog
to Digital converter, and compensate the RGB
deviation
■ Using instrument
● A djustment remocon, 801GF(802B, 802F, 802R) or
MSPG925FA pattern generator
(I t can output 480i/1080i horizontal 100% color bar
pattern signal, and its output level must setting
0.7V±0.1V p-p correctly)
* caution : Set Volume 0 after adjustment
5.2. Use Internal ADC(S7R)

- A DJ(EZ ADJUST) -> 6.ADC Calibration -> ADC
< Adjustment pattern : 480i / 1080p 60Hz Pattern > Calibration(START)
* E DID (The Extended Display Identification Data)/DDC

● You must make it sure its resolution and pattern cause (Display Data Channel) Download.
every instrument can have different setting ■ Summary
● Adjustment method 480i Comp1, Adjust 1080p Comp1/ ● It is established in VESA, for communication between
RGB (Factory adjustment) PC and Monitor without order from user for building
● ADC 480i Component1 adjustment user condition. It helps to make easily use realize
- Check connection of Component1 “Plug and Play” function.
- MSPG-925FA -> Model: 209, Pattern 65 ● For EDID data write, we use DDC2B protocol.
● Set Component 480i mode and 100% Horizontal Color
Bar Pattern(HozTV31Bar), then set TV set to - Auto Download
Component1 mode and its screen to “NORMAL” ■ After enter Service Mode by pushing “ADJ” key,
● ADC 1080p Component1 / RGB adjustment ■ Enter EDID D/L mode.
- Check connection both of Component1 and RGB ■ Enter “START” by pushing “OK” key.
- MSPG-925FA -> Model: 225, Pattern 65
● Set Component 1080p mode and 100% Horizontal Color * Caution:
Bar Pattern(HozTV31Bar), then set TV set to - N ever connect HDMI & D-sub Cable when the user
Component1 mode and its screen to “NORMAL” downloading .
● After get each the signal, wait more a second and enter - Use the proper cables below for EDID Writing
the “IN-START” with press IN-START key of Service
remocon. After then select “7. External ADC” with
navigator button and press “Enter”.
● After Then Press key of Service remocon “Right Arrow
(VOL+)”
● You can see “ADC Component1 Success”
● Component1 1080p, RGB 1080p Adjust is same method.
● C omponent 1080p Adjustment in Component1 input
mode
● RGB 1080p adjustment in RGB input mode
● If you success RGB 1080p Adjust. You can see “ADC
RGB-DTV Success”
■ It only needs to PCM EDID D/L for North America Product. ■ EDID data (Model name = LG TV)
(PU21A)
- RGB HD
00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
01 16 01 03 68 A0 5A 78 0A EE 91 A3 54 4C 99 26
0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01
01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88
36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20
28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A
3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 00 58
- South Centural America _2D_HD HDMI

00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
* Edid data and Model option download(RS232) 0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01
NO Enter EDID data Model 01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88
download MODE option download
36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20
Item download ‘Mode In’ download
28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A
CMD 1 A A
3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
CMD 2 A E
00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 3F
Data 0 0 00
0 10
02 03 27 F1 4F 10 1F 84 13 05 14 03 02 12 20 22
When transfer the Automatically download
‘Mode In’, (The use of a internal 15 11 16 01 26 15 07 50 09 57 07 67 03 0C 00 10
Carry the command. pattern) 00 B8 2D E3 05 03 01 01 1D 00 72 51 D0 1E 20 6E
28 55 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D
- Manual Download
40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71
■ Write HDMI EDID data
● Using instruments 1C 16 20 58 2C 25 00 40 84 63 00 00 9E 00 00 00
- Jig. (PC Serial to D-Sub connection) for PC, DDC 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
adjustment.
- S/W for DDC recording (EDID data write and read) 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D1
- D-sub jack
- Additional HDMI cable connection Jig.
● Preparing and setting.
- Set instruments and Jig. Like pic.5), then turn on PC
and Jig.
- Operate DDC write S/W (EDID write & read)
- It will operate in the DOS mode.
< For write EDID data, setting Jig and another instruments >
- South Centural America _2D_HD HDMI 2 - Adjustment Color Temperature(White balance)
■ Using Instruments
00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
● Color Analyzer: CA-210 (CH 10)
01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26 - Using LCD color temperature, Color Analyzer (CA-
0F 50 54 A1 08 00 31 40 45 40 61 40 01 01 01 01 210) must use CH 10, which Matrix compensated
(White, Red, Green, Blue compensation) with CS-
01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88 2100. See the Coordination bellowed one.
36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20 ● Auto-adjustment Equipment (It needs when Auto-adjust-
ment – It is availed communicate with RS-232C : Baud
28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A
rate: 115200)
3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC ●V ideo Signal Generator MSPG-925F 720p, 216Gray
00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 3F (Model: 217, Pattern 78)
■ Connection Diagram (Auto Adjustment)

02 03 27 F1 4F 10 1F 84 13 05 14 03 02 12 20 22 ● Using Inner Pattern
15 11 16 01 26 15 07 50 09 57 07 67 03 0C 00 20
00 B8 2D E3 05 03 01 01 1D 00 72 51 D0 1E 20 6E
28 55 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D
40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71
1C 16 20 58 2C 25 00 40 84 63 00 00 9E 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C1
● Using HDMI input

- South Centural America _2D_HD HDMI 3
00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
01 16 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
01 01 01 01 01 01 64 19 00 40 41 00 26 30 18 88
36 00 B0 84 43 00 00 18 A0 0F 20 00 31 58 1C 20
28 80 14 00 B0 84 43 00 00 1E 00 00 00 FD 00 3A
3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 3F < connection Diagram for Adjustment White balance >
■ White Balance Adjustment

02 03 27 F1 4F 10 1F 84 13 05 14 03 02 12 20 22 If you can’t adjust with inner pattern, then you can adjust
15 11 16 01 26 15 07 50 09 57 07 67 03 0C 00 30 it using HDMI pattern. You can select option at “Ez-Adjust
Menu – 7. White Balance” there items “NONE, INNER,
00 B8 2D E3 05 03 01 01 1D 00 72 51 D0 1E 20 6E
HDMI”. It is normally setting at inner basically. If you can’t
28 55 00 40 84 63 00 00 1E 02 3A 80 18 71 38 2D adjust using inner pattern you can select HDMI item, and
40 58 2C 45 00 40 84 63 00 00 1E 01 1D 80 18 71 you can adjust.
1C 16 20 58 2C 25 00 40 84 63 00 00 9E 00 00 00 In manual Adjust case, if you press ADJ button of service
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 remocon, and enter “Ez-Adjust Menu – 7. White Balance”,
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B1 then automatically inner pattern operates. (In case of
“Inner” originally “Test-Pattern. On” will be selected in The
“Test-Pattern. On/Off”.
- See Working Guide if you want more information about EDID
communication. ● Connect all cables and equipments like Pic.5)
●S et Baud Rate of RS-232C to 115200. It may set 115200
orignally.
● Connect RS-232C cable to set
● Connect HDMI cable to set
● When Color temperature (White balance) Adjustment
(Automatically)
- Press “Power only key” of service remocon and operate
automatically adjustment.
- Set BaudRate to 115200.
● You must start “wb 00 00” and finish it “wb 00 ff”.
● If it needs, then adjustment “Offset”.
■ White Balance Adjustment (Manual adjustment)

● Test Equipment: CA-210
- Using PDP color temperature, Color Analyzer (CA-210)
must use CH 10, which Matrix compensated (White, Red,
Green, Blue compensation) with CS-2100. See the
Coordination bellowed one.
● Manual adjustment sequence is like bellowed one.
- Turn to “Ez-Adjust” mode with press ADJ button of service
remocon.
- Select “10.Test Pattern” with CH+/- button and press
enter. Then set will go on Heat-run mode. Over 30
■ RS-232C Command (Commonly apply) minutes set let on Heat-run mode.
- Let CA-210 to zero calibration and must has gap more
RS-232C COMMAND Meaning 10cm from center of PDP module when adjustment.
[CMD ID DATA] - Press “ADJ” button of service remocon and select
wb 00 00 White Balance adjustment start. “7.White-Balance” in “Ez-Adjust” then press “►” button of
navigation key. (When press “►” button then set will go to
wb 00 10 Start of adjust gain
full white mode)
(Inner white pattern) - Adjust at three mode (Cool, Medium, Warm)
wb 00 1f End of gain adjust - If “cool” mode
Let B-Gain to 192 and R, G, B-Cut to 64 and then control
wb 00 20 Start of offset adjust R, G gain adjustment High Light adjustment.
(Inner white pattern) - If “Medium” and “Warm” mode Let R-Gain to 192 and R,
wb 00 2f End of offset adjust G, B-Cut to 64 and then control G, B gain adjustment
High Light adjustment.
wb 00 ff End of White Balance adjust - All of the three mode
(Inner pattern disappeared) Let R-Gain to 192 and R, G, B-Cut to 64 and then control
G, B gain adjustment High Light adjustment.
● “wb 00 00”: Start Auto-adjustment of white balance. - With volume button (+/-) you can adjust.
● “wb 00 10”: Start Gain Adjustment (Inner pattern) - After all adjustment finished, with Enter (■ key) turn to
● “jb 00 c0” : Ez-Adjust mode. Then with ADJ button, exit from
●… adjustment mode
● “wb 00 1f”: End of Adjustment
* If it needs, offset adjustment (wb 00 20-start, wb 00 2f- * Attachment: W
hite Balance adjustment coordination and
end) color temperature.
● “wb 00 ff”: End of white balance adjustment (inner pattern
disappear) ● Using CS-1000 Equipment.
- COOL : T=11000K, ∆uv=0.000, x=0.276 y=0.283
■ Adjustment Mapping information - MEDIUM : T=9300K, ∆uv=0.000, x=0.285 y=0.293
- WARM : T=6500K, ∆uv=0.000, x=0.313 y=0.329
RS-232C M CENTER M
COMMAND I (DEFAULT) A
[CMD ID DATA] N X
Cool Mid Warm Cool Mid Warm
R Gain jg Ja jd 00 184 192 192 192
G Gain jh Jb je 00 187 183 159 192
B Gain ji Jc jf 00 192 161 95 192
R Cut 64 64 64 127
G Cut 64 64 64 127
B Cut 64 64 64 127
6. GND and ESD Testing
● When tester will measure on Cool condition, adjust W30 on 6.1. Prepare GND and ESD Testing.
TV display menu. ■ Check the connection between set and power cord
6.2. Operate GND and ESD auto-test.

■ Fully connected (Between set and power cord) set enter the
● When tester will measure on medium condition, adjust 0 on Auto-test sequence.
TV display menu. ■ Connect D-Jack AV jack test equipment.
■ Turn on Auto-controller(GWS103-4)
■ Start Auto GND test.
■ If its result is NG, then notice with buzzer.
● When tester will measure on warm condition, adjust W30 on ■ If its result is OK, then automatically it turns to ESD Test.
TV display menu. ■ Operate ESD test
■ If its result is NG, then notice with buzzer.
■ If its result is OK, then process next steps. Notice it with
● Using CA-210 Equipment. (10 CH) Good lamp and STOPER Down.
- Contrast value: 216 Gray
Color Test Color Coordination 6.3. Check Items.

temperature Equipment ■ Test Voltage
x y
● GND: 1.5KV/min at 100mA
COOL CA-210 0.276 ± 0.002 0.283 ± 0.002 ● Signal: 3KV/min at 100mA
MEDIUM CA-210 0.285 ± 0.002 0.293 ± 0.002 ■ Test time: just 1 second.
■ Test point
WARM CA-210 0.313 ± 0.002 0.329 ± 0.002 ● GND test: Test between Power cord GND and Signal
cable metal GND.
- Brightness spec.
● ESD test: Test between Power cord GND and Live and
Item White average Brightness uniformity neutral.
brightness ■ Leakage current: Set to 0.5mA(rms)
Min 49 -20
Typ 60 6.4. POWER PCB Ass’y Voltage adjustment
(Va, Vs voltage adjustment)
Max +20
6.4.1. Test equipment : D.M.M 1EA
Unit cd/m² % 6.4.2. Connection Diagram for Measuring
Remark - 100% Window White - 85IRE(216Gray) 100% : refer to fig.1
Pattern Window White Pattern <XPOWER4 50R4/T4 PSU>
- 100IRE(255Gray) - Picture: Vivid(Medium)
- Picture: Vivid(Medium)
5.3. Test of RS-232C control.

- Press In-Start button of Service Remocon then set the
“4.Baud Rate” to 115200. Then check RS-232C control and
5.4. Selection of Country option.

- Selection of country option is allowed only North American
model (Not allowed Korean model). It is selection of Country (fig.1) PCB Assy Voltage adjustment
about Rating and Time Zone.
■ Models: All models which PU11A Chassis (See the first 6.4.3. Adjustment method
page.) 6.4.3.1. Vs adjustment (refer fig.1)
■ Press “In-Start” button of Service Remocon, then enter the (1) Connect + terminal of D.M.M. to Vs pin of P811, connect
“Option” Menu with “PIP CH-“ Button -terminal to GND pin of P811
■ Select one of these three (USA, CANADA, MEXICO) de- (2) After turning VR901, voltage of D.M.M adjustment as same
pends on its market using “Vol. +/-“button. as Vs voltage which on label of panel left/top ( deviation ;
±0.5V)
* Caution : Don’t push The INSTOP KEY after completing the 6.4.3.2. Va adjustment (refer fig.1)
function inspection. (1) After receiving 100% Full White Pattern, HEAT RUN.
(2) Connect + terminal of D.M.M. to Va pin of P811, connect
* Caution : Inspection only PAL M / NTSC -terminal to GND pin of P811
(3) After turning VR502,voltage of D.M.M adjustment as same
as Va voltage which on label of panel left/top (deviation;
±0.5V)
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
7. Default Service option. ■ Select download file (epk file)
7.1. ADC-Set.
■ R-Gain adjustment Value (default 128)
■ G-Gain adjustment Value (default 128)
■ B-Gain adjustment Value (default 128)
■ R-Offset adjustment Value (default 128)
■ G-Offset adjustment Value (default 128)
■ B-Offset adjustment Value (default 128)
7.2. White balance. Value.

Center(Default)
COOL Mid Warm
R Gain 192 192 192
G Gain 192 192 192
B Gain 192 192 192
R Cut 64 64 64
G Cut 64 64 64
B Cut 64 64 64
7.3. Temperature Threshold

■ Threshold Down Low 20
■ Threshold Up Low 23
■ Threshold Down High 70
■ Threshold Up High 75
8. USB DOWNLOAD(*.epk file download)

■ Put the USB Stick to the USB socket
■ Press Menu key, and move OPTION
■ After download is finished, remove the USB stick.

■ Press “IN-START” key of ADJ remote control, check the
S/W version.
9. Tool option
■ Press “FAV” Press 7 times 50PA4500-SF
Tool option 1 36864
Tool option 2 22794
Tool option 3 3697
Tool option 4 51270
Tool option 5 10
Country code 03
Country Group BR
Country BR
BLOCK DIAGRAM
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
310
300
540
303
304
601
209
305
208
520
A12
206
301
580
201
A9
205
302
200
204
A10
501
207
203
202
LV1
590
240
120
A2
900
400
910
+5V
Full SCART
EU
+3.3V
MMBT3906(NXP)
Q103-*1
MULTI
E
C
B
L103
120-ohm
EU
PDP GP4 LM1
EAX64280503
R104
10K
JK100 EU
C117
PSC008-02 R144
AV/SC1_DET 470 0.1uF
E 16V
R105 EU
1K R129 READY
SHIELD EU 0
EU B
R146
SC1_SOG_IN C 18K
23 C Q103
B ISA1530AC1 EU
AV/SC1_CVBS_IN EU
AV_DET C
22 R117 C109 C111 R136
Q100 330
COM_GND 75 27pF 220pF E EU
B
EU MMBT3904(NXP)
21 50V 50V
SYNC_IN EU EU EU DTV/MNT_VOUT
C116
20 E Q104 10uF
SYNC_OUT
SC1_VOUT MMBT3904(NXP) R147 16V
EU 10K EU
19 R141 EU
R113 5% C110 R135
1/16W
SYNC_GND2 R118 C106 R134 220 R143
75 1000pF 0 180
18 EU 470K 100uF 100 EU EU
50V EU
SYNC_GND1 EU 16V 1/4W
EU READY EU
17 R142
RGB_IO 390
SC1_FB READY EU
16
R_OUT R123 E 1K
R119 33 EU EU
SC1_R+/COMP1_Pr+ 75 R158
15 EU KDS184 MMBT3904(NXP)
RGB_GND EU Q106 SC_RE1
R106 D112 B EU
14 A2 E
75 1K
R_GND
SC1_ID REC_8 C EU C EU R157
13 R114 12K MMBT3904(NXP) B SC_RE2
R120 A1 E
D2B_OUT 10K 2.7K R160 Q105
12 EU EU EU
C
G_OUT MULTI MMBT3904(NXP) EU
SC1_G+/COMP1_Y+ Q107 B
11 D112-*1 EU 7.5K
D2B_IN R108 AV/SC1_L_IN MMBD6100 C 12K R156
10 75 A2 R159
R115 C102 R121 R126
G_GND 1000pF 10K C
470K 12K
9 50V EU
EU EU A1 EU
ID READY R155
8 3K
B_OUT
SC1_B+/COMP1_Pb+ AV/SC1_R_IN
7
AUDIO_L_IN R107 R116 C103 R124 P_17V
6 75 470K 1000pF 10K R127 IC101
50V EU 12K
B_GND EU AZ4580MTR-E1
READY EU P_17V
5
AUDIO_GND
4
AUDIO_L_OUT OUT1 1 8 VCC
3 R122 C107 R138 C114 R149
AUDIO_R_IN 0 5600pF 2K C113 27pF 15K
2 EU 50V EU 10uF 50V EU IN1- 2 7 OUT2
AUDIO_R_OUT EU 16V EU
1 Q101 EU
R125 C108
MMBT3904(NXP) R145
0 5600pF EU IN1+ 3 6 IN2-
EU R137 6.8K
50V EU
SCART1_Lout
2K R154
EU EU
EU 5.6K 5.6K
EU VEE 4 5 IN2+ R153
SCART1_Rout
C115
27pF R148 R152
50V 15K 6.8K
DTV_R_OUT EU EU EU
R139 +3.3V_ST EU
2K C112
EU 10uF R189
16V 10K
Q102
EU
MMBT3904(NXP) SCART1_MUTE
EU R140
2K
EU
EU
AR105 33
CI_OE /PCM_OE
CI SLOT +5V_CI_ON
CI_WE
CI_IORD
/PCM_WE
/PCM_IORD
CI_IOWR /PCM_IOWR
EU
AR106 33
C100 C101 CI_ADDR[12] PCM_A[12]
22uF 0.1uF CI_ADDR[13] PCM_A[13]
10V 16V
EU EU CI_ADDR[14] PCM_A[14]
BUF2_FE_TS_DATA[0-7] AR108
REG /PCM_REG 33 EU
BUF2_FE_TS_DATA[0] BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[0-7]
+5V EU BUF2_FE_TS_DATA[1] BUF1_FE_TS_DATA[1]
JK102 CI_ADDR[8]
AR107 33
PCM_A[8] BUF2_FE_TS_DATA[2] BUF1_FE_TS_DATA[2]
10067972-000LF
R151 CI_ADDR[9] PCM_A[9] BUF2_FE_TS_DATA[3] BUF1_FE_TS_DATA[3]
10K R102 EU AR103
EU 100 35 CI_ADDR[10] PCM_A[10]
EU 33
36 EU PCM_D[3] AR109
/CI_CD1 CI_ADDR[11] PCM_A[11] 33 EU
37 3 PCM_D[4] BUF2_FE_TS_DATA[4] BUF1_FE_TS_DATA[4]
EU
AR100 33 38 4 PCM_D[5] BUF2_FE_TS_DATA[5] BUF1_FE_TS_DATA[5]
CI_TS_DATA[4]
39 5 PCM_D[6] R133
10K
+3.3V_CI BUF2_FE_TS_DATA[6] BUF1_FE_TS_DATA[6]
CI_TS_DATA[5]
PCM_D[7] EU +3.3V_CI
CI_TS_DATA[6] 40 6 BUF2_FE_TS_DATA[7] BUF1_FE_TS_DATA[7]
R130 33 EU
CI_TS_DATA[7] 41 7 1/16W /PCM_CE
R1315% 33 EU BUF1_FE_TS_DATA[0-7]
42 8
R111 43 9 CI_ADDR[10] EU IC100 EU
10K CI_OE R165
EU 44 10 CI_ADDR[11] TC74LCX244FT C105 AR110
CI_IORD 10K 0.1uF 33
45 11 CI_ADDR[9] 16V EU
CI_IOWR BUF1_FE_TS_SYN BUF2_FE_TS_SYN
46 12 CI_ADDR[8] 1OE VCC
BUF2_FE_TS_SYN CI_DET
1
EU 20 BUF1_FE_TS_VAL_ERR BUF2_FE_TS_VAL_ERR
47 13 CI_ADDR[13] 1A1 2OE
BUF2_FE_TS_DATA[0] PCM_A[0] 2 19 BUF1_FE_TS_CLK BUF2_FE_TS_CLK

48 14 CI_ADDR[14] 2Y4 1Y1
3 18
BUF2_FE_TS_DATA[1] CI_ADDR[7] CI_ADDR[0]
49 15 CI_WE 1A2
4 17
2A4
BUF2_FE_TS_DATA[2] PCM_A[1] PCM_A[7]

READY 50 16 R132 100
/PCM_IRQA CI_ADDR[6]
2Y3
5 16
1Y2
CI_ADDR[1]
BUF2_FE_TS_DATA[3] R112 EU
51 17 1A3
6 15
2A3
0 R128 0 PCM_A[2] PCM_A[6]

52 18 2Y2
7 14
1Y3
READY CI_ADDR[5] CI_ADDR[2]

53 19 BUF2_FE_TS_VAL_ERR 1A4
8 13
2A2
BUF2_FE_TS_DATA[4] PCM_A[3] PCM_A[5]

54 20 BUF2_FE_TS_CLK 2Y1
9 12
1Y4
BUF2_FE_TS_DATA[5] CI_ADDR[4] CI_ADDR[3]

R109 55 21 CI_ADDR[12] GND 2A1 CI POWER ENABLE CONTROL
BUF2_FE_TS_DATA[6] 10K 10 11
PCM_A[4]
EU 56 22 CI_ADDR[7]
BUF2_FE_TS_DATA[7] CI_ADDR[6] +5V +5V_CI_ON
BUF2_FE_TS_DATA[0-7] 57 23 Q114
R100 EU 33 58 24 CI_ADDR[5] RSR025P03
EU
L100
120-ohm
PCM_RST
R101 EU 33 CI_ADDR[4] S EU
/PCM_WAIT 59 25 D
60 26 CI_ADDR[3]
REG
AR101 33 61 27 CI_ADDR[2] C131 C104 R198
CI_TS_CLK
5%
1/16W
EU CI_ADDR[1] R184 R187 G 0.1uF 0.1uF 10K
CI_TS_VAL 62 28 10K 10K 16V 16V READY
AR104 CI_ADDR[0] READY EU READY EU
CI_TS_SYNC 63 29
R110 33
0 64 30 EU PCM_D[0]
READY PCM_D[1]
AR102 33
65 31 AO3407A 3.3V_CI
CI_TS_DATA[0] PCM_D[2]
D
EU 66 32
CI_TS_DATA[1] 67 33 +3.3V +3.3V_CI
CI_ADDR[0-14] R188
CI_TS_DATA[2] 2K
68 34 EU
G
CI_TS_DATA[3] MULTI L101
R150 2
G2 69 G1
1 C Q114-*1 120-ohm
10K EU
EU R103 B Q113
+5V 100 PCM_5V_CTL MMBT3904(NXP)
EU PCM_D[0-7] R181 EU
/CI_CD2 PCM_D[0-7] 10K C136 C137
EU E 0.1uF 0.1uF
16V 16V
READY EU
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS GP4_S7LR 2011-10-20
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART,CI Slot 1 6
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
SPDIF MULTI
HDMI_1 SIDE_HDMI_1 SIDE_HDMI_2 JK204

JST1223-001
JK204-*1
2F01TC1-CLM97-4F
5V_HDMI_2 5V_HDMI_3
5V_HDMI_1 +5V +5V +5V GND
GND 1
1
For CEC +5V
Fiber Optic
Fiber Optic
BODY_SHIELD
JK200-*1 BODY_SHIELD 5V_DET_HDMI_2 R240 5V_DET_HDMI_3 VCC
SHIELD 5V_DET_HDMI_1 YKF45-7058V
R226 1K +3.3V_ST VCC 2
2
R200 HDMI1_NON Screw
DATA2+
1K C R203 SIDE_HDMI_2 C R209
1K 1
20 SIDE_HDMI_1 20
20 HDMI_1 C R202 DATA2_SHIELD
2 10K 10K C219
10K DATA2-
DATA1+
3
B SIDE_HDMI_1 B SIDE_HDMI_2 0.1uF R285
B HDMI_1 DATA1_SHIELD
4
HPD2 HPD3 VINPUT 16V 100 3 VIN

5
19 19 Q202
3
HPD1 DATA1-
R227 Q201 R237 R241 R250 SPDIF_OUT
1.8K SIDE_HDMI_2MMBT3904(NXP)
6
19 R201 Q200 R217 1.8K SIDE_HDMI_1 MMBT3904(NXP) 10K 10K
JP204
JP207
DATA0+
7
SIDE_HDMI_2 4
4
1.8K HDMI_1 MMBT3904(NXP) 10K DATA0_SHIELD
SIDE_HDMI_1 E SIDE_HDMI_1 SIDE_HDMI_2
JP201
DATA0-
8
18 18 E R260 C220
HDMI_1 E HDMI_1 9
R230 R244 56K R269 10pF
18 R204
CLK+
10
3.3K 3.3K
SHIELD
3.3K
CLK_SHIELD
READY 27K FIX_POLE 50V
R287 SIDE_HDMI_1
R231 R289 SIDE_HDMI_2
11
CLK-
12
17 R286 17 R288 READY
17 R281 R282 HDMI_133
R207 CEC
13
10K 10K 33 10K 10K R245
10K 10K HDMI_1
NC
SCL
14
SIDE_HDMI_1 SIDE_HDMI_1 SIDE_HDMI_1 DDC_SDA_2 SIDE_HDMI_2 SIDE_HDMI_233 SIDE_HDMI_2
DDC_SDA_3
HDMI_1 HDMI_1 DDC_SDA_1 SDA
15
16
16 16
16 DDC/CEC_GND
17
+5V_POWER
18
DDC_SCL_2 DDC_SCL_3 R261 D224
DDC_SCL_1 HPD
19 15 R232 15 R246 0 MMBD301LT1G
15 R208 20 33 33 SIDE_HDMI_2 READY 30V
33 HDMI_1 SIDE_HDMI_1 READY
JP205
JP208
SHIELD
HDMI_ARC 14 14 R268
JP202
14 100
CEC_REMOTE CEC_REMOTE CEC_REMOTE CEC_REMOTE_S7
CEC_REMOTE 13 13
13 PEN_TOUCH
CK-_HDMI2 CK-_HDMI3 S B D +5V_ST 1A SPEC
CK-_HDMI1 12 12
12
11 11
D222
READY
SIDE USB D225
B140A
IC207
AP2337SA-7
SWITCH ADDED +3.3V
CK+ CK+
PEN_TOUCH +3.3V +5V +5V_ST
11
CK+ 10 10 Q203 VIN 3 2 VOUT
10 CK+_HDMI1 CK+_HDMI2 CK+_HDMI3 BSS83 40V

1
GND
IC204
D0- D0- READY AP2191SG-13
D0- 9 D0-_HDMI2 9 D0-_HDMI3
9 D0-_HDMI1 R264
D0_GND D0_GND Capacitors on VBUSA should be 10K NC GND
D0_GND 8 8 R270 R243 R247
8 G placed as closd to connector as possible. 8 1
10K 0 0
D0+ D0+ OUT_2
7 2
IN_1 READY
D0+ 7 D0+_HDMI2 7 D0+_HDMI3 JK209 $0.11
7 D0+_HDMI1 D1- D1- 3AU04S-305-ZC-(LG) C212 C213 OUT_1
6 3
IN_2
D1- 6 D1-_HDMI2 6 D1-_HDMI3 0.1uF 10uF R258

6 D1-_HDMI1 16V 10V 33 FLG
5 4
EN
D1_GND D1_GND USB1_OCD USB1_CTL
1
D1_GND 5 5 R271
USB DOWN STREAM

5 33
D1+ D1+
D1+ 4 D1+_HDMI2 4 D1+_HDMI3
4
2
D1+_HDMI1 D2- D2- SIDE_USB_DM
D2- 3 D2-_HDMI2 3 D2-_HDMI3
3 D2-_HDMI1 D2_GND D2_GND
D2_GND 2 2
3
2 SIDE_USB_DP
D2+ D2+
D2+ 1 D2+_HDMI2 1 D2+_HDMI3
1 D2+_HDMI1
4
5
JK201 JK202
JK200 SIDE_HDMI_1 SIDE_HDMI_2 10mm
HDMI_1
JK211
PPJ239-01 COMPONENT2 RS232C +3.3V_ST S7_TXD
ETHERNET
[RD1]E-LUG S7_RXD +3.3V_ST
NON_EU 6H R283 0 PM_TXD
PM_RXD
C229
R284 0 0.1uF +2.5V
JK203 IC206 16V
SPG09-DB-009 R278 R279 MAX3232CDR
JK210
5H [RD1]O-SPRING_2 JK208
10K 10K
XRJV-01V-0-D12-080
1/16W
5%
PPJ234-02
JK210-*1
EU 1
[GN]E-LUG
R251
+3.3V 1 VCC C1+ 1 TP
BS-R430051
16 1 R296
6A 75
4H [RD1]CONTACT_2 [GN]O-SPRING
6 C228
0.1uF
10K
2
2 1
1 ET_NET_UDE
COMP2_Y+ R259 R276 100 READY

2 GND V+ 16V 2
2
5A 10K R266 15 2
R299 [GN]CONTACT 1K COMP2_DET 3 3
0 +5V_ST 3 TN 3
7 R277 C225
5G [WH1]O-SPRING 4A
[BL]E-LUG-S
100 DOUT1
14 3
C1- 0.1uF
16V 4
4
4
R252 3 4 RP
R265 5
5
7B 75 10K
8 R228
[BL]O-SPRING AV2_DET 10K RIN1 C2+ 5 6
6
USA 13 4 ET_NET 5
COMP2_Pb+
4F [RD1]CONTACT_1 5B R267 4 C226 7
7
[RD]E-LUG-S 1K TX 0.1uF 6
R229 ROUT1 C2- 6 RN 8
R253 9 C 12 5 16V 8
7C 75 100K
Q204 B USA 7 C200 9
[RD]O-SPRING_1 5 0.1uF D200 D204 D205 D206
5F [RD1]O-SPRING_1 COMP2_Pr+ MMBT3904(NXP)
R233 DIN1 V-
7
16V 5.6V 5.6V 5.6V 5.6V 9
5C 10 USA 11 6 ET_NET ET_NET ET_NET ET_NET ET_NET

[RD]CONTACT_1 E 100K 8
USA 8
4C DIN2 DOUT2
COMP2_L_IN 10 7
7F [RD1]E-LUG-S R256 10K R274 0 NON_RGB
9
PC_SER_DATA
5D [WH]O-SPRING R254 R262 R275 0 NON_RGB 9
470K 12K PC_SER_CLK ROUT2 RIN2
9 8
4E R273 R291
5E [BL1]O-SPRING [RD]CONTACT_2
R257 10K COMP2_R_IN C227 0 0
0.1uF ET_NET ET_NET
5E [RD]O-SPRING_2 16V
R255 R263
470K 12K R280 R290
0 0
ET_NET ET_NET
7E [BL1]E-LUG-S 6E [RD]E-LUG
4D [GN1]CONTACT
5D [GN1]O-SPRING
RGB PC PC AUDIO
JK207
JK205 PEJ027-04
+5V_ST E_SPRING
6D [GN1]E-LUG SPG09-DB-010 USA 3
JK206 6A T_TERMINAL1
R297 R298 PEJ027-04 IR
10K 10K
3 E_SPRING
6N [RD2]E-LUG 7A B_TERMINAL1
RED_GND
6 T_TERMINAL1
GND_2 R214 6A R_SPRING
1 4 R213
NON_EU 11 RED 75 R220 0
DSUB_R+
5N [RD2]O-SPRING_2 R234
10K
GREEN_GND 7A B_TERMINAL1 10K
PC_R_IN 5 T_SPRING
NON_USA
COMP1_R_IN 7 DDC_DATA
1/16W
R215
NON_EU
2 12 RGB_DDC_SDA
NON_EU
GREEN 75 4 R_SPRING R218 R222

R235 R236 470K 12K B_TERMINAL2
5%
DSUB_G+ 7B
470K 12K BLUE_GND TX
4N [RD2]CONTACT 8
H_SYNC
R205
33 R216 5 T_SPRING R210
DSUB_HSYNC +3.3V 6B T_TERMINAL2 10
NON_EU 3 13 BLUE 75 USA
R239 DSUB_B+ R221
10K NC 7B B_TERMINAL2 10K
9 R206
NON_EU
NON_EU
COMP1_L_IN PC_L_IN
5M [WH2]O-SPRING R238
470K
R242
12K 4 14
V_SYNC 33
DSUB_VSYNC R224
GND_1 C202 C203 R225 6B T_TERMINAL2 R219 R223
10K 470K 12K
10pF 10pF 1K
SYNC_GND 50V 50V
10 DSUB_DET
DDC_CLOCK
5L [RD2]O-SPRING_1 5 15 DDC_GND
RGB_DDC_SCL
PC_SER_DATA
SC1_R+/COMP1_Pr+ R212
10
PC_SER_CLK
16 R211
7L [RD2]E-LUG-S 10
SHILED
5K [BL2]O-SPRING
SC1_B+/COMP1_Pb+ GND
7K [BL2]E-LUG-S
+3.3V
NON_EU NON_EU
R248
4J [GN2]CONTACT 10K R249
1K
COMP1_DET
5J [GN2]O-SPRING
SC1_G+/COMP1_Y+
6J [GN2]E-LUG

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK INTERFACE
2 6
TUNER FE_TS_DATA[0]
FE_TS_DATA[1]
FE_TS_DATA[2]
FE_TS_DATA[3]
AR300 FNIM
33
BUF1_FE_TS_DATA[0]
BUF1_FE_TS_DATA[1]
BUF1_FE_TS_DATA[2]
BUF1_FE_TS_DATA[3]
AR301 FNIM
33
FE_TS_DATA[4] BUF1_FE_TS_DATA[4]
TUNER OPT1 OPT2 OPT3 FE_TS_DATA[7] BUF1_FE_TS_DATA[7]
TDSS-G101D DVB-T/C HNIM X FE_TS_DATA[0-7] AR302

33
FNIM
FE_TS_SYN BUF1_FE_TS_SYN
TDSS-H101F ATSC HNIM X FE_TS_VAL_ERR BUF1_FE_TS_VAL_ERR

FE_TS_CLK BUF1_FE_TS_CLK
TDSH-T101F DVB-T_SCA HNIM RF_SW

TDSN_B001F SBTVD FNIM RF_SW
TDSN_G201D DVB_T2 FNIM X RF_SWITCH
R310
1K
RF_SWITCH_CTL
C307
0.1uF
16V
RF_SWITCH
Close to Tuner Pin

+3.3V_TU
+3.3V_TU +1.8V_TU +2.5V_TU
TU304 TU303 TU302 TU301 TU300
TDSS-G101D TDSS-H101F TDSH-T101F
TDSN-G301D TDSN_B001F
DVB_T/C ATSC DVB_T_SCA
DVB_T2 SBTVD
RF_S/W_CTL NC NC RF_S/W_CTL R311
NC_1 1 1 1 1 R308 R309 10K
1 R301 2.2K 2.2K
RESET RESET RESET RESET 100
RESET 2 2 2 2
2 TUNER_RESET
SCL R307 TU_SCL
SCL SCL SCL SCL 22
3 3 3 3
3
SDA SDA SDA SDA R306 22 TU_SDA
SDA 4 4 4 4
4
+B1[3.3V] +3.3V +B1[3.3V] +B1[3.3V]
+B1[3.3V] 5 5 5 5 16V C304 C305
5 C302 C303 0.1uF 68pF 68pF C311
SIF SIF SIF SIF C310 50V 50V 0.1uF
SIF 6 6 6 6 0.1uF 10uF
6 16V 16V 16V
+B2[1.8V] +1.8V +B2[1.8V] +B2[1.8V]
+B2[1.8V] 7 7 7 7
7
CVBS CVBS CVBS CVBS
8
CVBS 8 8 8 8 DVB_T2 0 R302 Close to Tuner Pin
NC_1 IF_AGC IF_AGC IF_AGC
+B3[2.5V] 9 9 9 9 HNIM 0 R303
9 IF_AGC_MAIN READY
NC_2 DIF[P] DIF[P] DIF[P] HNIM 0 R304 R313
NC_2 10 10 10 10 IF_P_MSTAR
10 0
NC_3 DIF[N] DIF[N] DIF[N] HNIM 0 R305
NC_3 11 11 11 11 IF_N_MSTAR
11 +5V
+B4[3.3V] +B3[3.3V]
+1.25V_TU 12 12
12 12 12
+B5[1.23V] +B4[1.23V] R316
13 13 470 R317
SHIELD SHIELD SHIELD 82
NC_4 NC_4 C308
C300 C301 14 0.1uF TU_SIF
10uF 14 E
0.1uF 16V
6.3V 16V GND GND
FNIM FNIM 15 15
R312 MMBT3906(NXP)
ERROR ERROR READY 4.7K B Q301
16 R300 0
16
SYNC C
SYNC 17
17 FE_TS_SYN
VALID VALID
18 18 FE_TS_VAL_ERR
MCLK MCLK
19 19 FE_TS_CLK
D0 FE_TS_DATA[0] FE_TS_DATA[0-7]
D0 20
20
D1 D1 FE_TS_DATA[1]
21 21
D2 D2 FE_TS_DATA[2]
22 22
TU_CVBS
D3 D3 FE_TS_DATA[3]
23 23
D4 D4 FE_TS_DATA[4]
24 24
D5 D5 FE_TS_DATA[5]
25 25
D6 D6 FE_TS_DATA[6]
26 26
D7 D7 FE_TS_DATA[7]
27 27
28 28
SHIELD SHIELD

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
Tuner block 3 6
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
TUNER
VIDEO/AUDIO IC400
LGE2111A-T8 R450 HNIM
PCM_D[0-7]
IC400
LGE2111A-T8 LVDS IC400
LGE2111A-T8
100 C451 0.1uF READY HNIM
IF_P_MSTAR
HNIM C456 C459
IC400-*1 PCM_D[0] W21
LGE2111A-TE HNIM 100pF 100pF PCMDATA[0]/GPIO126
J2 AC4
50V 50V PCM_D[1] AA18
CK+_HDMI2 RXACKP VIFP C452 0.1uF PCMDATA[1]/GPIO127
J3 AD3 IF_N_MSTAR PCM_D[2] AB22 C7 AB25
C7 AB25 CK-_HDMI2 RXACKN VIFM R451 100 C460 PCMDATA[2]/GPIO128 5V_DET_HDMI_1 GPIO36 LVA0P RXA4-
GPIO36 LVA0P K3
HNIM PCM_D[3] AE20
E6 AB23
E6
GPIO37 LVA0N
AB23 D0+_HDMI2 RXA0P 100pF PCMDATA[3]/GPIO120
F5 AC25 J1 AC3 PCM_A[0-14] PCM_D[4] AA15 5V_DET_HDMI_2 GPIO37 LVA0N RXA4+
B6
GPIO38 LVA1P
AB24 D0-_HDMI2 RXA0N IP 50V HNIM PCMDATA[4]/GPIO119 F5 AC25
GPIO39 LVA1N
D1+_HDMI2
K2 AE3 C432 0.1uF R464 47 TU_SIF PCM_D[5] AE21 1/16W 5V_DET_HDMI_3
E5
GPIO40 LVA2P
AD25 RXA1P IM PCMDATA[5]/GPIO118 GPIO38 LVA1P RXA3-
D5 AC24
D1-_HDMI2
K1 C433 0.1uF R465 47 PCM_D[6] AB21 AE18 AR401 22 B6 AB24
GPIO41 LVA2N RXA1N PCMDATA[6]/GPIO117 NF_CE1Z/GPIO138 COMP1_DET GPIO39 LVA1N
B7
GPIO42 LVA3P
AE23
L2 AD4 C457 PCM_D[7] Y15 AC17 RXA3+
E7
GPIO45 LVA3N
AC23 D2+_HDMI2 RXA2P SIFP L400 PCMDATA[7]/GPIO116 NF_WPZ/GPIO198 /PF_WP E5 AD25
F7 AC22 L3 AC5 +3.3V 1000pF
50V AD18
/PF_CE0 AV/SC1_DET GPIO40 LVA2P RXACK-
GPIO46 LVA4P D2-_HDMI2 RXA2N SIFM 120-ohm NF_CEZ/GPIO137 D5 AC24
AB5
GPIO49 LVA4N
AD23
T5
Main READY PCM_A[0] W20 AC18 1/16W /PF_CE1 RXACK+
AB3
GPIO50
DDC_SDA_2 DDCDA_DA/GPIO24 R446 10K PCMADR[0]/GPIO125 NF_CLE/GPIO136 AMP_RESET_N GPIO41 LVA2N
A9 V23 T4 PCM_A[1] V20 AC19 AR400 22
/PF_OE B7 AE23
F4
GPIO51 Dvix only LVB0P
U24 DDC_SCL_2 DDCDA_CK/GPIO23 PCMADR[1]/GPIO124 NF_REZ/GPIO139 TUNER_RESET GPIO42 LVA3P RXA1-
GPIO52 LVB0N V5
HNIM HNIM PCM_A[2] W22 AD17
/PF_WE E7 AC23
AB1
I2C_SCKM0/GPIO53 LVB1P
V25 HPD2 HOTPLUGA/GPIO19 PCMADR[2]/GPIO122 NF_WEZ/GPIO140
N6 V24 PCM_A[3] AB18 AE17
PF_ALE PCM_5V_CTL GPIO45 LVA3N RXA1+
I2C_SDAM0/GPIO54 LVB1N PCMADR[3]/GPIO121 NF_ALE/GPIO141 F7 AC22
AB2
GPIO73 LVB2P
W25
AD2R452 R497 100 PCM_A[4] AA20 AD19
AC2
GPIO74 LVB2N
W23 IF_AGC 0 IF_AGC_MAIN PCMADR[4]/GPIO99 NF_RBZ/GPIO142 /F_RB GPIO46 LVA4P RXA0-
AA23 AE2 HNIM C450 C1612 PCM_A[5] AA21 AB5 AD23
LVB3P RF_AGC C435 100pF HNIM C1613 PCMADR[5]/GPIO101 AMP_SCL GPIO49 LVA4N
LVB3N
Y24
R437 0.047uF PCM_A[6] Y19 R438 RXA0+
AA25 0.1uF 50V 0.1uF PCMADR[6]/GPIO102 AMP_SDA AB3
LVB4P
AA24 0 25V HNIM PCM_A[7] AB17 GPIO50
LVB4N
READY HNIM HNIM PCMADR[7]/GPIO103 1K A9 V23
AE6
HNIM PCM_A[8] Y16
MODEL_OPT_1
LVACKP
AE24 I2C_SCKM1/GPIO75 TU_SCL PCMADR[8]/GPIO108 GPIO51 LVB0P RXB4-
AD24 AD6 PCM_A[9] AB19 H5 R486 100 AC_DET F4 U24
LVACKN
Y23 I2C_SDAM1/GPIO76 TU_SDA PCMADR[9]/GPIO110 GPIO_PM[0]/GPIO6 RF_SWITCH_CTL GPIO52 LVB0N RXB4+
LVBCKP PCM_A[10] AB20 K6
AB1 V25
LVBCKN
W24 PCMADR[10]/GPIO114 PM_UART_TX/GPIO_PM[1]/GPIO7 PM_TXD
PCM_A[11] AA16 K5 100 R449 I2C_SCKM0/GPIO53 LVB1P RXB3-
T25 PCMADR[11]/GPIO112 GPIO_PM[2]/GPIO8 DISP_EN N6 V24
GPIO196 AD1 +3.3V C447 5pF PCM_A[12] AA19 J6
GPIO193
U23 XIN PCMADR[12]/GPIO104 GPIO_PM[3]/GPIO9 5V_ON USB1_OCD I2C_SDAM0/GPIO54 LVB1N RXB3+
T24 AC1 PCM_A[13] AC21 K4 AB2 W25
XOUT
X-TAL_2 C448 5pF PCMADR[13]/GPIO107 GPIO_PM[4]/GPIO10 RL_ON
GPIO194
GND_2 GPIO73 LVB2P RXBCK-
3
T23
GPIO195 R5 R466 R468 PCM_A[14] AA17 L6
AC2 W23
SC_RE1 HOTPLUGB/GPIO20
3.3K PCMADR[14]/GPIO106 PM_UART_RX/GPIO_PM[5]/GPIO11 PM_RXD
3.3K R441 X400 C2 SCART1_MUTE GPIO74 LVB2N RXBCK+
PM_SPI_SCZ1/GPIO_PM[6]/GPIO12 AA23
AE9 D7 R461 22 1M 24MHz Y20 L5
CK+_HDMI3 RXCCKP SPDIF_IN/GPIO152 P_SDA /PCM_REG PCMREG_N/GPIO123 GPIO_PM[7]/GPIO13 /FLASH_WP LVB3P RXB1-
AC9 D6 R488 100 X-TAL_1 GND_1 M6 Y24
2
CK-_HDMI3 AC10
RXCCKN SPDIF_OUT/GPIO153 SPDIF_OUT +5V AB15
GPIO_PM[8]/GPIO14
M5
ERROR_DET LVB3N RXB1+
D0+_HDMI3 RXC0P /PCM_OE PCMOE_N/GPIO113 GPIO_PM[9]/GPIO15 AA25
AD9 AA22 C1 LVB4P RXB0-
D0-_HDMI3 AC11
RXC0N
E3
/PCM_WE AD22
PCMWE_N/GPIO197 PM_SPI_SCZ2/GPIO_PM[10]/GPIO16
M4
USB1_CTL AA24
D1+_HDMI3 RXC1P USB0_DM /PCM_IORD PCMIORD_N/GPIO111 GPIO_PM[11]/GPIO17 MODEL_OPT_3 LVB4N RXB0+
AD10 E2 R473 R476 /PCM_IOWR AD20
D1-_HDMI3
EU
RXC1N USB0_DP PCMIOWR_N/GPIO109
AE11 10K 10K A2 R489 33 SPI_SCK AE24
EU
D2+_HDMI3 RXC2P PM_SPI_SCK/GPIO1
AD11 AC12 AD21 D3 READY R487 33 LVACKP RXA2-
D2-_HDMI3 RXC2N USB1_DM SIDE_USB_DM /PCM_CE PCMCE_N/GPIO115 PM_SPI_CZ0/GPIO_PM[12]/GPIO0 /SPI_CS AD24
AE8 AE12
SIDE_USB_DP /PCM_IRQA AC20 B2 R432 22 SPI_SDI
DDC_SDA_3 DDCDC_DA/GPIO28 USB1_DP PCMIRQA_N/GPIO105 PM_SPI_SDI/GPIO2 LVACKN RXA2+
AD8 Y18 B1 R490 33 SPI_SDO Y23
DDC_SCL_3 DDCDC_CK/GPIO27 PCMCD_N/GPIO130 PM_SPI_SDO/GPIO3 LVBCKP RXB2-
AC8 Y21
HPD3 HOTPLUGC/GPIO21 /PCM_WAIT PCMWAIT_N/GPIO100 W24
C8 Y22 LVBCKN RXB2+
I2S_IN_BCK/GPIO150 SUB_SDA C461 C462 PCM_RST PCM_RESET/GPIO129
F2 D8
/CI_CD1 22 EU R458
CK+_HDMI1 RXDCKP I2S_IN_SD/GPIO151 SUB_SCL 0.1uF 0.1uF
F3 D9 R462 22 READY EU 22 R459 Y14 T25
CK-_HDMI1 G3
RXDCKN I2S_IN_WS/GPIO149 P_SCL 16V 16V /CI_CD2 U21
TS0CLK/GPIO87
AA10
CI_TS_CLK GPIO196
D0+_HDMI1 RXD0P EU PCM2_CE_N/GPIO131 TS0VALID/GPIO85 CI_TS_VAL CI_TS_DATA[0-7] U23
F1 B10 V21 Y12 GPIO193
D0-_HDMI1 RXD0N I2S_OUT_BCK/GPIO156 AUD_SCK PCM2_IRQA_N/GPIO132 TS0SYNC/GPIO86 CI_TS_SYNC T24
G2 C9 R20
D1+_HDMI1 RXD1P I2S_OUT_MCK/GPIO154 AUD_MASTER_CLK PCM2_CD_N/GPIO135 GPIO194
D1-_HDMI1
G1 B9 T20 Y13 CI_TS_DATA[0] T23
RXD1N I2S_OUT_SD/GPIO157 AUD_LRCH PCM2_WAIT_N/GPIO133 TS0DATA_[0]/GPIO77 GPIO195
H2 U22 Y11 CI_TS_DATA[1]
D2+_HDMI1 RXD2P
+3.3V PCM2_RESET/GPIO134 TS0DATA_[1]/GPIO78
H3 AA12 CI_TS_DATA[2]
D2-_HDMI1 RXD2N TS0DATA_[2]/GPIO79
R6 22 R479 D4 AB12 CI_TS_DATA[3]
DDC_SDA_1 DDCDD_DA/GPIO30 UART_TXD 22 UART1_TX/GPIO43 TS0DATA_[3]/GPIO80
U6 C10 R480 E4 AA14 CI_TS_DATA[4]
DDC_SCL_1 DDCDD_CK/GPIO29 I2S_OUT_WS/GPIO155 AUD_LRCK UART_RXD UART1_RX/GPIO44 TS0DATA_[4]/GPIO81
P5 R481 22 N25 AB14 CI_TS_DATA[5]
HPD1 HOTPLUGD/GPIO22 S7_TXD UART2_TX/GPIO65 TS0DATA_[5]/GPIO82
R4
EU R471 R472 R482 22 N24 AA13 CI_TS_DATA[6]
CEC_REMOTE_S7 CEC/GPIO5
C437 2.2uF 2.2K 2.2K S7_RXD UART2_RX/GPIO64 TS0DATA_[6]/GPIO83
AB9 B8 AB11 CI_TS_DATA[7]
AUL0
C438 AV/SC1_L_IN UART3_TX/GPIO47 TS0DATA_[7]/GPIO84
AA11 2.2uF A8
R404 22 P2
AUR0
Y9
AV/SC1_R_IN UART3_RX/GPIO48
AC15
DSUB_HSYNC R405 22 HSYNC0 AUL1 EU TS1CLK/GPIO98 BUF1_FE_TS_CLK
R3 AA9
I2C_SCL R477 22 P23 AD15 BUF1_FE_TS_DATA[0-7]
DSUB_VSYNC R406 33 C401 0.047uF VSYNC0 AUR1 I2C_SCKM2/DDCR_CK/GPIO72 TS1VALID/GPI96 BUF1_FE_TS_VAL_ERR
N2 AA7 NON_EU C472 2.2uF I2C_SDA R478 22 P24 AC16
DSUB_R+ R407 68 C402 0.047uF RIN0P AUL2 COMP1_L_IN I2C_SDAM2/DDCR_DA/GPIO71 TS1SYNC/GPIO97 BUF1_FE_TS_SYN
P3 AB8 NON_EU C478 2.2uF
R408 33 C403 0.047uF RIN0M AUR2
C443 COMP1_R_IN
N3 Y8 2.2uF RGB_DDC_SDA R469 22 D2 AD16 BUF1_FE_TS_DATA[0]
DSUB_G+ R409 68 C404 0.047uF GIN0P AUL3 COMP2_L_IN DDCA_DA/UART0_TX TS1DATA_[0]/GPIO88
N1 Y10 C444 2.2uF RGB_DDC_SCL R470 22 D1 AE15 BUF1_FE_TS_DATA[1]
R410 33 C405 0.047uF GIN0M AUR3 COMP2_R_IN DDCA_CK/UART0_RX TS1DATA_[1]/GPIO89
M3 AC7 C445 2.2uF AE14 BUF1_FE_TS_DATA[2]
DSUB_B+ R411 68 C406 0.047uF BIN0P AUL4 PC_L_IN TS1DATA_[2]/GPIO90
M2 AD7 C446 2.2uF AC13 BUF1_FE_TS_DATA[3]
R412 0 C407 1000pF BIN0M AUR4 PC_R_IN TS1DATA_[3]/GPIO91
R400 R403 M1 P21 AC14 BUF1_FE_TS_DATA[4]
10K 2.4K SOGIN0 PWM0 PWM0/GPIO66 TS1DATA_[4]/GPIO92
N23 AD12 BUF1_FE_TS_DATA[5]
PWM1 PWM1/GPIO67 TS1DATA_[5]/GPIO93
P22 AD13 BUF1_FE_TS_DATA[6]
COMP2_DET PWM2/GPIO68 TS1DATA_[6]/GPIO94
V2 R21 AD14 BUF1_FE_TS_DATA[7]
SC1_ID HSYNC1 SC_RE2 PWM3/GPIO69 TS1DATA_[7]/GPIO95
V3 W6 EU P20
SC1_FB
SC1_R+/COMP1_Pr+
R413
R414
33
68
C408
C409
0.047uF
0.047uF
U3
U2
VSYNC1
RIN1P
AUOUTL0
AUOUTL2
V6
V4
R442
SCART1_Lout LED_RED
F6
PWM4/GPIO70
PWM_PM/GPIO199
POWER IC400
LGE2111A-T8
RIN1M AUOUTL3
100
R415 33 C410 0.047uF T1 Y7
SC1_G+/COMP1_Y+ R416 C411 GIN1P AUOUTR0 EU
68 0.047uF T2 W5
SCART1_Rout
H6
R417 33 0.047uF GIN1M AUOUTR2 KEY1 SAR0/GPIO31
C412 R2 U5 R444 G5 K12 G10
SC1_B+/COMP1_Pb+ R418 68 0.047uF BIN1P AUOUTR3 KEY2 SAR1/GPIO32 AVDDLV_USB GND_32
C413 R1 100 G4 G11
BIN1M TOUCH_VER_CHK SAR2/GPIO33 GND_33
C414 1000pF T3 J5 G9 G12
SC1_SOG_IN SOGIN1 SAR3/GPIO34 VDDC_1 GND_34
R498 0 J4 H9 G13
AMP_MUTE SAR4/GPIO35 VDDC_2 GND_35
K10 G14
NON_EU VDDC_3 GND_36
AA2 C1406 0.1uF K11 G17
HSYNC2 VDDC_4 GND_37
R420 33 C415 0.047uF Y2 R23 C1407 0.1uF L10 G18
COMP2_Pr+ R421 68 C416 0.047uF RIN2P VSYNC_LIKE/GPIO145 +1.10V_VDDC VDDC_5 GND_38
AA3 C1408 0.1uF M12 G19
RIN2M VDDC_6 GND_39
R422 33 C417 0.047uF W2 AD5 R24 C1409 10uF M13 G24
COMP2_Y+ R423 GIN2P AUVRM SPI1_CK/GPIO201 VDDC_7 GND_40
68 C418 0.047uF Y3 R25 C1410 10uF N12 H11
R424 33 C419 0.047uF V1
GIN2M
AE5
C431 C434 C449 C454 L401 T21
SPI1_DI/GPIO202
P14
VDDC_8 GND_41
H12
COMP2_Pb+ BIN2P AUVAG 4.7uF 1uF 0.1uF 10uF BLM18SG121TN1D SPI2_CK/GPIO203 C1411 10uF VDDC_9 GND_42
R425 68 C420 0.047uF W3 AC6 T22 VDDC : 2026mA P15 H13
BIN2M AUVRP SPI2_DI/GPIO204 VDDC_10 GND_43
R426 0 C421 1000pF W1 R10 H14
SOGIN2 C1412 0.1uF VDDC_11 GND_44
AA6 MIUVDDC R14 H15
EARPHONE_OUTL VDDC_12 GND_45
AB6 C1413 10uF R15 H16
R427 33 C422 0.047uF EARPHONE_OUTR L405 VDDC_13 GND_46
AA8 C436 T10 H17
TU_CVBS CVBS0 120-ohm VDDC_14 GND_47
R428 EU 33EUC423 0.047uF Y4 Main 0.1uF H18
AV/SC1_CVBS_IN R429 33 C424 0.047uF CVBS1 GND_48
W4 C6 H19
COMP2_Y+ CVBS2 ET_RXD[0]/RP/GPIO60 RP GND_49
AA5 C5 Close to the Main IC P10 J9
TP MODEL OPTION
C400
1000pF
Y5
AA4
CVBS3
CVBS4
ET_TXD[0]/TP/GPIO57
A6
DDR IC400 FB_CORE
P19
R16
AVDD1P0
FB_CORE
GND_50
GND_51
J10
J11
50V CVBS5 ET_RXD[1]/RN/GPIO63 RN LGE2111A-T8 AVDDL_MOD GND_52
READY Y6 C4 PIN NAME PIN NO. HIGH LOW L11 J12
AA1
CVBSOUT0 ET_TXD[1]/LED1/GPIO56 ETH_LED1 M14
AVDD10_LAN GND_53
J13
DTV/MNT_VOUT CVBSOUT1
+2.5V DVDD_DDR GND_54
B5 MODEL_OPT_1 J14
ET_TX_CLK/TN/GPIO59 TN A9 3D 2D A11 B23 C1415 0.1uF GND_55
R433 68 C428 0.047uF AB4 C3 R402 EU 22 A-TMA0 C14
A_DDR3_A[0] B_DDR3_A[0]
D25
B-TMA0 J15
VCOM ET_TX_EN/GPIO58
A3
CI_DET A-TMA1 A_DDR3_A[1] B_DDR3_A[1] B-TMA1 C1416 0.1uF W9
GND_56
J16
ET_MDC/GPIO61 DSUB_DET R431 R443 R445 R460 B11 F22 L402 C1417 10uF AVDD2P5_ADC_1 GND_57
B3 49.9 49.9 49.9 49.9 MODEL_OPT_2 F4 FHD HD A-TMA2 F12
G22
B-TMA2 120-ohm W10 J18
ET_MDIO/GPIO62 AV2_DET 1% 1% 1% 1% A-TMA3 B-TMA3 Main AVDD2P5_ADC_2 GND_58
B4
C15
E24 AVDD2P5:172mA W11 J19
ET_COL/LED0/GPIO55 ETH_LED0 ET_NET ET_NET ET_NET ET_NET A-TMA4 A_DDR3_A[4] B_DDR3_A[4] B-TMA4 AVDD2P5_ADC_3 GND_59
E12 F21 L414 C425 0.1uF W12 J25
AVDD25_PGA:13mA AVDD25_REF GND_60
C426 C458 +3.3V A-TMA5 A14
E23
B-TMA5 K9
0.1uF 0.1uF A-TMA6 A_DDR3_A[6] B_DDR3_A[6] B-TMA6 C1418 0.1uF Y17
GND_61
K13
ET_NET ET_NET D11 D22 Main C439 AVDD25_LAN GND_62
N4 A-TMA7 B14
D24
B-TMA7 120-ohm 0.1uF K14
IRIN/GPIO4
A-TMA8 A_DDR3_A[8] B_DDR3_A[8] B-TMA8 L413 GND_63
T6 120-ohm V18 H10
ARC0 D12 D21 C440 AVDD_MOD_1 GND_64
N5 A-TMA9 A_DDR3_A[9] B_DDR3_A[9] B-TMA9 +3.3V_ST L403 0.1uF Main U19 K18
C16 C24 C469 0.1uF
HWRESET
A-TMA10 A_DDR3_A[10] B_DDR3_A[10] B-TMA10 120-ohm AVDD_MOD_2 GND_65
K19
TX C13 C25 Main Close to the Main IC GND_66
R1401 R401 R430 A-TMA11 A15
F23
B-TMA11 AVDD_NODIE:7.362mA K22
1K 1K 1K A-TMA12 A_DDR3_A[12] B_DDR3_A[12] B-TMA12 W14
GND_67
L8
SOC_RESET READY FHD 3D E11 E21 AVDD25_PGA GND_68
A-TMA13 A_DDR3_A[13] B_DDR3_A[13] B-TMA13 L406 W15 L9
B13 D23
MODEL_OPT_1 A-TMA14 A_DDR3_A[14] B_DDR3_A[14] B-TMA14 +3.3V 120-ohm AVSS_PGA GND_69
J8
Main GND_70
RF_SWITCH_CTL C471 0.1uF U7 L12
IC400-*2 IC400-*3 AVDD_NODIE GND_71
LGE2111A-TE SPIL LGE2111A-T8 SPIL L13
HDMI_ARC MODEL_OPT_3 F13 G20 C427 10uF
ARC A-TMBA0 B15
A_DDR3_BA[0] B_DDR3_BA[0]
F24
B-TMBA0 AVDD33 L7
AVDD_DVI_USB_1
GND_72
GND_73
L18
C7 AB25 R1400 R419 R467 A-TMBA1 E13
A_DDR3_BA[1] B_DDR3_BA[1]
F20
B-TMBA1 M7 L19
C7 AB25 C441 AVDD_DVI_USB_2 GND_74
16V
GPIO36 LVA0P
E6
GPIO36 LVA0P
AB23 E6
GPIO37 LVA0N
AB23 1K 1K 1K A-TMBA2 A_DDR3_BA[2] B_DDR3_BA[2] B-TMBA2 0.1uF P7 M8
F5
GPIO37 LVA0N
AC25 F5
GPIO38 LVA1P
AC25 C1419 R1406 READY HD 2D R7
AVDD3P3_MPLL GND_75
K8
B6
GPIO38 LVA1P
AB24 B6
GPIO39 LVA1N
AB24 0.1uF 150 C17 G25 AVDD_DMPLL GND_76
GPIO39 LVA1N E5 AD25 READY A-TMCK A_DDR3_MCLK B_DDR3_MCLK B-TMCK M10
E5
GPIO40 LVA2P
AD25
D5
GPIO40 LVA2P
AC24
A17 G23 Close to the Main IC GND_77
D5
GPIO41 LVA2N
AC24
B7
GPIO41 LVA2N
AE23 READY A-TMCKB B16
A_DDR3_MCLKZ B_DDR3_MCLKZ
F25
B-TMCKB C473 1uF M19 M11
B7 AE23
GPIO42 LVA3P DVDD_NODIE GND_78
E7
GPIO42 LVA3P
AC23 E7
GPIO45 LVA3N
AC23 A-TMCKE A_DDR3_MCLKE B_DDR3_MCLKE B-TMCKE L408 C474 10uF L14
F7
GPIO45 LVA3N
AC22 F7
GPIO46 LVA4P
AC22 R1407 120-ohm V7
GND_79
M15
AB5
GPIO46 LVA4P
AD23 AB5
GPIO49 LVA4N
AD23 63.4 Main C475 0.1uF AVDD_AU33 GND_80
AB3
GPIO49 LVA4N AB3
GPIO50
READY E14 D20 AU33:31mA W7 M16
GPIO50 A9 V23 AVDD_EAR33 GND_81
A9
GPIO51USA_SPIL_MAIN ICLVB0P
V23
F4
GPIO51EU_SPIL_MAIN ICLVB0P
U24
A-TMODT B12
A_DDR3_ODT B_DDR3_ODT
B25
B-TMODT C476 0.1uF M18
F4
GPIO52 LVB0N
U24
AB1
GPIO52 LVB0N
V25
+3.3V_ST SOC_RESET A-TMRASB A_DDR3_RASZ B_DDR3_RASZ B-TMRASB C442 R19
GND_82
M25
AB1 V25
I2C_SCKM0/GPIO53 LVB1P N6
I2C_SCKM0/GPIO53 LVB1P
V24
A12 B24 0.1uF C477 0.1uF VDDP_1 GND_83
N6
I2C_SDAM0/GPIO54 LVB1N
V24
AB2
I2C_SDAM0/GPIO54 LVB1N
W25 GND A-TMCASB C12
A_DDR3_CASZ B_DDR3_CASZ
A24
B-TMCASB T19 N10
AB2 W25
GPIO73 LVB2P VDDP_2 GND_84
GPIO73 LVB2P AC2 W23 A-TMWEB A_DDR3_WEZ B_DDR3_WEZ B-TMWEB N11
AC2
GPIO74 LVB2N
W23
AA23
GPIO74 LVB2N
AA23
Close to the Main IC GND_85
LVB3P LVB3P W18 N13
Y24 LVB3N
Y24 F11 E20 AVDD_LPLL_1 GND_86
LVB3N
AA25 LVB4P
AA25 A-TMRESETB A_DDR3_RESET B_DDR3_RESET B-TMRESETB W19 N14
LVB4P
AA24 AA24 C429 C487 AVDD_LPLL_2 GND_87
LVB4N LVB4N
22uF 10uF C479 1uF N15
GND_88
AE24 LVACKP
AE24 16V 16V B19 K24 C482 10uF V19 N16
LVACKP
AD24 LVACKN
AD24 READY A-TMDQSL A_DDR3_DQSL B_DDR3_DQSL B-TMDQSL L409
VDDP_NAND GND_89
N17
LVACKN
Y23 LVBCKP
Y23
R436 C18 K25
120-ohm C483 10uF GND_90
LVBCKP
W24 LVBCKN
W24
10 A-TMDQSLB A_DDR3_DQSLB B_DDR3_DQSLB B-TMDQSLB N19
LVBCKN
SOC_RESET Main C484 10uF J17
GND_91
K7
T25 T25 B18 J21 VDD33_T/VDDP/U3_VD33_2:47mA AVDD_DDR0_D_1 GND_92
GPIO196
GPIO196
U23
GPIO193
U23 A-TMDQSU A18
A_DDR3_DQSU B_DDR3_DQSU
J20
B-TMDQSU C485 0.1uF K15 P8
GPIO193 T24
VDD33_NAND AVDD_DDR0_D_2 GND_93
GPIO194
T24
GPIO194
T23
A-TMDQSUB A_DDR3_DQSUB B_DDR3_DQSUB B-TMDQSUB K16 P9
T23 AVDD_DDR0_D_3 GND_94
GPIO195
GPIO195 D400 R434 C430 E15 H24
L15 M9
KDS181 100K 0.1uF A-TMDML A_DDR3_DQML B_DDR3_DQML B-TMDML C453 C455 AVDD_DDR0_C GND_95
P11
16V A21 L20 0.1uF 0.1uF GND_96
A-TMDMU A_DDR3_DQMU B_DDR3_DQMU B-TMDMU K17 P13
AVDD_DDR1_D_1 GND_97
D17 L23 Close to the Main IC L17 P16
A-TMDQL0 G15
A_DDR3_DQL[0] B_DDR3_DQL[0]
J24
B-TMDQL0 +1.5V_DDR_IN M17 P17
A-TMDQL1 B21
L24
B-TMDQL1 L16 P18
C486 0.1uF AVDD_DDR1_C GND_100
A-TMDQL2 F15
J23
B-TMDQL2 P12
GND_101
A-TMDQL3 B22
M24
B-TMDQL3 C492 10uF R8
A-TMDQL4 A_DDR3_DQL[4] B_DDR3_DQL[4] B-TMDQL4 AVDD_DDR0:55mA E9
GND_102
R9
F14 H23 GND_EFUSE GND_103
A-TMDQL5 A_DDR3_DQL[5] B_DDR3_DQL[5] B-TMDQL5 AVDD_DDR1:55mA R11
<LM1 CHIP Config> A-TMDQL6
A22
D15
M23
K23
B-TMDQL6
L412
C493 0.1uF GND_104
R12
C488 C468 C470 GND_105
(AUD_SCK,AUD_MASTER_CLK,PWM1,PWM0) A-TMDQL7 A_DDR3_DQL[7] B_DDR3_DQL[7] B-TMDQL7 120-ohm 10uF 1uF 0.1uF C494 0.1uF A23
GND_1 GND_106
R13
C467 Main C497 10uF B17 R17
B51_NO_EJ : 4’b0000 Boot from 8051 with SPI flash G16 G21
1000pF Close to the Main IC GND_2 GND_107
A-TMDQU0 A_DDR3_DQU[0] B_DDR3_DQU[0] B-TMDQU0 C23 T8
SB51_WOS : 4’b0001 Secure B51 without scramble B20 L22 C498 10uF GND_3 GND_108
A-TMDQU1 A_DDR3_DQU[1] B_DDR3_DQU[1] B-TMDQU1 A5 T9
SB51_WS : 4’b0010 Secure B51 with scramble F16 H22 GND_4 GND_109
A-TMDQU2 A_DDR3_DQU[2] B_DDR3_DQU[2] B-TMDQU2 C11 N7
MIPS_SPI_NO_EJ : 4’b0100 Boot from MIPS with SPI flash C21 K20 GND_5 GND_110
MIPS_SPI_EJ_1 : 4’b0101 Boot from MIPS with SPI flash E16 H20 GND_6 GND_111
MIPS_SPI_EJ_2 : 4’b0110 Boot from MIPS with SPI flash A20 L21 GND_7 GND_112
A-TMDQU5 A_DDR3_DQU[5] B_DDR3_DQU[5] B-TMDQU5 D14 T13
MIPS_WOS : 4’b1001 Secure MIPS without scramble D16 H21 GND_8 GND_113
MIPS_WO : 4’b1010 Secure MIPS with scramble C20 K21 GND_9 GND_114
GND_10 GND_115
E17 T16
GND_11 GND_116
E18 T17
GND_12 GND_117
E19 U8
+3.3V E22
GND_13 GND_118
U9
CLose to Saturn7M IC CLose to Saturn7M IC F8
GND_14 GND_119
U10
GND_15 GND_120
1K READY
1K READY
1K READY
1K READY
F17 U11
GND_16 GND_121
F18 U12
VCC_1.5V_DDR VCC_1.5V_DDR GND_17 GND_122
R455
R439
R447
R453
R456
F19 U13
GND_18 GND_123
G8 U14
1K
GND_19 GND_124
H8 U15
GND_20 GND_125
R483 R491 N22 U16
AUD_SCK 1K 1K N21
GND_21 GND_126
U17
AUD_MASTER_CLK 1% 1% N20
GND_22 GND_127
R18
GND_23 GND_128
PWM1 A-MVREFCA M22 V9
GND_24 GND_129
B-MVREFCA M21 V10
PWM0 M20
GND_25 GND_130
V11
1K READY
GND_26 GND_131
LED_RED R484 C463 C464 R492 C465 C466 F10 V12
GND_27 GND_132
1K 0.1uF 1000pF 1K 0.1uF 1000pF
R463
R440
R448
R454
R457
V15 V14
1% 1% W16
GND_28 GND_133
V17
1K
1K
1K
1K
GND_29 GND_134
V8 T7
GND_30 GND_135
T18 E8
GND_31 GND_136

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN 4 6
IC501
Key/IR
A1
A2
MMBD6100
H5TQ1G63DFR-H9C
D500*-1
MULTI
VCC_1.5V_DDR
DDR3 Memory LVDS +3.3V_ST
NAND Flash IC504
1GBit x 2 P501 1GBit H27U1G8F2BTR-BC
C
+5V 12507WS-08L
M8 N3 A-TMA0 +5V
A-MVREFCA VREFCA A0 R515 +3.3V
R502 P7 USA 4.7K R518
A-TMA1
5.48VTO5.76V
1K A1 NC_1 NC_29
1% P3 100
A-TMA2 1 1 48
R512
4.7K
R513
4.7K
R577
4.7K
A2 IR
ZD502
A-MVREFDQ H1 N2 A-TMA3 +3.3V_ST +3.3V NC_2 NC_28
VREFDQ A3 C517 2 47
P8 A-TMA4 10pF
R503 A4 50V 2 NC_3 NC_27
1K P2 A-TMA5 3 46
R505 A5 R540 R542 PCM_A[0-7]
1% L8 R8
5.48VTO5.76V
A-TMA6 10K 10K R517 NC_4 NC_26 AR518
A1
A2
ZQ A6 100 4 45
240 R2 A-TMA7 3 22
C501 C503 A7 LD500 KEY1 NC_5 I/O7
ZD501
0.1uF 1000pF 1% T8 A-TMA8 5 44 PCM_A[7]
A8 D500 C534
5.48VTO5.76V
B2 R3 R516
A-TMA9 KDS184 C
100 220pF R565 R568 NC_6 I/O6
VDD_1 A9 50V PCM_A[6]
C
D9 L7 B KEY2 4 1K 4.7K 6 43
C524 10uF A-TMA10
VDD_2 A10/AP 2K R/B I/O5
ZD500
C525 0.1uF G7 R7 A-TMA11 C535 7 42 PCM_A[5]
R579 E Q500 220pF R514 /F_RB
5.48VTO5.76V
VDD_3 A11
C526 0.1uF K2 N7 A-TMA12 MMBT3904(NXP) 50V 22 5 RE I/O4
VDD_4 A12/BC LED_RED 8 41 PCM_A[4]
C527 0.1uF K8 T3 A-TMA13 P500 +3.3V_ST /PF_OE
47K
ZD503
VDD_5 A13 C520 CE NC_25
C528 0.1uF N1 104060-8017 R578 10pF 9 40
VDD_6 P503 50V 6 /PF_CE0
C529 0.1uF N9 M7 TF05-51S
R538 R539 NC_7 NC_24
VDD_7 NC_5 A-TMCK 4.7K 4.7K 10 39
C530 0.1uF R1 R519 R566 C554
5.48VTO5.76V
VDD_8 A-TMCKB 1 1 100 1K NC_8 NC_23 10uF
C531 0.1uF R9 M2 A-TMBA0 READY 7 READY 11 38
VDD_9 BA0 2 2 R576 0 SUB_SCL C550
C532 0.1uF N8 C522
A-TMBA1 0.1uF VCC_1 VCC_2
ZD507 ZD506
10V
BA1 R509 R511 3 R536 0 10pF
M3 3 UART_RXD R520 50V 12 37
5.48VTO5.76V
C533 0.1uF A-TMBA2 56 56 100READY
BA2 1% 1%
4
4 R537 0 8 VSS_1 VSS_2 C555
A1 UART_TXD SUB_SDA C523 13 36 0.1uF
5
VDDQ_1 5 10pF
A8 J7 6 50V NC_9 NC_22
VDDQ_2 CK C543 6 READY 9 14 35
C1 K7 7
VDDQ_3 CK 0.01uF 7 NC_10 NC_21
C9 K9 A-TMCKE 50V 8
15 34
VDDQ_4 CKE 8
5.48VTO5.76V
D2 9
CLE NC_20
VDDQ_5 9 +3.3V_ST 16 33 AR519
E9 L2 10 /PF_CE1 22
ZD505 ZD504
5.48VTO5.76V
VDDQ_6 CS 11 10 ALE I/O3
Hynix_1G_1600
F1 K1 A-TMODT RXA0- 17 32 PCM_A[3]
VDDQ_7 ODT 12 11 C547 PF_ALE IC504-*1
K9F1G08U0D-SCB0
IC501-*1
H5TQ1G63DFR-PBC H2 J3 A-TMRASB RXA0+ 0.1uF WE I/O2 SS
N3 M8 VDDQ_8 RAS VCC_1.5V_DDR 13
12 16V 18 31 PCM_A[2] NC_1
1 48
NC_29
P7
P3
N2
A0
A1
A2
VREFCA
H1
H9 K3 A-TMCASB RXA1- /PF_WE NC_2
2 47
NC_28
P8
P2
A3
A4
VREFDQ
VDDQ_9 CAS 14
RXA1+ 13 WP I/O1
NC_3
3 46
NC_27
L3 PCM_A[1]
A5
R8
A6 ZQ
L8 NC_4 NC_26
4 45
R2
T8
R3
A7
A8
B2
WE A-TMWEB R506 15 /PF_WP 19 30 NC_5
5 44
I/O7
L7
R7
A9
A10/AP
A11
VDD_1
VDD_2
VDD_3
D9
G7
J1 10K 14 NC_6
6 43
I/O6
N7
T3
A12/BC VDD_4
K2
K8
16 R558 NC_11 I/O0 PCM_A[0]
R/B
7 42
I/O5
M7
A13 VDD_5
VDD_6
N1
N9 NC_1 RXA2- 15 0 20 29 RE I/O4
M2
N8
A15
BA0
VDD_7
VDD_8
VDD_9
R1
R9 J9 T2 A-TMRESETB 17 CE
8
9
41
40
NC_25
M3
BA1
BA2
VDDQ_1
A1 NC_2 RESET RXA2+ 16 R556 R567 NC_12 NC_19 NC_7
10 39
NC_24
J7
K7
K9
CK
CK
VDDQ_2
VDDQ_3
A8
C1
C9
L1 18
3.3K 1K 21 28 NC_8
11 38
NC_23
L2
CKE
CS
VDDQ_4
VDDQ_5
VDDQ_6
D2
E9 NC_3 17
VCC_1
12 37
VCC_2
K1
J3
ODT VDDQ_7
F1
H2 L9 19
NC_13 NC_18
VSS_1
13 36
VSS_2
K3
L3
RAS
CAS
VDDQ_8
VDDQ_9
H9
NC_4 RXACK- NC_9

14 35
NC_22
T2
WE
RESET
NC_1
NC_2
J1
J9
T7 F3 20 18 22 27 NC_10
15 34
NC_21
NC_3
L1
L9
A-TMA14 DQSL A-TMDQSL RXACK+ CLE NC_20

F3
G3
DQSL
NC_4
NC_6
T7
NC_6 21 19 NC_14 NC_17 ALE
16 33
I/O3
G3
DQSL
17 32
C7
B7
DQSU VSS_1
A9
B3
A-TMDQSLB RXA3- 23 26 WE
18 31
I/O2
E7
DQSU
DML
VSS_2
VSS_3
VSS_4
E1
G8 DQSL 22 20 WP
19 30
I/O1
D3
E3
F7
DMU
DQL0
VSS_5
VSS_6
VSS_7
J2
J8
M1
M9
RXA3+ NC_15 NC_16 NC_11
20 29
I/O0
23 NC_12 NC_19
F2
F8
DQL1
DQL2
DQL3
VSS_8
VSS_9
VSS_10
P1
P9
A9 C7 RXA4- 21 24 25 NC_13
21 28
NC_18
H3
H8
DQL4 VSS_11
T1
T9
A-TMDQSU 22 27
G2
H7
DQL5
DQL6
VSS_12
VSS_1 DQSU 24
RXA4+ 22
NC_14
23 26
NC_17
D7
C3
DQL7
DQU0
VSSQ_1
VSSQ_2
B1
B9
D1
B3 B7 A-TMDQSUB
NC_15
24 25
NC_16
25
C8
C2
DQU1
DQU2
DQU3
VSSQ_3
VSSQ_4
VSSQ_5
D8
E2 VSS_2 DQSU 23
A7
A2
B8
DQU4
DQU5
VSSQ_6
VSSQ_7
E8
F9
G1
E1 26
A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9
VSS_3 24
G8 E7 A-TMDML HD 27
VSS_4 DML RXB0- 25
J2 D3 A-TMDMU 28
SS_1G_1600 VSS_5 DMU RXB0+ 26
J8 SS_1G_1333
29
VSS_6 IC501-*3
SS_2G_1333
IC501-*4 RXB1-
IC501-*2
K4B1G1646G-BCK0
M1 E3
K4B1G1646G-BCH9 K4B2G1646C
30 27
A-TMDQL0 N3 M8 N3 M8
RXB1+
DQL0
A0 VREFCA
N3
P7
A0
A1
VREFCA
M8
VSS_7 P7
P3
A0
A1
VREFCA P7
P3
A1
A2
31 28
P3
N2
P8
A2
A3 VREFDQ
H1
M9 F7 N2
P8
A2
A3
A4
VREFDQ
H1 N2
P8
P2
A3
A4
VREFDQ
H1
P2
R8
A4
A5
A6 ZQ
L8
VSS_8 DQL1 A-TMDQL1 P2
R8
R2
A5
A6 ZQ
L8 R8
R2
A5
A6
A7
ZQ
L8
32 29
R2
P1 F2 T8
A7 T8
RXB2-
SERIAL FLASH
A7 A8
T8 A8
R3
L7
A8
A9
A10/AP
VDD_1
VDD_2
B2
D9
VSS_9 DQL2 A-TMDQL2 R3

L7
R7
A9
A10/AP
VDD_1
VDD_2
B2
D9
G7
R3
L7
R7
A9
A10/AP
VDD_1
VDD_2
B2
D9
G7
33
R7
N7
T3
A11
A12/BC
VDD_3
VDD_4
G7
K2
K8
P9 F8
N7
T3
A11
A12/BC
A13
VDD_3
VDD_4
VDD_5
K2
K8
N7
T3
A11
A12/BC
A13
VDD_3
VDD_4
VDD_5
K2
K8
RXB2+ 30
A13 VDD_5
VDD_6
N1
A-TMDQL3 M7
VDD_6
N1
N9 M7
VDD_6
N1
N9
DQL3
NC_5 VDD_7
M7 N9
VSS_10 NC_5 VDD_7

R1 R1
34
8MBit
NC_5 VDD_7
M2
N8
BA0
VDD_8
VDD_9
R1
R9
T1 H3
M2
N8
BA0
BA1
VDD_8
VDD_9
R9 M2
N8
BA0
BA1
VDD_8
VDD_9
R9
31
M3
BA1
BA2 A-TMDQL4 M3
BA2
A1
M3
BA2
A1
35
DQL4
VDDQ_1
J7
CK
VDDQ_1
VDDQ_2
A1
A8
VSS_11 J7
K7
CK
VDDQ_1
VDDQ_2
A8
C1
J7
K7
CK
CK
VDDQ_2
VDDQ_3
A8
C1
RXBCK- 32
K7
K9
CK
CKE
VDDQ_3
VDDQ_4
VDDQ_5
C1
C9
D2
T9 H8 A-TMDQL5
K9
L2
CK
CKE
VDDQ_3
VDDQ_4
VDDQ_5
C9
D2
E9
K9
L2
CKE VDDQ_4
VDDQ_5
C9
D2
E9
36
DQL5
CS VDDQ_6
L2
K1
CS
ODT
VDDQ_6
VDDQ_7
E9
F1
VSS_12 K1
J3
CS
ODT
VDDQ_6
VDDQ_7
F1
H2
K1
J3
ODT
RAS
VDDQ_7
VDDQ_8
F1
H2
RXBCK+ 33
J3
K3
L3
RAS
CAS
WE
VDDQ_8
VDDQ_9
H2
H9
G2 A-TMDQL6
K3
L3
RAS
CAS
WE
VDDQ_8
VDDQ_9
H9
J1
K3
L3
CAS
WE
VDDQ_9
H9
J1 37
T2
RESET
NC_1
NC_2
J1
J9
DQL6 T2
RESET
NC_1
NC_2
J9
L1
T2
RESET
NC_1
NC_2
NC_3
J9
L1 RXB3- 34
F3
NC_3
NC_4
L1
L9
T7
H7 A-TMDQL7 F3
DQSL
NC_3
NC_4
NC_6
L9
T7 F3
DQSL
NC_4
NC_6
L9
T7
38 +3.3V_ST +3.3V_ST +3.3V_ST
G3
DQSL
DQSL
NC_6
DQL7
G3
C7
DQSL
A9
G3
C7
DQSL
DQSU VSS_1
A9
RXB3+ 35
C7
B7
DQSU
DQSU
VSS_1
VSS_2
A9
B3
B1 B7
DQSU
DQSU
VSS_1
VSS_2
B3
E1
B7
DQSU VSS_2
B3
E1 39
IC505
E7
DML
VSS_3
VSS_4
E1
G8
VSSQ_1
E7
D3
DML
VSS_3
VSS_4
G8
J2
E7
D3
DML
VSS_3
VSS_4
G8
J2 RXB4-
D3
E3
DMU VSS_5
VSS_6
J2
J8
M1
B9 D7 E3
DMU
DQL0
VSS_5
VSS_6
VSS_7
J8
M1 E3
DMU
DQL0
VSS_5
VSS_6
VSS_7
J8
M1
40 36 W25Q80BVSSIG
F7
DQL0
DQL1
VSS_7
VSS_8
M9
A-TMDQU0 F7
F2
DQL1 VSS_8
M9
P1
F7
F2
DQL1 VSS_8
M9
P1
RXB4+
DQU0
DQL2
VSSQ_2
F2 P1 DQL2 VSS_9 VSS_9
DQL2 F8 P9 F8 P9
VSS_9
F8
H3
H8
DQL3
DQL4
VSS_10
VSS_11
P9
T1
T9
D1 C3
H3
H8
DQL3
DQL4
DQL5
VSS_10
VSS_11
VSS_12
T1
T9
H3
H8
DQL3
DQL4
DQL5
VSS_10
VSS_11
VSS_12
T1
T9 41 37 R564 R569
G2
DQL5
DQL6
VSS_12
A-TMDQU1 G2
H7
DQL6
G2
H7
DQL6
10K 4.7K
DQU1
DQL7
H7
DQL7
VSSQ_1
B1
VSSQ_3 D7
DQL7
VSSQ_1
B1
B9 D7
DQU0
VSSQ_1
VSSQ_2
B1
B9
42 38 IC505-*1 READY C556
D7
C3
C8
DQU0
DQU1
DQU2
VSSQ_2
VSSQ_3
VSSQ_4
B9
D1
D8
D8 C8 A-TMDQU2
C3
C8
C2
DQU0
DQU1
DQU2
VSSQ_2
VSSQ_3
VSSQ_4
D1
D8
E2
C3
C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D1
D8
E2 MX25L8006EM2I-12G CS VCC 0.1uF
DQU2
DQU3 VSSQ_5
C2
A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E2
E8
VSSQ_4 A7
A2
DQU3
DQU4
VSSQ_5
VSSQ_6
E8
F9
A7
A2
DQU4
DQU5
VSSQ_6
VSSQ_7
E8
F9 43
39 1 8
A2
B8
A3
DQU5
DQU6
DQU7
VSSQ_7
VSSQ_8
VSSQ_9
F9
G1
G9
E2 C2 A-TMDQU3
B8
A3
DQU5
DQU6
DQU7
VSSQ_7
VSSQ_8
VSSQ_9
G1
G9
B8
A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G1
G9
MX
/SPI_CS
CS# VCC
VSSQ_5 DQU3 44
40 1 8
E8 A7 A-TMDQU4 RXA0-
45
VSSQ_6 DQU4 41 SO/SIO1 HOLD# DO[IO1] HOLD[IO3]
F9 A2 A-TMDQU5 46
RXA0+ 2 7
2 7
VSSQ_7 DQU5 FHD 42 SPI_SDO
G1 B8 A-TMDQU6 47 RXA1- WP#
3 6
SCLK
VSSQ_8 DQU6 43 R561

G9 A3 A-TMDQU7 48 RXA1+ GND SI/SIO0 0 %WP[IO2] CLK
4 5
VSSQ_9 DQU7 44 3 6
49 /FLASH_WP SPI_SCK
50 45 RXA2- R575
51 46 RXA2+ GND DI[IO0] 33
4 5 SPI_SDI
52
47
IC500 48 RXACK-
H5TQ1G63DFR-H9C 49 RXACK+
VCC_1.5V_DDR 50 RXA3-
51 RXA3+
M8 N3 52 RXA4-
B-MVREFCA B-TMA0
R500 VREFCA A0 53
P7 B-TMA1 RXA4+
1K A1
1% P3 54
A2 B-TMA2
B-MVREFDQ H1 N2 55
B-TMA3
VREFDQ A3 56
P8 B-TMA4 RXB0-
R501 A4 57
1K P2 B-TMA5 RXB0+
1% R504 A5 58
A0’h
L8 R8 RXB1-
C500 C502 240
ZQ A6
R2
B-TMA6
B-TMA7
59 RXB1+
EEPROM
A7
0.1uF 1000pF 1%
B2
A8
T8
R3
B-TMA8
60
61 RXB2-
1MBit +3.3V
B-TMA9
VDD_1 A9 62
C506 10uF D9 L7 B-TMA10 RXB2+
VDD_2 A10/AP 63
C507 0.1uF G7 R7 B-TMA11
VDD_3 A11 64 IC503-*1
C508 0.1uF K2 N7 B-TMA12 RXBCK- R1EX24256BSAS0A
VDD_4 A12/BC 65
C509 0.1uF K8 T3 B-TMA13 RXBCK+
VDD_5 A13 Renesas_IC503
A0 VCC C552
C510 0.1uF N1 66 RXB3-
1 8
0.1uF
VDD_6 67 A1 WP
C511 0.1uF N9 M7 RXB3+ 2 7
IC503
VDD_7 NC_5 68 AT24C256C-SSHL-T
C512 0.1uF R1 B-TMCK RXB4- A2
3 6
SCL
VDD_8 69
C513 0.1uF R9 M2 B-TMBA0 B-TMCKB RXB4+ VSS SDA
VDD_9 BA0 4 5 A0 VCC
C514 0.1uF N8 70 1 8
B-TMBA1
BA1 71
C515 0.1uF M3 B-TMBA2 R508 R510
BA2 A1 WP
A1 56 56 72 2 7
VDDQ_1 1% 1%
A8 J7 73 R573
VDDQ_2 CK A2 SCL 22
Hynix_1G_1600
C1 K7 74 3 6 I2C_SCL
IC500-*1 VDDQ_3 CK C542 75 P_SDA R574
H5TQ1G63DFR-PBC
C9 K9 B-TMCKE
N3
P7
A0 VREFCA
M8
VDDQ_4 CKE 0.01uF GND SDA 22
P3
N2
P8
A1
A2
A3 VREFDQ
H1
D2 50V 76 DISP_EN 4 5 I2C_SDA
A4
P2
R8
A5
A6 ZQ
L8 VDDQ_5 77
R2
T8
A7
A8 E9 L2
R3
L7
R7
A9
A10/AP
VDD_1
VDD_2
B2
D9
G7 VDDQ_6 CS P_SCL
N7
T3
A11
A12/BC
VDD_3
VDD_4
K2
K8
F1 K1 78 PC_SER_DATA
A13 VDD_5
VDD_6
N1
ODT B-TMODT
M7
A15 VDD_7
VDD_8
N9
R1 VDDQ_7 79
M2
N8
M3
BA0
BA1
VDD_9
R9
H2 J3 B-TMRASB PC_SER_CLK
J7
BA2
VDDQ_1
A1
A8 VDDQ_8 RAS VCC_1.5V_DDR
K7
K9
CK
CK
VDDQ_2
VDDQ_3
C1
C9
H9 K3 80
CKE VDDQ_4
VDDQ_5
D2
CAS B-TMCASB
L2
K1
CS
ODT
VDDQ_6
VDDQ_7
E9
F1 VDDQ_9
J3
K3
L3
RAS
CAS
WE
VDDQ_8
VDDQ_9
H2
H9
L3 B-TMWEB R507
T2
RESET
NC_1
NC_2
J1
J9 WE 10K 81
F3
DQSL
NC_3
NC_4
NC_6
L1
L9
T7
J1
G3
DQSL
NC_1
C7
B7
DQSU
DQSU
VSS_1
VSS_2
VSS_3
A9
B3
E1
J9 T2 B-TMRESETB
E7
D3
DML
DMU
VSS_4
VSS_5
G8
J2 NC_2 RESET
E3
F7
DQL0
DQL1
VSS_6
VSS_7
VSS_8
J8
M1
M9
L1
F2
F8
DQL2
DQL3
VSS_9
VSS_10
P1
P9 NC_3
H3
H8
G2
DQL4
DQL5
DQL6
VSS_11
VSS_12
T1
T9
L9
H7
DQL7
VSSQ_1
B1 NC_4
D7
C3
C8
DQU0
DQU1
VSSQ_2
VSSQ_3
B9
D1
D8
T7 F3 B-TMDQSL
C2
A7
DQU2
DQU3
DQU4
VSSQ_4
VSSQ_5
VSSQ_6
E2
E8 B-TMA14 NC_6 DQSL
A2
B8
A3
DQU5
DQU6
DQU7
VSSQ_7
VSSQ_8
VSSQ_9
F9
G1
G9
G3 B-TMDQSLB
DQSL
Addr:10101--
SS_1G_1600
A9 C7 B-TMDQSU
HDCP EEPROM
VSS_1 DQSU
8KBit
SS_1G_1333
SS_2G_1333
IC500-*2
K4B1G1646G-BCK0
B3 B7 B-TMDQSUB
IC500-*3
K4B1G1646G-BCH9
IC500-*4
K4B2G1646C
VSS_2 DQSU N3 M8
N3
P7
A0
A1
VREFCA
M8
E1 P7
P3
A0
A1
A2
VREFCA
N3
P7
P3
A0
A1
A2
VREFCA
M8
P3
N2
P8
A2
A3 VREFDQ
H1
VSS_3 N2
P8
P2
A3
A4
VREFDQ
H1 N2
P8
A3
A4
VREFDQ
H1
P2
R8
A4
A5
A6 ZQ
L8 G8 E7 B-TMDML
R8
R2
A5
A6
A7
ZQ
L8
P2
R8
R2
A5
A6
A7
ZQ
L8
R2
T8
R3
A7
A8
B2
VSS_4 DML T8
R3
L7
A8
A9 VDD_1
B2
D9
T8
R3
A8
A9 VDD_1
B2
L7
R7
A9
A10/AP
A11
VDD_1
VDD_2
VDD_3
D9
G7 J2 D3 B-TMDMU
R7
N7
A10/AP
A11
A12/BC
VDD_2
VDD_3
VDD_4
G7
K2
L7
R7
N7
A10/AP
A11
A12/BC
VDD_2
VDD_3
VDD_4
D9
G7
K2
N7
T3
A12/BC
A13
VDD_4
VDD_5
K2
K8
N1
VSS_5 DMU T3
M7
A13 VDD_5
VDD_6
K8
N1
N9
T3
A13 VDD_5
VDD_6
K8
N1
M7
NC_5
VDD_6
VDD_7
VDD_8
N9
R1 J8 M2
NC_5
BA0
VDD_7
VDD_8
VDD_9
R1
R9
M7
M2
NC_5
BA0
VDD_7
VDD_8
VDD_9
N9
R1
R9 +3.3V
M2
N8
M3
BA0
BA1
VDD_9
R9
VSS_6 N8
M3
BA1
BA2
A1
N8
M3
BA1
BA2
J7
BA2
CK
VDDQ_1
VDDQ_2
A1
A8 M1 E3 B-TMDQL0
J7
K7
CK
CK
VDDQ_1
VDDQ_2
VDDQ_3
A8
C1
J7
K7
CK
CK
VDDQ_1
VDDQ_2
VDDQ_3
A1
A8
C1
K7
K9
CK
CKE
VDDQ_3
VDDQ_4
C1
C9
D2
VSS_7 DQL0 K9
L2
CKE VDDQ_4
VDDQ_5
C9
D2
E9
K9
CKE VDDQ_4
VDDQ_5
C9
D2
L2
K1
CS
ODT
VDDQ_5
VDDQ_6
VDDQ_7
E9
F1 M9 F7 B-TMDQL1
K1
J3
CS
ODT
RAS
VDDQ_6
VDDQ_7
VDDQ_8
F1
H2
L2
K1
J3
CS
ODT
RAS
VDDQ_6
VDDQ_7
VDDQ_8
E9
F1
H2
J3
K3
L3
RAS
CAS
VDDQ_8
VDDQ_9
H2
H9
VSS_8 DQL1 K3
L3
CAS
WE
VDDQ_9
H9
J1
K3
L3
CAS
WE
VDDQ_9
H9
T2
WE
RESET
NC_1
NC_2
J1
J9 P1 F2 B-TMDQL2
T2
RESET
NC_1
NC_2
NC_3
J9
L1
T2
RESET
NC_1
NC_2
NC_3
J1
J9
L1
F3
NC_3
NC_4
L1
L9
T7
VSS_9 DQL2 F3
G3
DQSL
NC_4
NC_6
L9
T7 F3
DQSL
NC_4
NC_6
L9
T7
G3
DQSL
DQSL
NC_6
P9 F8 B-TMDQL3 C7
DQSL
DQSU VSS_1
A9
G3
C7
DQSL
DQSU VSS_1
A9
C7
B7
DQSU
DQSU
VSS_1
VSS_2
A9
B3
E1
VSS_10 DQL3 B7
E7
DQSU VSS_2
VSS_3
B3
E1
G8
B7
DQSU VSS_2
VSS_3
B3
E1
IC502
E7
D3
DML
DMU
VSS_3
VSS_4
VSS_5
G8
J2 T1 H3 B-TMDQL4
D3
DML
DMU
VSS_4
VSS_5
VSS_6
J2
J8
E7
D3
DML
DMU
VSS_4
VSS_5
VSS_6
G8
J2
J8 CAT24C08WI-GT3-H-RECV(TV)
E3
F7
DQL0
VSS_6
VSS_7
J8
M1
M9
VSS_11 DQL4 E3
F7
F2
DQL0
DQL1
VSS_7
VSS_8
M1
M9
P1
E3
F7
DQL0
DQL1
VSS_7
VSS_8
M1
M9
R563
F2
DQL1
DQL2
VSS_8
VSS_9
P1
T9 H8 B-TMDQL5
F8
DQL2
DQL3
VSS_9
VSS_10
P9
F2
F8
DQL2
DQL3
VSS_9
VSS_10
P1
P9
F8
H3
H8
DQL3
DQL4
DQL5
VSS_10
VSS_11
VSS_12
P9
T1
T9
VSS_12 DQL5
H3
H8
G2
DQL4
DQL5
DQL6
VSS_11
VSS_12
T1
T9
H3
H8
G2
DQL4
DQL5
VSS_11
VSS_12
T1
T9
4.7K NC_1 VCC
G2
H7
DQL6
G2
H7
DQL7
B1
H7
DQL6
DQL7
B1 1 8
DQL7
VSSQ_1
B1
B-TMDQL6 D7
DQU0
VSSQ_1
VSSQ_2
B9 D7
DQU0
VSSQ_1
VSSQ_2
B9
D7
C3
C8
DQU0
DQU1
VSSQ_2
VSSQ_3
B9
D1
D8
DQL6 C3
C8
C2
DQU1
DQU2
VSSQ_3
VSSQ_4
D1
D8
E2
C3
C8
DQU1
DQU2
VSSQ_3
VSSQ_4
D1
D8
R570
C2
A7
DQU2
DQU3
VSSQ_4
VSSQ_5
E2
E8 H7 A7
A2
DQU3
DQU4
VSSQ_5
VSSQ_6
E8
F9
C2
A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E2
E8
NC_2 WP 4.7K
A2
B8
A3
DQU4
DQU5
DQU6
VSSQ_6
VSSQ_7
VSSQ_8
F9
G1
G9
DQL7 B-TMDQL7 B8
A3
DQU5
DQU6
DQU7
VSSQ_7
VSSQ_8
VSSQ_9
G1
G9
A2
B8
A3
DQU5
DQU6
DQU7
VSSQ_7
VSSQ_8
VSSQ_9
F9
G1
G9
2 7
DQU7 VSSQ_9
B1 READY R571
VSSQ_1 A2 3
6 SCL 22
B9 D7 B-TMDQU0 I2C_SCL
VSSQ_2 DQU0 R572
D1 C3 B-TMDQU1 VSS SDA 22
VSSQ_3 DQU1 4 5 I2C_SDA
D8 C8 B-TMDQU2
VSSQ_4 DQU2
+1.5V_DDR_IN VCC_1.5V_DDR E2 C2 B-TMDQU3
VSSQ_5 DQU3
E8 A7 B-TMDQU4
VSSQ_6 DQU4
F9 A2 B-TMDQU5
VSSQ_7 DQU5
L500 G1 B8 B-TMDQU6
500 C544 C545 VSSQ_8 DQU6
Main 10uF 0.1uF G9 A3 B-TMDQU7
VSSQ_9 DQU7
10V 16V
* LCI: LVDS Connection Indicator

Memory.LVDS,IR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 5 6
Power Wafer 1.5V DDR / 1.24V Core
DCON_EN
P_17V +3.3V Multi
P600
C642 0.01uF
SMAW200-H18S1 P_17V
READY
C641 100pF
C613 C620 C621
R648
120K
10uF 10uF 0.1uF R639 R650
1 2 25V 25V 50V C636 3300pF 10K 33K
+5V READY IC603
3 4 L600
R661 R634
DCON_EN
TPS54327DDAR [EP]GND
+5V
120 10K 56K
5 6
CIS21J121
+3.3V_ST
LOW_P
RLIM2
7 8 ERROR_DET C608 C610 C634
10uF 0.1uF 10uF
CMP2
9 10 C606 R609 10V 16V EN VIN 16V
V7V
FB2
SS2
EN2
0.1uF 100 1 8 C632
16V +5V_ST R1 +3.3V
L606
R600 11 12 4.7uF R670
THERMAL
10K R617 10V 4.7
13 14 59K READY
1% VFB VBST
9
RL_ON 15 16 AC_DET 2 7 C609
3300pF
21
20
19
18
17
16
15
5V_ON 17 18 C607 C628 L605 C655 READY
0.1uF C623 4700pF NR5040T2R2N 0.047uF
16V 22pF VREG5 SW 50V 2.2uH 25V
C602
0.1uF
C603
0.1uF
50V 3 6 R2
16V 16V 19 22 14
READY READY READY
R2
C650 C629 C630 V3V BST2 R656
SS GND 10uF 10uF 0.1uF 47K
R619 4 5 16V 16V 16V 1%
17.4K 23 13
1% R622 GND_1 VIN2 C656 C651
C624 C626 0 22uF 22uF
1uF 3300pF 16V 16V R657 C666
10V 50V 24 12 L607 43K 0.022uF
PGOOD LX2_2 NR5040T3R3N 1% 16V
IC605 +1.5V_DDR_IN
GND_2 25 TPS65253RHDR 11 LX2_1 R1
THERMAL
GND_3 26 10 LX1_2 L608
NR5040T3R3N
Vout=0.765*(1+R1/R2)
29
+1.10V_VDDC
GND_4 27 9 LX1_1 R653
C683 C657 4.3K C661
22uF 22uF 1% 0.022uF
16V 16V 16V
28 8 FB_CORE
GND_5 VIN1 C653
10uF
C654
10uF R654 R658
0
51K R1
7
25V 25V READY
3.3Vst 2.5V Multi/2.5_TU 1.25V_TU 3.3V_TU /1.8V_TU [EP]GND
1%
R655
ROSC
FB1
CMP1
SS1
RLIM1
EN1
BST1
100K R2
1%
C652
+3.3V +2.5V +2.5V_TU +3.3V +3.3V_TU 0.047uF
IC604 25V
+5V_ST +3.3V_ST IC601
+3.3V
IC602
+1.25V_TU R2
AZ1117BH-ADJTRE1
TJ3940S-2.5V-3L L613 AP1117EG-13 L604
R614 R613
120-ohm
220 100
+1.8V_TU
5%
2A FNIM 120-ohm
IC600 DVB_T2 2A C611
AP2121N-3.3TRE1 VIN VOUT
R635
3 2 INPUT ADJ/GND R630 3300pF
3300pF 10K
IN OUT 3K 50V
OUTPUT READY
5%
VIN 3 2 VOUT 1 R612 1%
ADJ/GND R666
0.01uF
1 C627 R662
100pF
READY
MULTI R1 4.7
R647
100K
R649
1 C604-*1 C605 GND C671 C682 R620 10uF R631 56K READY
R1
33K
C600 C601 C604 10uF 10uF 0.1uF 1 6.3V 390K
10uF
10V
0.1uF
16V
1uF 1uF 6.3V C612 10V 16V C617 R2 FNIM 1%
GND 10V 6.3V 10uF DVB_T2 DVB_T2 10uF R621
6.3V 6.3V R618 C625 1
R615
FNIM
FNIM 240 10uF

FNIM 6.3V
C645
C649
C648
FNIM C631
1
10uF
6.3V
DCON_EN
Vout=1.25*(1+R2/R1) Vout=1.25*(1+R2/R1)
Vout=0.8*(1+R1/R2)
+3.3V Audio AMP

EMI GND
R608
0
R628
10K
READY R636 R607
0 0
C READY
R627
10K B 19 18
AMP_MUTE Q600
READY MMBT3904(NXP) EAPD/OUT4B OUT3A/FFX3A
R605 EMI_GND1
E READY 20 17 0
R637
0 TWARN/OUT4A OUT3B/FFX3B
C643 R606
0.1uF 21 16 0
50V VDD_DIG_1 CONFIG
C660
22 15 0.1uF
GND_DIG_1 VDD 50V
AC_DET R604 EMI_GND2
22 R638
23 14 0
R625 PWRDN GND_REG
2.2 24 13 L609 C674 C678 R602
10.0uH 0
VDD_PLL OUT1A
R685
R686
0.22uF 1000pF
39
39
R629 50V 50V

25 12
SMAW250-H04R
2K C647 C672
C633
0.1uF 680pF
50V
FILTER_PLL GND1 C662 1uF 25V 0.22uF
16V C637 C669 50V 4
4700pF C675 C679
R626 50V 26 11 C663 0.1uF 50V 330pF
L610 0.22uF 1000pF R601
EMI_GND3
GND_PLL VCC1 50V 10.0uH 0
P601
0 Close-by 50V 50V

27Close-by
AUD_MASTER_CLK C635 3
READY 22pF 22 R640
10
50V XTI OUT1B R603
0
AUD_SCK C639
28 9 L611 2
READY 22pF 22 R641 C670 10.0uH
50V
BICKI OUT2A C664 1uF 25V 330pF C676 C680
AUD_LRCK 50V 0.22uF 1000pF
C640
READY 22pF 22 R642
29 8 C665 0.1uF 50V C673
0.22uF 50V 50V 1 EMI_GND4
R687
LRCKI VCC2
R688
39
39
50V 50V
AUD_LRCH C644
30 7
C677 C681 GND
READY 22pF 22 R643 L612 0.22uF 1000pF
50V SDI GND2 10.0uH
AMP_RESET_N
Close-by 50V 50V
31 6 P_17V C667
22 R644 C668
RESET OUT2B 0.1uF 68uF
50V 35V
C659
R623 2K
R645 32 5 0.1uF
22 INT_LINE VCC_REG 50V
THERMAL
AMP_SDA
R624 2K R646 33 4
22 SDA VSS
37
AMP_SCL
34 3
SCL TEST_MODE
R633 35 2
10K GND_DIG_2 SA
C638 C646 36 Close-by 1
0.1uF 0.1uF
VDD_DIG_2 GND_SUB
50V
50V
[EP]GND
STA368BWG
IC606

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Power,AMP 6
8Pin Wafer to Main Green Eye Sensor
P1 +3.3V_ST +3.3V_ST IR Receiver
12507WS-08L
OPT
R3
4.7K
1
+3.3V_ST
1
IR IC2
OPT ZD3-*1 ZD1-*1
2 R13 R14 KSM-903SMR1CL
2 2K 2.7K 5.48VTO5.76V 5.48VTO5.76V
IC1
VDD
R1
3 CM3231A3OG VOUT 47
3 KEY1 1
IR
4
4 SCLK GND ZD3 ZD1
4 KEY2 3 EYE_SCL 2 5.6B 5.6B
R2
5 SDAT VCC 330
5 LED_R 2 3
EYE_SDA
6
OPT +3.3V_ST
1
6 EYE_SCL C1 C2 ZD2 C3 C4
ZD6 ZD7 5.6B
GND
0.1uF 10uF 10uF 0.1uF
7 16V 6.3V 5.6B 5.6B 6.3V 16V
7 EYE_SDA
8
8 +3.3V_ST
ZD6-*1 ZD7-*1
9 5.48VTO5.76V 5.48VTO5.76V
ZD2-*1
5.48VTO5.76V
9 ZD4 ZD5
5.6B 5.6B
ZD4-*1 ZD5-*1
5.48VTO5.76V 5.48VTO5.76V
JTP1283 JTP1283 JTP1283 JTP1283 JTP1283 JTP1283 JTP1283 JTP1283

1
1
Tact Switch RED LED
3
3
2
2
SW1-*1 SW2-*1 SW3-*1 SW4-*1 SW5-*1 SW6-*1 SW7-*1 SW8-*1
+3.3V_ST
KEY2
R15
10K
KEY1
R5 R6 R7 R8 R9 R10 R11 R12

27K 3.9K 10K 27K 620 3.9K 10K 620
JTP1289 JTP1289 JTP1289 JTP1289 JTP1289 JTP1289 JTP1289 JTP1289

R4
C LTST-C191KRKT
4.7K B Q1 LD1
LED_R MMBT3904(NXP) EAV60793101
OPT OPT SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
E
C5 C6
0.1uF ZD8 0.1uF ZD9
16V 5.6B 16V 5.6B OPT
C7
10uF
6.3V
ZD8-*1 ZD9-*1
5.48VTO5.76V 5.48VTO5.76V Power Input Home OK Vol- Vol+ CH- CH+
2.4V 0.93V 1.65V 2.4V 0.2V 0.93V 1.65V 0.2V

(KEY1) (KEY1) (KEY2)(KEY2) (KEY2) (KEY2) (KEY1) (KEY1)

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS EAX64342101 12/04/2011
Tact/IR/Eye 1 1
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
GP2R, LM1 Training Manual
Table of contents
1. PCB layout.
2. GP2R vs LM1
3. GP2R. (Block, Power, I2C)
4. LM1. (Block, Power, I2C)
5. LM1 SOC Power sequence.
6. Memory test.
7. Pen touch overview.
1. PCB Layout.
GP2R (206 x 183) LM1 (206 x 141.5)
※ LM1 use internal EDID&HDCP. (LM1 is Removing the EEPROM for EDID&HDCP)
LM1 is optimizing Power block. (LM1 is reducing DC/DC, LDO, power application)
2. GP2R vs GP4 LM1.
Difference GP2R 50PZ550 LM1 50PA6500 Changes
PDP Module R3(FHD) R4(FHD) New module. 50R4 Initial model.
Tool PZ Tool PA Tool 12’ years New tool.
PCB 206x183 206x141.5 change PCB Size. (smaller than GP2R.)
Main IC S7R S7LR Internal sub-Micom .(PM block)

VSC
Jack Layout Slim Depth Slim Depth Same.
Sub Assy PZ Tool PA Tool GP2R 15pin, LM1 8pin
PSU 50R3 XP5 B’d 50R4 UP1 B’d Reduce power on time.
SW GP2R LM1 PDP only code.
JIG GP2R LM1 Support DFT JIG.
- . . Develop new WAFER and CABLE. (12 years)
Power Wafer 18P 18P Stand by 0.3W ↓
Stand by 3.5V O O Stand by 3.5V .
12V_secondary X X Not use 12V.
IR Wafer 15P 8P LM1 not support 3D.
USB O O SIDE USB.
Memory DDR3 DDR3 DDR3 1Gbit . 2ea
3. GP2R Power measure Summary
Power Line Voltage Spec [V] Voltage [V] Ripple spec [Vpp] Ripple [mV] Current [A] Remark
+5V_ST 4.845~5.355 5.01 86 0.009
+5V_ST_EN 4.845~5.355 5.00 17 0.710
+3.3V_AVDD 3.14~3.6 3.31 0.5 15 0.285
+2.5V_AVDD 2.38~2.62 2.53 20 0.200
+1.5V_DDR_IN 1.425~1.575 1.57 1.5V +/-5% 20 0.310
+1.26V_VDDC 1.2~1.32 1.27 30 0.770
+3.3V_ST 3.234~3.366 3.30 0.5 19 0.024
+17V 16.15~17.85 17.03 1.09A 1.420
+5V_TU 4.75~5.25 4.99 None 20 0.170
+5V 4.845~5.355 5.03 57 2.600
+3.3V_TU 3.15~3.46 3.26 None 26 0.320
+1.2V_TU 1.20~1.32 1.27 None 21 0.300
3-1. GP2R Power Block Diagram
+5V_ST IC205
L603
5Vst MAX 3A C619 C627 C219
AT24C02BN
0.1u 0.1u
RGB EDID
100u
16V 16V 16V
+5V_ST_EN IC600 +3.3V_AVDD
Q600 L602
AZ1085S 2A/3ea S7_3.3V_AVDD
C654 C655 RTR030P02 C656 C657 C600 C607 C608 2A C615
0.01u 100u 0.1u 0.1u 3.3V 22u 0.1u 0.1u
22u 10u 0.1u
16V 25V 16V 16V 16V 6.3V 16V 16V 2ea 13ea
NAND Flash/HDCP/EEPROM
+2.5V_AVDD
IC604
2A 2A/2ea 2.5V_AVDD
TJ3964 C616 C623
22u 0.1u 10u 0.1u
6.3V 16V 1ea 4ea
+1.5V_DDR_IN
IC602
DDR
C609 C611 TPA54319 C637 C647 C650 10u 0.1u
10u 0.1u 10u 10u 0.1u 2ea 32ea
16V 16V 10V 10V 16V
2A/2ea S7 AVDD_DDR
10u 0.1u
4ea 10ea
IC603 +1.26V_VDDC
2A/2ea DVDD
C610 C612 TPA54319 C651 C652 C653 10u 0.1u
10u 0.1u 10u 10u 0.1u 2ea 2ea
16V 16V 10V 10V 16V
VDDC
10u 0.1u
1ea 8ea
IC203
MAX3232CDR
IC601 +3.3V_ST
AP2121N S7_MPLL
C601 C605 C606
0.1u
300mA 100u 0.1u
16V 16V 16V IC503(S-FLASH)
C552 MX25L8005M2I-15G
0.1u
16V
SUB ASSY
+17V +5V_TU
IC605 L610
17V C634 C635 C636 TPA54319 C641 C642 2A C304 C307
5V_TU
4.7u 4.7u 0.01u 10u 10u 22u 0.1u
50V 50V 50V 16V 16V 10V 16V
IC303 Audio AMP

C341 C344 C340 STA338BWG13TR
68u 68u 0.1u
35V 35V 50V
3-2. GP2R Power Block Diagram
+5V
L604 L101
+5V 3A C621 C624 2A C103 C104 +5V_CI_ON
C628 C631
100u 100u 0.1u 22u 22u 0.1u
L605 16V 16V 16V 16V 10V 16V
3A IC205
AT24C02 EDID
IC206
USB
AP2191 C223 C222
100u 0.1u
16V 16V
SPDIF
C235
0.1u
16V
L708 IC704 L709 L710
1.0V_LTX
2A C725 C728 TPS54319 C746 C747 C748 2A 2A
10u 0.1u 10u 10u 0.1u
16V 16V 10V 10V 16V 1.0V
0.1u 13ea
16V
IC706 L708 +3.3V_3D
IC702 MX25L4005
C750 AZ1085S C753 C754 2A C735
0.1u 22u 0.1u 0.1u
16V 16V 16V 16V
IC707 R834
1.8V
C751 AZ1117ST C752 C755 0Ω1/10W 0.1u 33ea
0.1u 22u 0.1u 16V
16V L705 16V 16V
3.3V_LTX
2A C789 C805 0.1u 7ea
10u 100p 16V
L706 16V 50V
C753 C754 0.1u 3.3V_VDD
2A 7ea
10u 100p 16V
L707 16V 50V
3.3V_PLL
2A 0.1u 3ea
16V
IC606 L601 L100

+3.3V_CI
C658 AZ1085S C659 C660 2A C661 C126 2A C128
0.1u 22u 0.1u 0.1u 0.1u 0.1u
16V 6.3V 16V 16V 16V 16V
C120 IC101 74LCX244
0.1u
16V
C332 IC303 Audio AMP

0.1u
50V
+3.3V_TU
L300
C302 +3.3V_TU
2A
0.1u
16V
+1.2V_TU
C309 IC301
C313 C325 C322 C300 +1.2V_TU
22u AZ1117H
10V 0.1u 22u 0.1u 0.1u
16V 10V 16V 16V
3-3. LDO/DC-DC Start up
■ IC600 (+3.3V_AVDD/AZ1085S) ■ IC602 (+1.5V_DDR_IN/TPS54319)
Vin
Vout Ve
n
Vin
Vo
Io
■ IC604(+2.5V_AVDD/TJ3964S) ■ IC603 (+1.26V_VDDC/TPS54319)
Vin
Vout
Ve
Vin n
Vo
Io
3-4. LDO/DC-DC Start up
■ IC606 (+3.3V/AZ1085S)
Vout
Vin
■ IC605 (+5V_TU/TPS54231)
Vin
Ve
n
Vo
Io
3-5. GP2R I2C MAP
DDC_SCL/SDA_1~3
DDCR_CK/GPIO72 (N22)<I2C-SCL> <EEPROM-SCL>+3.3
+5V_HD DDCR_DA/GPIO71
(M22)<I2C-SDA> 2.2K (R480,R482) <EEPROM-SDA>
1 (R208,209)
V
MI 2 (R233,234)
10K 3 (R256,257) EEPROM
EEPROM HDCP
HDCP
0xA0
0xA0 EEPROM
EEPROM
Ch2
Ch2 0xA8
0xA8
Ch2
Ch2
HDMI1,2,3
HDMI1,2,3
0xA0
0xA0 Ch10,12,11
Ch10,12,11
TGPIO2/I2C_CLK (R3) <TU_SCL> <SCL1>+3.3V_T

TGPIO3/I2C_SDA (T3) <TU_SDA> 4.7K (R319,R326) <SDA1>
TUNER
TUNER
TDTJ-S001D
TDTJ-S001D 0x10/C2
0x10/C2
Ch6
Ch6
SATURN7R
SATURN7R
TGPIO0/UPGAIN (U1) <AMP_SCL> +3.3
TGPIO1/DNGAIN
(U2) 2K (R360,R359) <AMP_SDA>
SUB_SCL (F15)I2S_IN_WS/GPIO174 AMP
AMP STA338BWG13TR
STA338BWG13TR V
+3.3V_S 0x38
SUB_SDA (F14)I2S_IN_BCK/GPIO175 0x38
T Ch5
Ch5
4.7K (R635,R633)
TOUCH
TOUCH G_EYE
G_EYE
0x52
0x52 0x20
0x20
I2S_IN_SD/GPIO176 (F13)<P_SCL> <MODULE_SCL/3DF_SCL>
+3.3
Ch7
Ch7 Ch7
Ch7 SPDIF_IN/GPIO177
(G14)<P_SDA> 3.3K (R1412,R1411)
4.7K (R780,R781) <MODULE_SDA/3DF_SDA>
V_A
LG8300
LG8300 MODULE
MODULE
VDD
0x74
0x74 0x1C
0x1C
Ch4
Ch4 Ch4
Ch4
(B5) <RGB_DDC_SCL> +5.0

<DDC_SCL/UART_RX>
DDCA_CK/UART0_RX (A5) <RGB_DDC_SDA> 10K (R237,R247) <DDC_SDA/UART_TX>
V_ST
DDCA_DA/UART0_TX EEPROM
EEPROM ISP
ISP
RGB
RGB 0xA0
0xA0
Ch8
Ch8
4. LM1 Power Block optimization.
1. GP2R vs LM1 Power Block.
Amp
17V Amp 1.8V Tuner
17V LDO (1A)
5V Tuner
TPS54231 2A 3.3V Multi 1.25V _TU
AP2191 TPS54327(3A) LDO (1A)
USB
2.5V
3.3V Multi 1.25V Tuner LDO (1A)
LDO (3A) LDO AP2191
5.1V
3.3V 3D 1.8V 3D DDR USB
5.1V LDO (3A) LDO
1V 3D core
AOZ1073 3A 3.3V AVDD 2.5V
LDO (3A) LDO
1.24V core
1.5V DDR 1.5V DDR
AOZ1073 3A TPS65253(3A)
FET SW 1.26V Core
AOZ1073 3A
3.3V Standby
St 5V
LDO(AP2121) 3.5V 3.3V ST
St. AP2121
DC/DC : 4 DC/DC : 2
LDO : 7 GP2R Power Block LDO : 4 LM1 Power Block
4-1. P_17V
+3.3V +3.3V_CI
Spec) 850mV↓ Spec) 165mV ↓ Spec) 165mV ↓
16mVrms L605 8.66mVrms L101 4.7mVrms
283mVpp 17V to 3.3V 2.2uH 37.5mVpp 120 Ohm 46.6mVpp Buffer for
TPS54327 CI_ADDR
C620 C621 (3A, $0.14) 3.5A C629/50 C630 2A C137 [0:7]
10uF 0.1uF 4.9x4.9 10uF 0.1uF 1608 0.1uF
25V 50V 16V 16V 16V
→6.3V
3216 2012 1005 1005
3216
→1608
0.00586↓
OP-Amp change
for SC
1 C667 C668
Audio
AMP
+3.3V_TU
Spec) 165mV ↓ Spec) 90mV↓
4.6mVrms
L604
7 0.1uF 68uF
13.5mVrms
3.3V to 1.8V 41.6mVpp
120 Ohm 158mVpp AP1117E18G
50V 35V
V 2A C627 (850mW) C631 C618
1608 8PI/6.3H
1608 10uF 10uF 0.1uF
6.3V 6.3V 16V
17V to 12V
TPS54231D Spec) 165mV↓ 1608 1608 1005 Tuner
C693 C694 (2A) 23.4mVrms
10uF 0.01uF 166.6mVpp
25V 50V C614 C615
3225 1005 0.1uF 10uF
16V 16V
C643 →6.3V
Spec) 165mV↓ 1005
0.1uF 8.5mVrms 3216
Audio →1608
50V 186.6mVpp
C711 C712
LNB AMP change
1608
10uF 0.1uF
16V 50V C638
C646
3216 1608
0.1uF
50V
1608
4-2. P_17V
* Y17
+3.3V +2.5V
Spec) 165mV↓
x3 7.8mVrms L613
3.3V to 2.5V 120 Ohm 47.5mVpp 120 Ohm
TJ3940S-2.5V LM1 Tuner
C605 (714mW) C612 2A C1417 x6 2A C682 C671
10uF 10uF 1608 10uF 0.1uF 1608 0.1uF 10uF
6.3V 6.3V 10V 16V 16V 10V
→6.3V →6.3V
1608 1608 1005 1005
2012 2012
→1608 →1608
change change
DVB_T2
Nand
1 * W18/9
Spec) 165mV↓
x2 C554 Flash
0.1uF 10uF
7 L408/9
120 Ohm
9.7mVrms
67.5mVpp 16V 10V
+1.25V_TU
→6.3V
V 2A
1608
x5
0.1uF
X4
10uF
1005
2012
→1608
3.3V to 1.25V
AP1117EG-13
(???mW) C625
16V 10V change
→6.3V 10uF
1005 LM1
2012 6.3V
→1608 1608
change
HDCP
x3 C427
0.1uF 10uF
16V 10V * L7
Tuner
→6.3V Spec) 165mV↓
NVR
1005 C552
2012 8.5mVrms
→1608 0.1uF C684 C685
45mVpp
0.00636↓ 16V 0.1uF 10uF
change 1005 16V 6.3V
1005 1608
NOT_HNIM
4-3. P_5V
+5V
Spec) 250mV↓
L600 7mVrms
120 Ohm 70mVpp
USB OCD
5A C608 C610
2012 10uF 0.1uF
10V 16V
→16V
1005
2012 SPDIF
→3216 C219
0.0005↓ 0.1uF
change 16V
5 1005
+5V_CI_ON Spec) 250mV↓
V L100 31mVrms
135.4mVpp
MOFET 120 Ohm
PCMCI
Switch 2A C104 C100 C101
1608 0.1uF 22uF 0.1uF
16V 10V 16V
→16V
1005 1005
3216
→3225
0.017↓
change
4-4. P_5V
* M14
+5V +1.24V_VDDC
Spec) 55mV↓
L606 L405 9.4mVrms
120 Ohm ???mVrms 120 Ohm 48.3mVpp
5A C653/4 C683/57 2A x2 C1413 ???mVrms
2012 10uF 22uF 1608 0.1uF 10uF
25V 16V 16V 10V
→6.3V
3225 3225 1005 * R15
2012 LM1
→1608
change
5V to 1.1V
TPS65253RH x3 x3 Spec) 55mV↓
D 0.1uF 10uF 17.7mVrms
(adjustable) 70mVpp
$0.25 16V 10V
→6.3V
1005
2012
→1608
change
5 +1.5V_DDR_IN
* M17
Spec) 55mV↓
V L412
120 Ohm
15.9mVrms
90mVpp LM1
C651/56 C467 2A x4 x4 C468 MIU0/1
22uF 1000pF 1608 10uF 0.1uF 1uF
16V 50V 10V 16V 10V
1005 →6.3V
3225 1005 1005
2012
→1608
change
* IC501 / G7
VCC_1.5V_DDR
Spec) 55mV↓
L500 19.69mVrms
500 Ohm 120.8mVpp
3A C544 C545 x2 x2
DDR1/2
??? 10uF 0.1uF 1000pF 0.1uF
10V 16V 50V 16V
→6.3V
1005 1005 1005
2012
→1608
change
4-5. STBY
Spec) 250mV↓
23mVrms
150mVpp
+3.3V_ST
5V to 3.3V
AP2121N-3.3 RS232C
C600 C601 (0.3A) C604 C228
10uF 0.1uF 1uF 0.1uF
10V 16V 6.3V 16V
→16V
1005 1005 1005
2012
→3216
0.0005↓
change L406
120 Ohm
2A C469 LM1
S 1608 0.1uF
16V
T 1005
B
Y C556
Serial Flash
0.1uF
16V
1005
SUB Ass’y
C547
0.1uF
16V
1005
4-6. GP4 LM1 I2C MAP EAX64337201_0
+3.3V_TU
R3082.2K R309 2.2K
I2C_SCKM1/GPIO75 AE6 TU_SCL
I2C_SDAM1/GPIO76 AD6 TU_SDA TU300
TDSS-G201D
IC400 +3.3V
R624 2K R623 2K
GPIO49 AB5 AMP_SCL
GPIO50 AB3 AMP_SDA IC300
STA368BWG
+3.3V_AVDD
R468 3.3K R466 3.3K
I2S_IN_WS/GPIO149 D9 P_SCL SCL_3.3V_MOD P500
SPDIF_IN/GPIO152 D7 P_SDA SDA_3.3V_MOD LVDS
+3.3V_ST
R539 4.7K R538 4.7K
I2S_IN_SD/GPIO151 D8 SUB_SCL
P501
I2S_IN_BCK/GPIO150 C8 SUB_SDA
KEY/IR PIN8
+3.3V_AVDD
R469 2.2K R468 2.2K
I2C_SCKM2/DDCR_CK/GPIO72 P23 I2C_SCL
IC503 EEPROM
I2C_SDAM2/DDCR_DA/GPIO71 P24 I2C_SDA
IC502 HDCP (OTP)
5. GP4 LM1 SOC Power Sequence Procedure
▶Hot Point
288ms / [Spec] before all pwr input raise

SOC_RESET
+3.3V_AVDD
Multi_PWR +1.10V_VDDC
+1.5V_DDR_IN
0ms
SOC_RESET
Threshold
+3.3V_AVDD
+1.10V_VDDC
+1.5V_DDR_IN
◈ SOC_RESET timing and Power sequence are ok.
5. GP4 LM1 SOC Power Sequence Procedure
◈ Solution
█ Value of Capacitor and resister.

① Cap Æ 22uF.
0CK226DC67A 22uF 6.3V $0.0117
② Resister Æ 100㏀.
+3.3V_AVDD
1
Threshold
SOC_RESET
2
6. Memory margin test. (DDR)
STEP1. Setting like below. (Red box) STEP2. Call “direct MIU Auto BIST” function from Menu.
6. Memory margin test. (DDR)
STEP3. Setting like below and push “Start DQS”. (Red box) STEP4. below picture is test result. Red box is timing margin.
※Normal operating board has timing margin 7~9. If timing margin under 7 ,it’s some problem DDR or Main MIU.
7. Pen touch overview. (Installation_Pentouch Program.)
7. Pen touch overview. (Installation_Pentouch Program.)
7-1. Pen touch overview. (Check the installation status.)
1 Currently installed programs 2 Check USB Dongle Driver in Device Manager

Check the LG Pentouch Multi-touch Driver or Pentouch TV -LG Pentouch Multi-touch Driver(MultiTouch)
-LG Pentouch Multi-touch Driver(BUS)
-LG Pentouch Multi-touch Driver(Dongle)
the Dongle Driver should be displayed when connected USB Dongle
7-2. Pen touch overview. (Pairing between Touch Pen and Dongle)
7-3. Pen touch overview. (Pairing between Touch Pen and Dongle)
7-4. Pen touch overview. (Using the Pentouch Function)
■ Image shown may differ from your monitor. You need the following items to use the Pentouch functions:
1 Enter the Pentouch mode on your monitor. - Press TOUCH button on the remote control or MENU to access the main menus. Then choose Pentouch function.
2 Select the correct computer input connection to enter the Pentouch mode.
3 Use the touch pen or the mouse to start the Pentouch program. Pressing the /Home button on the touch pen works in the same way as right-clicking the mouse.
■ Viewing the Screen Settings

I
mage shown may differ from your monitor. If you press the OK button on the remote control, the screen shown below appears to indicate that the screen
settings have been updated successfully.
① The text "Pentouch" should be displayed to indicate that the Pentouch mode is activated. If not, restart the Pentouch mode.
② "1365x768 " should be displayed to indicate that the resolution has been set successfully. If not, set the monitor resolution again.(See p.38)
7-5. Pen touch overview. (PDP Pen Touch Concept)
Principle 2. The position data processed Pentouch TV

Application looks like PC mouse.
Step 1. USB Dongle receive the position data.
Principle 1. The Pen using PDP Cell’s light energy Step 2. USB Dongle Driver parsing the positon
Step 1. The pen detect the PDP Cell’s light Step 3. Pentouch TV application drawing and click function.
Step 2. The pen convert detected light to voltage Step 4. The result was displayed PDP TV through HDMI or
Step 3. The pen calculate X,Y position RGB cable.
Step 4. The pen transfer the X,Y data through RF
RF Wireless communication
(2.4GHz)
Pen
The photo sensor in the
pen detect the light
USB
Dongle
It can use Multi-Touch function by support 2 pens.
Plasma
Display Pentouch TV Application
- It was developed by LG.
- It can be using internet for web surfing , Flash Game etc.
The HDMI or RGB signal is PC’s output that configuration set by clone mode.

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Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 50PA4500 50PA4500-SF

P/NO : MFL67341904 (1201-REV00) Printed in Korea

SAFETY PRECAUTIONS ......................................................................... 3

EXPLODED VIEW .................................................................................. 13

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

always perform an AC leakage current check on the exposed

2. Requirement for Test

(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

4. Model General Specification

2. Specification ■ Adjustment sequence

■ A fter Receive 100% Full white pattern (06CH) then 5. R

< See ADC Adjustment RS232C Protocol_Ver1.0 >

5.1. Auto Adjust Component 480i/1080p RGB

* caution : Set Volume 0 after adjustment

5.2. Use Internal ADC(S7R)

* E DID (The Extended Display Identification Data)/DDC

- South Centural America _2D_HD HDMI

■ Connection Diagram (Auto Adjustment)

● Using HDMI input

■ White Balance Adjustment

■ White Balance Adjustment (Manual adjustment)

6.2. Operate GND and ESD auto-test.

Color Test Color Coordination 6.3. Check Items.

5.3. Test of RS-232C control.

5.4. Selection of Country option.

7.2. White balance. Value.

7.3. Temperature Threshold

8. USB DOWNLOAD(*.epk file download)

■ After download is finished, remove the USB stick.

BUF2_FE_TS_DATA[0] PCM_A[0] 2 19 BUF1_FE_TS_CLK BUF2_FE_TS_CLK

BUF2_FE_TS_DATA[2] PCM_A[1] PCM_A[7]

0 R128 0 PCM_A[2] PCM_A[6]

READY CI_ADDR[5] CI_ADDR[2]

BUF2_FE_TS_DATA[4] PCM_A[3] PCM_A[5]

BUF2_FE_TS_DATA[5] CI_ADDR[4] CI_ADDR[3]

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

HDMI_1 SIDE_HDMI_1 SIDE_HDMI_2 JK204

HPD2 HPD3 VINPUT 16V 100 3 VIN

19 R201 Q200 R217 1.8K SIDE_HDMI_1 MMBT3904(NXP) 10K 10K

10 CK+_HDMI1 CK+_HDMI2 CK+_HDMI3 BSS83 40V

D1- 6 D1-_HDMI2 6 D1-_HDMI3 0.1uF 10uF R258

USB DOWN STREAM

COMP2_Y+ R259 R276 100 READY

5C 10 USA 11 6 ET_NET ET_NET ET_NET ET_NET ET_NET

GREEN 75 4 R_SPRING R218 R222

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

TDSS-G101D DVB-T/C HNIM X FE_TS_DATA[0-7] AR302

TDSS-H101F ATSC HNIM X FE_TS_VAL_ERR BUF1_FE_TS_VAL_ERR

TDSH-T101F DVB-T_SCA HNIM RF_SW

Close to Tuner Pin

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

NC_4 RXACK- NC_9

A-TMA14 DQSL A-TMDQSL RXACK+ CLE NC_20

VSS_9 DQL2 A-TMDQL2 R3

VSS_10 NC_5 VDD_7

VSSQ_8 DQU6 43 R561

* LCI: LVDS Connection Indicator

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

■ A fter Receive 100% Full white pattern (06CH) then 5. R

5.1. Auto Adjust Component 480i/1080p RGB

* E DID (The Extended Display Identification Data)/DDC