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5 4 3 2 1

Tiguan1.0_AMD Comal DIS/UMA (15.6") Ultra/Slim 01


D D

VRAM DDR3 x 4 (900 MHz) PCB 6L STACK UP


AMD APU AIT Mars PRO
PCI-E Gen3
128 x 16 x 4, 64 bit
x 8 Lane 256 x 16 x 4, 64 bit LAYER 1 : TOP
Power : 18 (Watt)
Max 1GBs/2GBs PAGE 21-22 LAYER 2 : SGND
DDR3 SODIMM1 Processor : TRINITY Daul / Package : S3
DDR3 800 ~ 1600 MT/s LAYER 3 : IN1(High)
Maxima 4GBs Quad Core Size : 23 x 23 (mm) 27MHz LAYER 4 : IN2(Low)
PAGE 12 Power : 25 (Watt) PAGE 16
LAYER 5 : SVCC
Package : FP2 827-PIN BGA PAGE 14-20
DDR3 SO-DIMM2 LAYER 6 : BOT
DDR3 800 ~ 1600 MT/s Size : 27 x 31 (mm)
Maxima 4GBs DP Port2
HDMI Conn
PAGE 13
PAGE 30 Power Source
RTD2132S BQ24728
DP Port0 LCD Conn (15.6") System Charge Power (+BATCHG)
PAGE 02-05 DP to LVDS
Translator PAGE 11 PAGE 30

BCLK133M
C C
Green CLK
32.768KHz
UMI x 4 G5934RZ1U
PAGE 27
System Discharge Power
(+1.5V/+3V/+5V)
(+3VSUSV/+3VLANVCC/+1.1V)
SATA - 1st HDD AMD FCH USB3.0 Interface USB 2.0/3.0
SATA0 6GB/s USB2.0 x 2
Package : 9.5 (mm) PORT0,1 Combo x 2
Hudson M3 Ricktek RT8223PZ
Power : PAGE 28 PAGE 26
Power : 4.7 Watt System Power (+3VPCU/+5VPCU/
Package : 656pin FCBGA +3VS5/+5VS5)
mSATA SATA1 6GB/s
Size : 24.5 x 24.5 (mm) USB2.0 Interface
Package : 12.7 (mm)
Power : PAGE 28 SPI Interface
PAGE 06-10 ISL6277/RT8228AZ/AP3407A/ISL6208BCRZ
System BIOS Processor Power (+VCC_CORE/
+1.2V/+2.5V/+VDDNB_CORE)
SPI ROM Camera External USB BT USB2.0 x 2
B PAGE 08 B
Azalia

8 0 2 10, 11
PAGE 30 PAGE 23 PAGE 27 PAGE 26
Richtek RT8207L
LPC Interface PCIE Gen 1 x 1 Lane System Memory Power (+1.5VSUS/
+0.75V_DDR_VTT)

80 Port (Debug)
iTE IT8518E/HX IDT 92HD99B Realtek RTL8105E Realtek RTS5229 Intel Rambo Peak Richtek RT8228AZ
PAGE 25
Embedded Controller Audio Codec LAN Controller Card Reader Halt Mini Card PCH Power (+1.1VS5)
EC SPI ROM CMC WLAN / BT Combo
PAGE 29
Power : Power : Power : Power : Power :
Keyboard Package : LQPF128 Package : QFN-40 Package : OFN48 Package : LQPF24 Package :
PAGE 26 RT8152E/G5193/G5193R41U/NB650
Size : 14 x 14 (mm) Size : 5 x 5 (mm) Size : 6 x 6 (mm) Size : 4 x 4 (mm) Size :
Touch Pad DGPU Power (+VGA_CORE/+1.0V_VGA/+3V_VGA/
PAGE 28 PAGE 29 PAGE 23 PAGE 24 PAGE 25 PAGE 27 +1.5V_VGA/+1.8V_VGA/+VDDCI)
A A

SLG3NB242 FAN Controller Daughterl/B CONN 25MHz


GreenCLK Combo Jack
NS681684 RJ45 Conn PROJECT : U56
PAGE 27 PAGE 28 PAGE 23
TRANSFORMER Quanta Computer Inc.
PAGE 24 PAGE 24
Size Document Number Rev
25MHz A3 1A
Block Diagram
NB5 Date: Thursday, August 09, 2012 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1

02
U25A
PEG_RXP0 AP1 AN1 PEG_TXP0_C C672 0.1U/10V_4 PEG_TXP0
[14] PEG_RXP0 P_GFX_RXP[0] P_GFX_TXP[0] PEG_TXP0 [14]
[14] PEG_RXN0 PEG_RXN0 AP2 AN2 PEG_TXN0_C C673 0.1U/10V_4 PEG_TXN0 PEG_TXN0 [14]
PEG_RXP1 P_GFX_RXN[0] P_GFX_TXN[0] PEG_TXP1_C C644 0.1U/10V_4 PEG_TXP1
[14] PEG_RXP1 AM1 P_GFX_RXP[1] P_GFX_TXP[1] AM4 PEG_TXP1 [14]
PEG_RXN1 AM2 AM3 PEG_TXN1_C C645 0.1U/10V_4 PEG_TXN1
[14] PEG_RXN1 P_GFX_RXN[1] P_GFX_TXN[1] PEG_TXN1 [14]
[14] PEG_RXP2 PEG_RXP2 AK3 AK2 PEG_TXP2_C C674 0.1U/10V_4 PEG_TXP2 PEG_TXP2 [14]
P_GFX_RXP[2] P_GFX_TXP[2]

PEG X 8
[14] PEG_RXN2 PEG_RXN2 AK4 AK1 PEG_TXN2_C C675 0.1U/10V_4 PEG_TXN2 PEG_TXN2 [14]
PEG_RXP3 P_GFX_RXN[2] P_GFX_TXN[2] PEG_TXP3_C C646 0.1U/10V_4 PEG_TXP3
[14] PEG_RXP3 AJ1 P_GFX_RXP[3] P_GFX_TXP[3] AH1 PEG_TXP3 [14]
[14] PEG_RXN3 PEG_RXN3 AJ2 AH2 PEG_TXN3_C C647 0.1U/10V_4 PEG_TXN3 PEG_TXN3 [14]
PEG_RXP4 P_GFX_RXN[3] P_GFX_TXN[3] PEG_TXP4_C C676 0.1U/10V_4 PEG_TXP4
[14] PEG_RXP4 AH4 P_GFX_RXP[4] P_GFX_TXP[4] AF3 PEG_TXP4 [14]
[14] PEG_RXN4 PEG_RXN4 AH3 AF4 PEG_TXN4_C C677 0.1U/10V_4 PEG_TXN4 PEG_TXN4 [14]
PEG_RXP5 P_GFX_RXN[4] P_GFX_TXN[4] PEG_TXP5_C C648 0.1U/10V_4 PEG_TXP5
[14] PEG_RXP5 AF2 P_GFX_RXP[5] P_GFX_TXP[5] AE1 PEG_TXP5 [14]
PEG_RXN5 AF1 AE2 PEG_TXN5_C C649 0.1U/10V_4 PEG_TXN5
D
[14] PEG_RXN5 P_GFX_RXN[5] P_GFX_TXN[5] PEG_TXN5 [14] D
[14] PEG_RXP6 PEG_RXP6 AD1 AD4 PEG_TXP6_C C678 0.1U/10V_4 PEG_TXP6 PEG_TXP6 [14]
PEG_RXN6 P_GFX_RXP[6] P_GFX_TXP[6] PEG_TXN6_C C679 0.1U/10V_4 PEG_TXN6
[14] PEG_RXN6 AD2 P_GFX_RXN[6] P_GFX_TXN[6] AD3 PEG_TXN6 [14]
PEG_RXP7 PEG_TXP7_C C650 0.1U/10V_4 PEG_TXP7

GRAPHICS
[14] PEG_RXP7 AB3 P_GFX_RXP[7] P_GFX_TXP[7] AB2 PEG_TXP7 [14]
PEG_RXN7 AB4 AB1 PEG_TXN7_C C651 0.1U/10V_4 PEG_TXN7
[14] PEG_RXN7 P_GFX_RXN[7] P_GFX_TXN[7] PEG_TXN7 [14]
AA1 P_GFX_RXP[8] P_GFX_TXP[8] Y1
AA2 P_GFX_RXN[8] P_GFX_TXN[8] Y2
Y4 P_GFX_RXP[9] P_GFX_TXP[9] V3
Y3 P_GFX_RXN[9] P_GFX_TXN[9] V4
V2 P_GFX_RXP[10] P_GFX_TXP[10] U1 UMA can remove
V1 P_GFX_RXN[10] P_GFX_TXN[10] U2
T1 P_GFX_RXP[11] P_GFX_TXP[11] T4
T2 P_GFX_RXN[11] P_GFX_TXN[11] T3
P3 P_GFX_RXP[12] P_GFX_TXP[12] P2
P4 P_GFX_RXN[12] P_GFX_TXN[12] P1
N1 P_GFX_RXP[13] P_GFX_TXP[13] M1
N2 P_GFX_RXN[13] P_GFX_TXN[13] M2
M4 P_GFX_RXP[14] P_GFX_TXP[14] K3
M3 P_GFX_RXN[14] P_GFX_TXN[14] K4
K2 P_GFX_RXP[15] P_GFX_TXP[15] J1
K1 P_GFX_RXN[15] P_GFX_TXN[15] J2
PCIE_RXP0_WLAN AH5 AG7 PCIE_TXP0_C C233 0.1U/10V_4 PCIE_TXP0_WLAN [24]
[24] PCIE_RXP0_WLAN P_GPP_RXP[0] P_GPP_TXP[0]
TO WLAN PCIE_RXN0_WLAN AH6 AG8 PCIE_TXN0_C C232 0.1U/10V_4 PCIE_TXN0_WLAN [24] TO WLAN
[24] PCIE_RXN0_WLAN P_GPP_RXN[0] P_GPP_TXN[0]
AG5 P_GPP_RXP[1] P_GPP_TXP[1] AE7
AG6 P_GPP_RXN[1] P_GPP_TXN[1] AE8
AE6 P_GPP_RXP[2] P_GPP_TXP[2] AD7
AE5 P_GPP_RXN[2] P_GPP_TXN[2] AD8
AD6 P_GPP_RXP[3] P_GPP_TXP[3] AB6
AD5 AB5

GPP
P_GPP_RXN[3] P_GPP_TXN[3]
C AM10 AN6 UMI_TXP0_C C280 0.1U/10V_4 UMI_TXP0 C
[7] UMI_RXP0 P_UMI_RXP[0] P_UMI_TXP[0] UMI_TXP0 [7]
[7] UMI_RXN0 AN10 AM6 UMI_TXN0_C C287 0.1U/10V_4 UMI_TXN0 UMI_TXN0 [7]
P_UMI_RXN[0] P_UMI_TXN[0] UMI_TXP1_C C303 0.1U/10V_4 UMI_TXP1
[7] UMI_RXP1 AN8 P_UMI_RXP[1] P_UMI_TXP[1] AP6 UMI_TXP1 [7]
AM8 AR6 UMI_TXN1_C C313 0.1U/10V_4 UMI_TXN1
[7] UMI_RXN1 P_UMI_RXN[1] P_UMI_TXN[1] UMI_TXN1 [7]
[7] UMI_RXP2 AP8 AP4 UMI_TXP2_C C272 0.1U/10V_4 UMI_TXP2 UMI_TXP2 [7]
P_UMI_RXP[2] P_UMI_TXP[2] UMI_TXN2_C C277 0.1U/10V_4 UMI_TXN2
[7] UMI_RXN2 AR8 P_UMI_RXN[2] P_UMI_TXN[2] AR4 UMI_TXN2 [7]
AR7 AP3 UMI_TXP3_C C261 0.1U/10V_4 UMI_TXP3
[7] UMI_RXP3 P_UMI_RXP[3] P_UMI_TXP[3] UMI_TXP3 [7]
[7] UMI_RXN3 AP7 AR3 UMI_TXN3_C C265 0.1U/10V_4 UMI_TXN3 UMI_TXN3 [7]
P_UMI_RXN[3] P_UMI_TXN[3]

UMI
+1.2V_VDDP R410 196/F_6 P_ZVDDP AR11 AP11 P_ZVSS R409 196/F_6
P_ZVDDP P_ZVSS
4/19 For Comal. TRINITY-A8-SERIES_BGA813

+3V

HDT+ Connector for Debug only VID Override Circuit


BOOT VOLTAGE
+1.5V
R200
*0_4/S 4/19 For Comal. SVC SVD VFIX_+VDD VFIX_+VDD
=VCC/GND =OPEN
R199 R198
1K/F_4 1K/F_4 0 0 1.1 1.1

U9 Note: 0 1 1.0 1.2


B APU_RST# 1 6 APU_RST_L_BUF B
[4,7] APU_RST# A1 Y1 To override VID,Remove Rd, Re, Rf, install Rc
2 5 set VID via SVC & SVD option RES. 1 0 0.9 1.0
GND VCC
APU_PWRGD 3 4 APU_PWROK_BUF
A2 Y2
1 1 0.8 0.8
*74LVC2G07

J1
+1.5VSUS 20
APU_TEST18 19
close to HDT [4] APU_TEST18 18
Rd
+1.5VSUS APU_TEST19 SVC R175 *0_4/S CPU_SVC
debug HEADER [4] APU_TEST19 17 [4] SVC CPU_SVC [36]
APU_RST_L_BUF Re
APU_TDI R202 1K/F_4 CPU_LDT_RST_HTPA# 16 SVD R179 *0_4/S CPU_SVD
TP70 15 [4] SVD CPU_SVD [36]
APU_TCK R204 1K/F_4 APU_DBREQ# Rf
[4] APU_DBREQ# 14
APU_TMS R203 1K/F_4 APU_DBRDY APU_PWRGD R196 *0_4/S CPU_PWRGD_SVID_REG CPU_PWRGD_SVID_REG [36]
[4] APU_DBRDY 13 [4,7] APU_PWRGD
APU_TRST# R201 1K/F_4 APU_TCK
[4] APU_TCK 12
APU_TMS APU_PWRGD have pull up 300ohm
[4] APU_TMS 11
APU_TDI
[4] APU_TDI
APU_TRST# 10 to +1.5V on page 4
[4] APU_TRST# APU_TDO 9
[4] APU_TDO 8
APU_DBREQ# R206 1K/F_4 APU_PWROK_BUF
7
A 6 A
5
4/19 For Comal. 4
3
2
1
*HDT CONN
88511-2001-20p-l
PROJECT : U56
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
NB5 Llano PCIE/UMI/GPP
Date: Tuesday, August 07, 2012 Sheet 2 of 39
5 4 3 2 1
5 4 3 2 1

03
M_A_DQ[0..63] [12] M_B_DQ[0..63] [13]
[12] M_A_A[15:0] U25B [13] M_B_A[15:0] U25C
M_A_A0 AA28 F15 M_A_DQ0 M_B_A0 Y33 C16 M_B_DQ0
M_A_A1 MA_ADD[0] MA_DATA[0] M_A_DQ1 M_B_A1 MB_ADD[0] MB_DATA[0] M_B_DQ1
R29 MA_ADD[1] MA_DATA[1] E15 R32 MB_ADD[1] MB_DATA[1] B17
M_A_A2 T30 H19 M_A_DQ2 M_B_A2 T31 B20 M_B_DQ2
M_A_A3 MA_ADD[2] MA_DATA[2] M_A_DQ3 M_B_A3 MB_ADD[2] MB_DATA[2] M_B_DQ3
R28 MA_ADD[3] MA_DATA[3] F19 P33 MB_ADD[3] MB_DATA[3] C20
D M_A_A4 R26 E14 M_A_DQ4 M_B_A4 P32 A16 M_B_DQ4 D
M_A_A5 MA_ADD[4] MA_DATA[4] M_A_DQ5 M_B_A5 MB_ADD[4] MB_DATA[4] M_B_DQ5
P26 MA_ADD[5] MA_DATA[5] H15 P31 MB_ADD[5] MB_DATA[5] B16
M_A_A6 P27 E17 M_A_DQ6 M_B_A6 N32 B19 M_B_DQ6
M_A_A7 MA_ADD[6] MA_DATA[6] M_A_DQ7 M_B_A7 MB_ADD[6] MB_DATA[6] M_B_DQ7
P30 MA_ADD[7] MA_DATA[7] D18 M33 MB_ADD[7] MB_DATA[7] A20
M_A_A8 P29 M_B_A8 M32
M_A_A9 MA_ADD[8] M_A_DQ8 M_B_A9 MB_ADD[8] M_B_DQ8
M28 MA_ADD[9] MA_DATA[8] G20 L32 MB_ADD[9] MB_DATA[8] B22
M_A_A10 AB26 E20 M_A_DQ9 M_B_A10 AB31 C22 M_B_DQ9
M_A_A11 MA_ADD[10] MA_DATA[9] M_A_DQ10 M_B_A11 MB_ADD[10] MB_DATA[9] M_B_DQ10
M26 MA_ADD[11] MA_DATA[10] H23 M31 MB_ADD[11] MB_DATA[10] A26
M_A_A12 M29 G23 M_A_DQ11 M_B_A12 K32 B26 M_B_DQ11
M_A_A13 MA_ADD[12] MA_DATA[11] M_A_DQ12 M_B_A13 MB_ADD[12] MB_DATA[11] M_B_DQ12
AE27 MA_ADD[13] MA_DATA[12] E19 AF33 MB_ADD[13] MB_DATA[12] B21
M_A_A14 L26 H20 M_A_DQ13 M_B_A14 K33 A22 M_B_DQ13
M_A_A15 MA_ADD[14] MA_DATA[13] M_A_DQ14 M_B_A15 MB_ADD[14] MB_DATA[13] M_B_DQ14
[12] M_A_BS#[2..0] L27 MA_ADD[15] MA_DATA[14] E22 [13] M_B_BS#[2..0] J32 MB_ADD[15] MB_DATA[14] C24
D22 M_A_DQ15 B25 M_B_DQ15
M_A_BS#0 MA_DATA[15] M_B_BS#0 MB_DATA[15]
AB27 MA_BANK[0] AB33 MB_BANK[0]
M_A_BS#1 AA29 H25 M_A_DQ16 M_B_BS#1 AA32 A28 M_B_DQ16
M_A_BS#2 MA_BANK[1] MA_DATA[16] M_A_DQ17 M_B_BS#2 MB_BANK[1] MB_DATA[16] M_B_DQ17
[12] M_A_DM[7..0] M30 MA_BANK[2] MA_DATA[17] F25 [13] M_B_DM[7..0] K31 MB_BANK[2] MB_DATA[17] B28
D28 M_A_DQ18 B31 M_B_DQ18
M_A_DM0 MA_DATA[18] M_A_DQ19 M_B_DM0 MB_DATA[18] M_B_DQ19
D16 MA_DM[0] MA_DATA[19] D29 C18 MB_DM[0] MB_DATA[19] A32
M_A_DM1 D20 E23 M_A_DQ20 M_B_DM1 B23 C26 M_B_DQ20
M_A_DM2 MA_DM[1] MA_DATA[20] M_A_DQ21 M_B_DM2 MB_DM[1] MB_DATA[20] M_B_DQ21
E25 MA_DM[2] MA_DATA[21] D24 C28 MB_DM[2] MB_DATA[21] B27
M_A_DM3 F30 D26 M_A_DQ22 M_B_DM3 D31 A30 M_B_DQ22
M_A_DM4 MA_DM[3] MA_DATA[22] M_A_DQ23 M_B_DM4 MB_DM[3] MB_DATA[22] M_B_DQ23
AK29 MA_DM[4] MA_DATA[23] D27 AM31 MB_DM[4] MB_DATA[23] C30
M_A_DM5 AL25 M_B_DM5 AN30
M_A_DM6 MA_DM[5] M_A_DQ24 M_B_DM6 MB_DM[5] M_B_DQ24
AM20 MA_DM[6] MA_DATA[24] G28 AR24 MB_DM[6] MB_DATA[24] B33
M_A_DM7 AM16 G29 M_A_DQ25 M_B_DM7 AN18 C32 M_B_DQ25
MA_DM[7] MA_DATA[25] M_A_DQ26 MB_DM[7] MB_DATA[25] M_B_DQ26
MA_DATA[26] H27 MB_DATA[26] F33
G17 J29 M_A_DQ27 B18 F32 M_B_DQ27
[12] M_A_DQSP0 MA_DQS_H[0] MA_DATA[27] M_A_DQ28 [13] M_B_DQSP0 MB_DQS_H[0] MB_DATA[27] M_B_DQ28
[12] M_A_DQSN0 H17 MA_DQS_L[0] MA_DATA[28] E28 [13] M_B_DQSN0 A18 MB_DQS_L[0] MB_DATA[28] B32
F22 F27 M_A_DQ29 B24 C31 M_B_DQ29
[12] M_A_DQSP1 MA_DQS_H[1] MA_DATA[29] [13] M_B_DQSP1 MB_DQS_H[1] MB_DATA[29]
G22 H29 M_A_DQ30 A24 E32 M_B_DQ30
C [12] M_A_DQSN1 MA_DQS_L[1] MA_DATA[30] M_A_DQ31 [13] M_B_DQSN1 MB_DQS_L[1] MB_DATA[30] M_B_DQ31 C
[12] M_A_DQSP2 E26 MA_DQS_H[2] MA_DATA[31] H28 [13] M_B_DQSP2 B30 MB_DQS_H[2] MB_DATA[31] F31
[12] M_A_DQSN2 F26 MA_DQS_L[2] [13] M_B_DQSN2 B29 MB_DQS_L[2]
H30 AH29 M_A_DQ32 D32 AK32 M_B_DQ32
[12] M_A_DQSP3 MA_DQS_H[3] MA_DATA[32] [13] M_B_DQSP3 MB_DQS_H[3] MB_DATA[32]
G30 AJ30 M_A_DQ33 D33 AL32 M_B_DQ33
[12] M_A_DQSN3 MA_DQS_L[3] MA_DATA[33] [13] M_B_DQSN3 MB_DQS_L[3] MB_DATA[33]
AL29 AM28 M_A_DQ34 AM32 AP32 M_B_DQ34
[12] M_A_DQSP4 MA_DQS_H[4] MA_DATA[34] M_A_DQ35 [13] M_B_DQSP4 MB_DQS_H[4] MB_DATA[34] M_B_DQ35
[12] M_A_DQSN4 AL30 MA_DQS_L[4] MA_DATA[35] AM27 [13] M_B_DQSN4 AM33 MB_DQS_L[4] MB_DATA[35] AN31
AH25 AH27 M_A_DQ36 AN28 AK31 M_B_DQ36
[12] M_A_DQSP5 MA_DQS_H[5] MA_DATA[36] [13] M_B_DQSP5 MB_DQS_H[5] MB_DATA[36]
AJ25 AH28 M_A_DQ37 AP29 AK33 M_B_DQ37
[12] M_A_DQSN5 MA_DQS_L[5] MA_DATA[37] [13] M_B_DQSN5 MB_DQS_L[5] MB_DATA[37]
AK20 AJ29 M_A_DQ38 AP23 AN32 M_B_DQ38
[12] M_A_DQSP6 MA_DQS_H[6] MA_DATA[38] [13] M_B_DQSP6 MB_DQS_H[6] MB_DATA[38]
AL20 AK27 M_A_DQ39 AP24 AP33 M_B_DQ39
[12] M_A_DQSN6 MA_DQS_L[6] MA_DATA[39] [13] M_B_DQSN6 MB_DQS_L[6] MB_DATA[39]
[12] M_A_DQSP7 AK15 MA_DQS_H[7] [13] M_B_DQSP7 AR18 MB_DQS_H[7]
AL15 AK26 M_A_DQ40 AP18 AP30 M_B_DQ40
[12] M_A_DQSN7 MA_DQS_L[7] MA_DATA[40] [13] M_B_DQSN7 MB_DQS_L[7] MB_DATA[40]
AJ26 M_A_DQ41 AR30 M_B_DQ41
MA_DATA[41] M_A_DQ42 MB_DATA[41] M_B_DQ42
[12] M_A_CLKP0 W 29 MA_CLK_H[0] MA_DATA[42] AK23 [13] M_B_CLKP0 W 32 MB_CLK_H[0] MB_DATA[42] AP27
Y30 AJ23 M_A_DQ43 Y32 AN26 M_B_DQ43
[12] M_A_CLKN0 MA_CLK_L[0] MA_DATA[43] [13] M_B_CLKN0 MB_CLK_L[0] MB_DATA[43]
W 26 AM26 M_A_DQ44 V33 AR32 M_B_DQ44
[12] M_A_CLKP1 MA_CLK_H[1] MA_DATA[44] [13] M_B_CLKP1 MB_CLK_H[1] MB_DATA[44]
W 27 AL26 M_A_DQ45 V32 AP31 M_B_DQ45
[12] M_A_CLKN1 MA_CLK_L[1] MA_DATA[45] M_A_DQ46 [13] M_B_CLKN1 MB_CLK_L[1] MB_DATA[45] M_B_DQ46
U29 MA_CLK_H[2] MA_DATA[46] AM24 U32 MB_CLK_H[2] MB_DATA[46] AR28
V30 AL23 M_A_DQ47 V31 AP28 M_B_DQ47
MA_CLK_L[2] MA_DATA[47] MB_CLK_L[2] MB_DATA[47]
U26 MA_CLK_H[3] T33 MB_CLK_H[3]
U27 AK22 M_A_DQ48 T32 AP25 M_B_DQ48
MA_CLK_L[3] MA_DATA[48] M_A_DQ49 MB_CLK_L[3] MB_DATA[48] M_B_DQ49
MA_DATA[49] AH22 MB_DATA[49] AN24
L29 AK19 M_A_DQ50 H32 AR22 M_B_DQ50
[12] M_A_CKE0 MA_CKE[0] MA_DATA[50] [13] M_B_CKE0 MB_CKE[0] MB_DATA[50]
K30 AH19 M_A_DQ51 H33 AP21 M_B_DQ51
[12] M_A_CKE1 MA_CKE[1] MA_DATA[51] [13] M_B_CKE1 MB_CKE[1] MB_DATA[51]
AM22 M_A_DQ52 AP26 M_B_DQ52
MA_DATA[52] M_A_DQ53 MB_DATA[52] M_B_DQ53
[12] M_A_ODT0 AD30 MA0_ODT[0] MA_DATA[53] AL22 [13] M_B_ODT0 AF31 MB0_ODT[0] MB_DATA[53] AR26
AG28 AJ20 M_A_DQ54 AH31 AN22 M_B_DQ54
[12] M_A_ODT1 MA0_ODT[1] MA_DATA[54] [13] M_B_ODT1 MB0_ODT[1] MB_DATA[54]
AE26 AL19 M_A_DQ55 AE32 AP22 M_B_DQ55
MA1_ODT[0] MA_DATA[55] MB1_ODT[0] MB_DATA[55]
AG29 MA1_ODT[1] AH33 MB1_ODT[1]
AK17 M_A_DQ56 AR20 M_B_DQ56
B MA_DATA[56] M_A_DQ57 MB_DATA[56] M_B_DQ57 B
[12] M_A_CS#0 AD26 MA0_CS_L[0] MA_DATA[57] AJ17 [13] M_B_CS#0 AD31 MB0_CS_L[0] MB_DATA[57] AP19
AE29 AK14 M_A_DQ58 AF32 AP16 M_B_DQ58
[12] M_A_CS#1 MA0_CS_L[1] MA_DATA[58] [13] M_B_CS#1 MB0_CS_L[1] MB_DATA[58]
AB30 AH14 M_A_DQ59 AC32 AR16 M_B_DQ59
MA1_CS_L[0] MA_DATA[59] M_A_DQ60 MB1_CS_L[0] MB_DATA[59] M_B_DQ60
AF30 MA1_CS_L[1] MA_DATA[60] AM18 AG32 MB1_CS_L[1] MB_DATA[60] AN20
AL17 M_A_DQ61 AP20 M_B_DQ61
MA_DATA[61] M_A_DQ62 MB_DATA[61] M_B_DQ62
[12] M_A_RAS# AB29 MA_RAS_L MA_DATA[62] AH15 [13] M_B_RAS# AB32 MB_RAS_L MB_DATA[62] AP17
AD29 AL14 M_A_DQ63 AD32 AN16 M_B_DQ63
[12] M_A_CAS# MA_CAS_L MA_DATA[63] [13] M_B_CAS# MB_CAS_L MB_DATA[63]
[12] M_A_WE# AD28 MA_W E_L [13] M_B_WE# AD33 MB_W E_L
+1.5VSUS R211 1K/F_4
[12] M_A_RST# J28 MA_RESET_L Soldermask openings for all bottom side vias/TPs under FS1 [13] M_B_RST# H31 MB_RESET_L
[12] M_A_EVENT# AA26 MA_EVENT_L [13,24] M_B_EVENT# Y31 MB_EVENT_L
+MEMVREF_CPU G32 M_VREF TRINITY-A8-SERIES_BGA813
+1.5VSUS R212 1K/F_4
C392 +1.5VSUS R217 39.2/F_4+M_ZVDDIO AJ32
220P/50V_4 M_ZVDDIO
Place close to APU within 1" TRINITY-A8-SERIES_BGA813 220P/50V_4
C393

+1.5VSUS

Reserved for AMD suggest


R210

A 1K/F_4 A

R214 *0_4/S +MEMVREF_CPU

R216 C394 C395


PROJECT : U56
1K/F_4
0.1U/10V_4 1000P/50V_4 Quanta Computer Inc.
Size Document Number Rev
Custom 1A
NB5 Llano DDR3 MEM I/F
Date: Tuesday, August 07, 2012 Sheet 3 of 39
5 4 3 2 1
5 4 3 2 1

Place caps with APU < 1 inch

DP0 output to
eDP to LVDS converter
[11] INT_eDP_TXP0
[11] INT_eDP_TXN0
route PCIE as 85ohm +/- 10%
C697
C696
0.1U/10V_4
0.1U/10V_4
INT_eDP_TXP0_C
INT_eDP_TXN0_C
H2
H1
U25D

DP0_TXP[0]
DP0_TXN[0]
DP0_AUXP
DP0_AUXN
M5
M6
INT_eDP_AUXP_C
INT_eDP_AUXN_C
C694
C695
0.1U/10V_4
0.1U/10V_4
INT_eDP_AUXP [11]
INT_eDP_AUXN [11]
LVDS INT_eDP_AUXP

INT_eDP_AUXN
R355

R356
*100K/F_4

*100K/F_4 +3V
04

DISPLAY PORT 0
H3 DP0_TXP[1] DP1_AUXP L5
Display port power 1.5V min 1.2v max : 1.65v H4 L6 INT_eDP_AUXP_C R368 1.8K_4
DP0_TXN[1] DP1_AUXN
F4 J5 INT_eDP_AUXN_C R369 1.8K_4
DP0_TXP[2] DP2_AUXP INT_HDMI_AUXP [27]
F3 DP0_TXN[2] DP2_AUXN J6 INT_HDMI_AUXN [27] HDMI
F1 DP0_TXP[3] DP3_AUXP P5
F2 DP0_TXN[3] DP3_AUXN P6
D D

DISPLAY PORT MISC.


E2 DP1_TXP[0] DP4_AUXP R5
E1 DP1_TXN[0] DP4_AUXN R6

DISPLAY PORT 1
D4 DP1_TXP[1] DP5_AUXP U5
D3 DP1_TXN[1] DP5_AUXN U6

D1 M7 FCH_LVDS_HPD
DP1_TXP[2] DP0_HPD FCH_LVDS_HPD [11]
D2 DP1_TXN[2] DP1_HPD L7
J7 HDMI_HPD_Q
DP2_HPD HDMI_HPD_Q [27]
C1 DP1_TXP[3] DP3_HPD P7
C2 DP1_TXN[3] DP4_HPD R7
U7 +1.5VSUS
IN_D2 C698 0.1U/10V_4 PEG_HDMI_TXDP2 DP5_HPD +1.5VSUS
[27] IN_D2 B2 DP2_TXP[0]
IN_D2# C699 0.1U/10V_4 PEG_HDMI_TXDN2 A2 C6 APU_BLEN
[27] IN_D2# DP2_TXN[0] DP_BLON APU_DIGON TP93
4/19 HDMI change to DP2 for Comal. DP_DIGON D7 TP95
IN_D1 C700 0.1U/10V_4 PEG_HDMI_TXDP1

DISPLAY PORT 2
[27] IN_D1 B3 DP2_TXP[1] DP_VARY_BL A6 APU_BLPWM [11]
DP2 output to IN_D1# C701 0.1U/10V_4 PEG_HDMI_TXDN1 A3
[27] IN_D1# DP2_TXN[1]
B6 DP_AUX_ZVSS R362 150/F_4 To AMD HDT R215 R383
HDMI connector IN_D0 C702 0.1U/10V_4 PEG_HDMI_TXDP0 B4
DP_AUX_ZVSS *39.2/F_4 301/F_4
[27] IN_D0 IN_D0# PEG_HDMI_TXDN0 DP2_TXP[2]
C703 0.1U/10V_4 A4 AL6
[27] IN_D0# DP2_TXN[2] TEST6
note --HDMI P&N can not swap Y23 APU_TEST9 M_TEST APU_TEST35
TEST9 TP54
C_TXC_HDMI+ C704 0.1U/10V_4 PEG_HDMI_TXCP B5 V23 APU_TEST10
[27] IN_CLK DP2_TXP[3] TEST10 TP53
C_TXC_HDMI- C705 0.1U/10V_4 PEG_HDMI_TXCN A5 G9 APU_TEST14_BP0
[27] IN_CLK# DP2_TXN[3] TEST14 TP60
F9 APU_TEST15_BP1 M_TEST CONNECTION TBD 7/8 For Comal.
TEST15 TP58
CLK_APU_P AL9 E9 APU_TEST16_BP2 R213 R376
[7] CLK_APU_P CLKIN_H TEST16 TP64
Note: CLK_APU_HCLKP/N is 100MHZ SSC CLK_APU_N AK9 G8 APU_TEST17_BP3 39.2/F_4 *301/F_4
[7] CLK_APU_N CLKIN_L TEST17 APU_TEST18 TP59

TEST
TEST18 F12 APU_TEST18 [2]
CLK_DP_P APU_TEST19

CLK
[7] CLK_DP_P AL7 DISP_CLKIN_H TEST19 E12 APU_TEST19 [2]
Note: CLK_DP_NSSCP/N is 100MHZ non-SSC CLK_DP_N AK7 F14 APU_TEST20_SCANCLK2
C [7] CLK_DP_N DISP_CLKIN_L TEST20 APU_TEST24_SCANCLK1 TP67 C
G12 TEST35 PU FOR INTERNAL
TEST24 TP65
SVC E5 AJ8 APU_TEST25_H TEST35 PD FOR CUSTOMER
[2] SVC SVD SVC TEST25_H APU_TEST25_L TP51
[2] SVD E6 SVD TEST25_L AH8 TP47
G14 APU_TEST28_H
TEST28_H TP68

SER.
R176 0_4 APU_SVT_R D6 H14 APU_TEST28_L
[36] CPU_SVT SVT TEST28_L TP69
+1.5V R174 *1K/F_4 V25 DMAACTIVE_L controls
APU_SIC TEST30_H
AJ11 SIC TEST30_L Y25 entry and exit from the
APU_SID AH11 AH32 M_TEST +1.2V
R190 301/F_4 SID TEST31 sleep and power states
+1.5V TEST32_H R25
APU_RST# AK11 T25 APU_TEST25_L R178 510/F_4
[2,7] APU_RST# RESET_L TEST32_L
APU_PWRGD AH9 AL5 APU_TEST35
[2,7] APU_PWRGD PW ROK TEST35
+1.5V R197 301/F_4
APU_PROCHOT# DMAACTIVE_L APU_TEST9 R195 *0_4

CTRL
AL12 PROCHOT_L DMAACTIVE_L AP10 DMAACTIVE_L [7]
APU_THERMTRIP# AK5 R398 *1K/F_4 +1.5V
R407 1K/F_4 APU_ALERT THERMTRIP_L CPU_THERMDA R401 1K/F_4 +1.5VSUS
+1.5VSUS AR10 ALERT_L TEST4 T23 TP49
R23 CPU_THERMDC APU_TEST18 R171 1K/F_4
TEST5 TP55
APU_TDI E11 APU_TEST19 R172 1K/F_4
[2] APU_TDI APU_TDO TDI APU_TEST20_SCANCLK2
G11 R186 1K/F_4
[2] APU_TDO TDO
APU_TCK H12 APU_TEST24_SCANCLK1 R185 1K/F_4
[2] APU_TCK TCK
APU_TMS APU_TEST25_H R180 510/F_4

JTAG
[2] APU_TMS F11 TMS RSVD L8
PV change to short-pad APU_TRST# H11 P8
[2] APU_TRST# TRST_L RSVD
APU_DBRDY E8 AH12
[2] APU_DBRDY APU_DBREQ# DBRDY RSVD

RSVD
[2] APU_DBREQ# E7 DBREQ_L RSVD AJ12
RSVD AK12
R361 *0_4/S VSS_SENSE G6
[36] CPU_VDD0_RUN_FB_L VDDP_FB_H VSS_SENSE
[30] VDDP_FB_H H6 VDDP_SENSE
CPU_VDDNB_RUN_FB_H H5
[36] CPU_VDDNB_RUN_FB_H VDDNB_SENSE
VDDIO_FB_H G7

SENSE
+1.5VSUS [32] VDDIO_FB_H VDDIO_SENSE
CPU_VDD0_RUN_FB_H G5
[36] CPU_VDD0_RUN_FB_H VDD_SENSE
VDDP_FB_H H7
B VDDR_SENSE B

TP91 TRINITY-A8-SERIES_BGA813

Thermal R405
10K/F_4 R406
TP57
TP94
TP71
+1.5V +1.5VSUS

1K/F_4
4/19 For Comal, R378 R377
*1K/F_4 1K/F_4 +1.5VSUS +1.5VSUS
close to APU.
2

Q18
MMBT3904 R372 0_4 APU_PROCHOT#
[36] VRHOT
3 1 APU_THERMTRIP# R379 0_4 APU_PROCHOT#
[6] FCH_THERMTRIP# [7] FCH_PROCHOT#
度C
THERMTRIP# shutdown temperature 125度 R386 R395 R402 R389
R373 0_4 2K/F_4 2K/F_4 1K/F_4 1K/F_4
[26] H_PROCHOT#
3920_RST# to EC reserve only
3920_RST# [26]
C708

2
Q5 D6 220P/50V_4 Q19
3

MMBT3904 BAS316/DG MMBT3904


2 2 1 ECPWROK MBCLK2 3 1 APU_SIC
ECPWROK [10,26] [11,23,26] MBCLK2
R125 10K/F_4 +3V
1

1 2
RB501V-40 D10
SYS_SHDN-1# 3 1 DGPU_OVT# [15]

2
R151
Q24 *2N7002 +3VPCU +5VPCU U22 *11.5K/F_4 R152 Q20
*G718 *11.5K/F_4 MBDATA2 MMBT3904 3 1 APU_SID
DGPU_PWROK [6,7,26,33,34,35] [11,23,26] MBDATA2
2

1 VCC TMSNS1 8
THERMTRIP# R164 0_4 FCH_THERMTRIP#
2

A R161 *100K_6 NTC 1 2 A


R159 *0_4 R382 C251 2 7 R150 *8.87K/F_4 2 1 RB501V-40 D9
HW_ALERT# [24] GND RHYST1
3

10K/F_4 *1U/6.3V_4
1

D8 *RB501V-40 R162 *0_4/S 3 6


Q6 OT1 TMSNS2
2 2 1 HWPG [26,29,30,31,32]
*ME2N7002E HW_ALERT# 4 5 R139 *8.87K/F_4 2 1
PROJECT : U56
OT2 RHYST2
R138 *100K_6 NTC
Quanta Computer Inc.
over 120 degree C= Low
1

When 100K-NTC 100 C=6.164K Size Document Number Rev


ADD VGA TEMP_ FAIL function is active Hi
Thermal Trip = 120 C Llano Display/Misc 1A
NB5 Date: Tuesday, August 07, 2012 Sheet 4 of 39
5 4 3 2 1
5 4 3 2 1

05
U25F
APU POWER TABLE EMI suggestion
+VCC_CORE A17 Y11
PIN NAME NET NAME VSS VSS
VOLTAGE A19 VSS VSS Y12
A21 VSS VSS Y14
VDD +VCC_CORE +1.1V A23 Y15
VSS VSS
A25 VSS VSS Y17
VDDNB +VDDNB_CORE ?? A27 Y19
C357 C328 C356 VSS VSS
A29 VSS VSS Y20
VDDIO +1.5VSUS +1.5V 470P/50V_4 *470P/50V_4 *470P/50V_4 A31 Y22
VSS VSS
B1 VSS VSS AA4
VDDP +1.2V_VDDP +1.2V C3 AA5
VSS VSS
C4 VSS VSS AB7
VDDR +1.2V_VDDR +1.2V C33 AB8
D VSS VSS D
D5 AC1
VDDA +2.5V_VDDA +2.5V +VCC_CORE 36A D9
VSS VSS
AC2
+VCC_CORE VSS VSS
U25E Maximum IDDspike 50A D11
D13
VSS VSS AC4
AC9
VSS VSS
J12 VDD VDD V17 D15 VSS VSS AC11
J14 VDD VDD V19 D17 VSS VSS AC12
+VDDNB_CORE J15 V20 D19 AC14
VDD VDD C333 C335 C346 C359 C315 C706 C345 C317 VSS VSS
J17 VDD VDD V22 D21 VSS VSS AC15
J19 W8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 D23 AC17
VDD VDD VSS VSS
J20 VDD VDD AA8 D25 VSS VSS AC19
J22 VDD VDD AA9 D30 VSS VSS AC20
M11 VDD VDD AA11 E4 VSS VSS AC22
C728 C743 C729 C734 M12 AA12 E27 AC23
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 VDD VDD VSS VSS
M14 VDD VDD AA14 E29 VSS VSS AC25
M15 AA15 C330 C331 C309 C285 C316 C693 C323 E30 AE4
VDD VDD 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 *22U/6.3VS_8 VSS VSS
M17 VDD VDD AA17 E33 VSS VSS AF9
M19 VDD VDD AA19 F5 VSS VSS AF11
M20 VDD VDD AA20 F6 VSS VSS AF12
M22 VDD VDD AA22 F7 VSS VSS AF14
R8 VDD VDD AD9 F8 VSS VSS AF15
C291 C292 C290 C288 C289 R9 AD11 F17 AF17
0.22U/10V_4 0.22U/10V_4 180P/50V_4 180P/50V_4 180P/50V_4 VDD VDD VSS VSS
R11 VDD VDD AD12 F20 VSS VSS AF19
R12 AD14 C319 C369 C332 C338 C358 C360 C347 C349 F23 AF20
VDD VDD 0.22U/10V_4 0.22U/10V_4 180P/50V_4 180P/50V_4 180P/50V_4 0.01U/25V_4 0.01U/25V_4 0.01U/25V_4 VSS VSS
R14 VDD VDD AD15 F28 VSS VSS AF22
R15 VDD VDD AD17 F29 VSS VSS AF23
R17 VDD VDD AD19 G1 VSS VSS AF25
R19 VDD VDD AD20 G2 VSS VSS AG1
R20 VDD VDD AD22 G4 VSS VSS AG2
+VDDNB_CAP R22 AG12 G15 AG4
VDD VDD VSS VSS
U8 VDD VDD AG14 G19 VSS VSS AG9
C V9 AG15 G25 AG11 C
VDD VDD VSS VSS
V11 VDD VDD AG17 G26 VSS VSS AG26
V12 VDD VDD AG19 G27 VSS VSS AH7
V14 AG20 G33 AH17
C297 C294 C295 C296 C286 V15
VDD VDD
AG22
25A H8
VSS VSS
AH20
22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 22U/6.3VS_8 180P/50V_4 +VDDNB_CORE VDD VDD +VDDNB_CORE VSS VSS
Maximum IDDNBspike 33A H9
H22
VSS VSS AH23
AH26
VSS VSS
A7 VDDNB VDDNB B11 H26 VSS VSS AH30
A8 VDDNB VDDNB B12 J4 VSS VSS AJ4
A9 B13 J8 AJ5
+VDDP_CAP A10
VDDNB VDDNB
B14
DECOUPLING between PROCESSOR and DIMMs J9
VSS VSS
AJ6
VDDNB VDDNB VSS VSS
A11 B15 J11 AJ7
A12
VDDNB VDDNB
C8
Across VDDIO and VSS split J23
VSS VSS
AJ9
VDDNB VDDNB +1.5VSUS VSS VSS
A13 VDDNB VDDNB C10 J25 VSS VSS AJ14
A14 VDDNB VDDNB C12 J26 VSS VSS AJ15
A15 VDDNB VDDNB C14 J27 VSS VSS AJ19
C298 C299 B7 D8 J30 AJ22
22U/6.3VS_8 *22U/6.3VS_8 VDDNB VDDNB C425 C493 C365 C422 C412 C477 C756 C757 VSS VSS
B8 VDDNB VDDNB D10 K9 VSS VSS AJ27
B9 D12 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 K11 AJ28
VDDNB VDDNB +VDDNB_CAP VSS VSS
B10 VDDNB VDDNB D14 K12 VSS VSS AJ33
K14 VSS VSS AK6
VDDNB_CAP M9 K15 VSS VSS AK8
+1.5VSUS N9 K17 AK25
VDDNB_CAP VSS VSS
2.8A Up to DDR3-1333 @ 1.50V VDDIO K19 VSS VSS AK28
J33 VDDIO VDDIO W 33 If the VSS plane is cut to create a VDDIO plane, K20 VSS VSS AK30
K23 AA23 K22 AL1
K25
VDDIO VDDIO
AA25
ceramic capacitors are connected across L1
VSS VSS
AL2
VDDIO VDDIO VSS VSS
C448 C414 C450 C418 C468 C361 L28 VDDIO VDDIO AA27 the VDDIO and VSS plane split as follows L2 VSS VSS AL4
0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 L30 AA30 +1.5VSUS L4 AL8
VDDIO VDDIO VSS VSS
L33 VDDIO VDDIO AA33 M8 VSS VSS AL11
B M27 AB28 M23 AL27 B
VDDIO VDDIO VSS VSS
N23 VDDIO VDDIO AC30 M25 VSS VSS AL28
N25 VDDIO VDDIO AC33 N4 VSS VSS AL33
C390 C471 C445 C464 C368 N30 AD23 C362 C363 C421 C426 C415 C366 N11 AM5
180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 VDDIO VDDIO 22U/6.3VS_8 22U/6.3VS_8 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 VSS VSS
N33 VDDIO VDDIO AD25 N12 VSS VSS AM7
P28 VDDIO VDDIO AD27 N14 VSS VSS AM9
R27 VDDIO VDDIO AE28 N15 VSS VSS AM11
+1.2V_VDDP R30 AE30 N17 AM15
VDDIO VDDIO VSS VSS
VDDP = 5A R33 VDDIO VDDIO AE33 N19 VSS VSS AM17
U28 VDDIO VDDIO AG23 N20 VSS VSS AM19
+1.2V R413 *0_8/S +1.2V_VDDP U30 AG25 N22 AM21
VDDIO VDDIO VSS VSS
U33 VDDIO VDDIO AG27 R1 VSS VSS AM23
W 28 VDDIO VDDIO AG30 R2 VSS VSS AM25
C723 C727 C720 C724 W 30 AG33 R4 AM29
22U/6.3VS_8 0.22U/10V_4 0.22U/10V_4 22U/6.3VS_8 VDDIO VDDIO VSS VSS
VDDR = 3.3A ( Up to DDR3-1333 @ 1.5V ) +1.2V
T9 VSS VSS AM30
AM12 VDDP VDDR AN14 T11 VSS VSS AN3
AN12 VDDP VDDR AP14 T12 VSS VSS AN4
AP12 VDDP VDDR AP15 T14 VSS VSS AN33
AP13 AR14 +1.2V_VDDR_B R414 *0_8/S T15 AP5
VDDP VDDR VSS VSS
AR12 VDDP VDDR AR15 T17 VSS VSS AP9
AR13 VDDP T19 VSS VSS AR2
C725 C730 C731 C740 C732 C738 C735 C733 T20 AR5
180P/50V_4 180P/50V_4 *22U/6.3VS_8 0.22U/10V_4 0.22U/10V_4 1000P/50V_4 180P/50V_4 180P/50V_4 VSS VSS
AA6 VDDP_CAP T22 VSS VSS AR9
+VDDP_CAP AA7 VDDP_CAP U4 VSS VSS AR17
W1 VSS VSS AR19
AM13 VDDA W2 VSS VSS AR21
TP66 AM14 VDDA W4 VSS VSS AR23
W5 VSS VSS AR25
TRINITY-A8-SERIES_BGA813 W6 VSS VSS AR27
W7 VSS VSS AR29
A Y9 AR31 A
VSS VSS
VDDA= 0.75A
TRINITY-A8-SERIES_BGA813
L32 +2.5V_VDDA
+2.5V
PBY160808T-221Y-N(220,2A)

C348
4.7U/6.3V_6
C343
0.22U/10V_4
C344
3300P/50V_4
PROJECT : U56
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
NB5 Llano POWER/GND
Date: Wednesday, July 11, 2012 Sheet 5 of 39
5 4 3 2 1
5 4 3 2 1

+3VS5
NC,no install by default
R166

R173
*2.2K_4

*2.2K_4
FCH_TEST0

FCH_TEST1 TP106
TP101
PCIE_RST2#
RI#
AB6
R2
W7
U23A
PCIE_RST2#/GEVENT4#
RI#/GEVENT22#
USBCLK/14M_25M_48M_OSC G8

B9 USB_RCOMP_SB R348 11.8K/F_6


06
R169 *2.2K_4 FCH_TEST2 SUSB# SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
[26] SUSB# T3 SLP_S3#
SUSC# W2 H1

MISC
[26] SUSC# SLP_S5# USB_FSD1P/GPIO186

USB
DNBSWON# J4 H3
[26] DNBSWON# FCH_PWRGD PW R_BTN# USB_FSD1N
[10] FCH_PWRGD N7 PW R_GOOD HUDSON-M3 USB_FSD0P/GPIO185 H6
FCH_TEST0 T9 Part 4 of 5 H5
D +3V FCH_TEST1 TEST0 USB_FSD0N D
T10

USB
TP44 TEST1/TMS
FCH_TEST2

1.1
ACPI / WAKE UP
V9 TEST2 USB_HSD13P H10
R192 2.2K_4 SMB_RUN_CLK GEVENT0# internal pull Hi 8.2K to +3V EC_A20GATE AE22 G10
[26] EC_A20GATE GA20IN/GEVENT0# USB_HSD13N
to DDR3 SMBUS GEVENT1# internal pull Hi 8.2K to +3V EC_RCIN# AG19
[26] EC_RCIN# KBRST#/GEVENT1#
R193 2.2K_4 SMB_RUN_DAT FCH_PME# R9 K10

EVENTS
TP42 SIO_EXT_SMI# PME#/GEVENT3# USB_HSD12P
GEVENT23# internal pull Hi 8.2K to +3V [26] SIO_EXT_SMI# C26 LPC_SMI#/GEVENT23# USB_HSD12N J12
+3VS5 GEVENT5# internal pull Hi 8.2K to +3VS5 R394 *0_4/S GEVENT5# T5
[26] SIO_EXT_SCI# LPC_PD#/GEVENT5#
SYS_RST# U4 G12 USBP11+
SYS_RESET#/GEVENT19# USB_HSD11P USBP11+ [23]
PCIE_WAKE# no need to pull PCIE_WAKE# K1 F12 USBP11- USB Combo 3.0/2.0.
[21,24] PCIE_WAKE# W AKE#/GEVENT8# USB_HSD11N USBP11- [23]
C690 *100P/50V_4 V7
R168 *1K_4 SYS_RST#
Hi resistor from check list FCH_THERMTRIP# R10 IR_RX1/GEVENT20# USBP10+
[4] FCH_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD10P K12 USBP10+ [23]
SYS_RST# internal +3V R189 10K/F_4 WD_PWRGD AF19 K13 USBP10- USB Combo 3.0/2.0.
W D_PW RGD USB_HSD10N USBP10- [23]
10K pull up RSMRST#
[26] RSMRST# U2 RSMRST# USB_HSD9P B11
USB_HSD9N D11
PCIE_CLKREQ_CR# AG24
[22] PCIE_CLKREQ_CR# CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ2# internal pull Hi 8.2K to +3V PCIE_CLKREQ_LAN# AE24 E10 USBP8+
[21] PCIE_CLKREQ_LAN# CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD8P USBP8- USBP8+ [27]
AE26 SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD8N F10 USBP8- [27] CAMERA
CLK_REQ3# internal pull Hi 8.2K to +3V AF22 CLK_REQ0#/SATA_IS3#/GPIO60
+3VS5 AH17 C10
SATA_IS4#/FANOUT3/GPIO55 USB_HSD7P
CLK_REQ4# internal pull Hi 8.2K to +3V AG18 SATA_IS5#/FANIN3/GPIO59 USB_HSD7N A10
R134 10K/F_4 SCL3 R415 *0_4/S FCH_GPIO66 AF24
[20] SPKR SPKR/GPIO66
SMB_RUN_CLK AD26 H9
[12,13] SMB_RUN_CLK SCL0/GPIO43 USB_HSD6P
R136 10K/F_4 SDA3 SMB_RUN_DAT AD25 G9

USB
[12,13] SMB_RUN_DAT SDA0/GPIO47 USB_HSD6N
SCL1

2.0
[11,25] SCL1 T7 SCL1/GPIO227
R128 10K/F_4 SCL2 SDA1 R7 A8
[11,25] SDA1 SDA1/GPIO228 USB_HSD5P
PCIE_CLKREQ_WLAN#AG25 C8
SDA2 [24] PCIE_CLKREQ_WLAN# CLKREQ1# CLK_REQ2#/FANIN4/GPIO62 USB_HSD5N
R132 10K/F_4 AG22

GPIO
RF_OFF1# CLK_REQ1#/FANOUT4/GPIO61
[24] RF_OFF1# J2 IR_LED#/LLB#/GPIO184 USB_HSD4P F8
This pin is used to SMARTVOLT2 AG26 E8
C SCL1 TP62 VGA_PD SMARTVOLT2/SHUTDOW N#/GPIO51 USB_HSD4N C
R156 2.2K_4 power down VGA DAC TP45 V8
GBE_LED0 DDR3_RST#/GEVENT7#/VGA_PD
TP46 W8 GBE_LED0/GPIO183 USB_HSD3P C6 USBP3+ [24]
R155 2.2K_4 SDA1 regulators when CRT Y6 A6 Touch screen
SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD3N USBP3- [24]
no connected V10 GBE_LED2/GEVENT10#
AA8 GBE_STAT0/GEVENT11# USB_HSD2P C5 USBP2+ [24]
R160 *4.7K_4 FCH_THERMTRIP# AF25 A5 WLAN Min-Card
TP52 CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD2N USBP2- [24]
C271 *0.01U/25V_4 C1
USB_HSD1P
TP90 M7 BLINK/USB_OC7#/GEVENT18# USB_HSD1N C3
R8 USB_OC6#/IR_TX1/GEVENT6# EXternal MIC
ODD_PLUGIN# T1 E1
TP103 USB_OC5#/IR_TX0/GEVENT17# USB_HSD0P USBP0+ [20]
R353 10K/F_4 DNBSWON# GEVENT16# internal pull Hi 8.2K to +3VS5 P6 E3 LEFT side USB 2.0 Connector
USB_OC4#/IR_RX0/GEVENT16# USB_HSD0N USBP0- [20]
TP35 F5 USB_OC3#/AC_PRES/TDO/GEVENT15#
GEVENT15# internal pull Hi 8.2K to +3VS5 4/19 For Comal. FCH_JTAG_TCK P5 C16 USBSS_CALRP R349 1K/F_4
TP100

USB
FCH_JTAG_TDI USB_OC2#/TCK/GEVENT14# USBSS_CALRP USBSS_CALRN R342 1K/F_4

OC
For Zero ODD TP89
FCH_JTAG_RST#
J7
T8
USB_OC1#/TDI/GEVENT13# USBSS_CALRN A16 +FCH_VDD_11_SSUSB_S
TP43 USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
A14
To Azalia USB_SS_TX3P
USB_SS_TX3N C14 USB 3.0 Not Implemented: left unconnected.
ACZ_SDOUT_R R399 33_4 R404 *10K/F_4 ACZ_BCLK_R AB3 C12
ACZ_SDOUT_AUDIO [20] ACZ_SDOUT_R AZ_BITCLK USB_SS_RX3P
AB1 AZ_SDOUT USB_SS_RX3N A12
ACZ_SYNC_R R400 33_4 HD audio R396 *10K/F_4 ACZ_SDIN0 AA2
ACZ_SYNC_AUDIO [20] ACZ_SDIN1 AZ_SDIN0/GPIO167
interface is R391 *10K/F_4 Y5 D15
ACZ_BCLK_R R403 33_4 R397 *10K/F_4 ACZ_SDIN2_R AZ_SDIN1/GPIO168 USB_SS_TX2P
BIT_CLK_AUDIO [20] Y3 AZ_SDIN2/GPIO169 USB_SS_TX2N B15
+3V_S5 voltage R390 *10K/F_4 ACZ_SDIN3_R Y1
ACZ_RST#_R R411 33_4 ACZ_SYNC_R AZ_SDIN3/GPIO170
ACZ_RST#_AUDIO [20] AD6 AZ_SYNC USB_SS_RX2P E14
ACZ_RST#_R AE4 F14
ACZ_SDIN0 AZ_RST# USB_SS_RX2N
ACZ_SDIN0 [20]

USB
F15

AUDIO

3.0
USB_SS_TX1P USB30_TX1+ [23]
TP36 K19 PS2_DAT/SDA4/GPIO187 USB_SS_TX1N G15 USB30_TX1- [23]

HD
B C273 C278 J19 B
TP34 PS2_CLK/CEC/SCL4/GPIO188
*33P/50V_4 33P/50V_4 J21 SPI_CS2#/GBE_STAT2/GPIO166 USB_SS_RX1P H13 USB30_RX1+ [23]
USB_SS_RX1N G13 USB30_RX1- [23]
BT_COMBO_OFF# D21 J16
[24] BT_COMBO_OFF# PS2KB_DAT/GPIO189 USB_SS_TX0P USB30_TX0+ [23]
6/21/2012 for EMI C20 PS2KB_CLK/GPIO190 USB_SS_TX0N H16 USB30_TX0- [23]
VGA_RSTB D23
[14] VGA_RSTB PS2M_DAT/GPIO191
[26] VGA_ON_SB VGA_ON_SB C22 J15
PS2M_CLK/GPIO192 USB_SS_RX0P USB30_RX0+ [23]
USB_SS_RX0N K15 USB30_RX0- [23]
F21 KSO_0/GPIO209 SCL3 of a TSI-capable APU's
E20 H19 SCL2
KSO_1/GPIO210 SCL2/GPIO193 SDA2
thermal bus,Pulled up to
F20 KSO_2/GPIO211 SDA2/GPIO194 G19
A22 G22 SCL3 APU_VDDIO. Resistor value
KSO_3/GPIO212 SCL3_LV/GPIO195
E18 KSO_4/GPIO213 SDA3_LV/GPIO196 G21 SDA3 verified in the relevant APU
CLK_REQ# already A20 KSO_5/GPIO214 EC_PW M0/EC_TIMER0/GPIO197 E22 design guide.
Pure UMA can remove internal pull up 8.2K J18 KSO_6/GPIO215 EC_PW M1/EC_TIMER1/GPIO198 H22
H18 J22 EC_PWM2
KSO_7/GPIO216 EC_PW M2/EC_TIMER2/W OL_EN/GPIO199 EC_PWM2 [10]
1 2 CLKREQ1# G18 H21
[34] VGA_REQ KSO_8/GPIO217 EC_PW M3/EC_TIMER3/GPIO200
B21 No need for GPIO200
D20 RB501V-40 KSO_9/GPIO218
K18 KSO_10/GPIO219 KSI_0/GPIO201 K21
D19 EMBEDDED K22
KSO_11/GPIO220 CTRL KSI_1/GPIO202
A18 KSO_12/GPIO221 KSI_2/GPIO203 F22
R421 C18 KSO_13/GPIO222 KSI_3/GPIO204 F24
3

B19 KSO_14/XDB0/GPIO223 KSI_4/GPIO205 E24


2 Q21 B17 B23
33,34,35] DGPU_PWROK KSO_15/XDB1/GPIO224 KSI_5/GPIO206
*MMBT3904-7-F A24 C24
KSO_16/XDB2/GPIO225 KSI_6/GPIO207
D17 F18
1

10K/F_4 KSO_17/XDB3/GPIO226 KSI_7/GPIO208

A A

Hudson-M3-A14

PROJECT : U56
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
NB5 Hudson-M3 GPIO/USB/AZ/RGMII
Date: Tuesday, August 07, 2012 Sheet 6 of 39
5 4 3 2 1
5 4 3 2 1

C744 150P/50V_4

07
[22] CARD_PCIE_RST# R418 33_4
[22,24] MINI_PCIE_RST# R420 33_4

C745 150P/50V_4 U23E


R335 *33_4 CLK_33M_DEBUG
C747 150P/50V_4
[21] LAN_PCIE_RST# R422 33_4 PCIE_RST# AE2 PCIE_RST#
HUDSON-M3 PCICLK0 AF3
R423 33_4 A_RST# AD5 Part 1 of 5 AF1 PCI_CLK1
[14] GPU_RST# A_RST# PCICLK1/GPO36 PCI_CLK1 [10]
C750 150P/50V_4 AF5
C370 0.1U/10V_4 UMI_RXP0_C PCICLK2/GPO37 PCI_CLK3
[2] UMI_RXP0 AE30 UMI_TX0P PCICLK3/GPO38 AG2 PCI_CLK3 [10]
[2] UMI_RXN0 C367 0.1U/10V_4 UMI_RXN0_C AE32 AF6 PCI_CLK4 PCI_CLK4 [10]
C351 0.1U/10V_4 UMI_RXP1_C UMI_TX0N PCICLK4/14M_OSC/GPO39
[2] UMI_RXP1 AD33

CLKS
C355 0.1U/10V_4 UMI_RXN1_C UMI_TX1P PCIRST#_L R408 33_4 KBC_RST# C717 *150P/50V_4
Place these PICE AC AD31 AB5

PCI
D
[2] UMI_RXN1 UMI_TX1N PCIRST# D
[2] UMI_RXP2 C336 0.1U/10V_4 UMI_RXP2_C AD28
coupling cap close to FCH C342 0.1U/10V_4 UMI_RXN2_C AD29
UMI_TX2P
[2] UMI_RXN2 UMI_TX2N
C324 0.1U/10V_4 UMI_RXP3_C AC30 AJ3
[2] UMI_RXP3 UMI_TX3P AD0/GPIO0 KBC_RST# [26]
C329 0.1U/10V_4 UMI_RXN3_C AC32 AL5
[2] UMI_RXN3 UMI_TX3N AD1/GPIO1
AD2/GPIO2 AG4
[2] UMI_TXP0 AB33 UMI_RX0P AD3/GPIO3 AL6
[2] UMI_TXN0 AB31 UMI_RX0N AD4/GPIO4 AH3
[2] UMI_TXP1 AB28 UMI_RX1P AD5/GPIO5 AJ5
[2] UMI_TXN1 AB29 UMI_RX1N AD6/GPIO6 AL1
[2] UMI_TXP2 Y33 UMI_RX2P AD7/GPIO7 AN5
[2] UMI_TXN2 Y31 UMI_RX2N AD8/GPIO8 AN6
[2] UMI_TXP3 Y28 UMI_RX3P AD9/GPIO9 AJ1
[2] UMI_TXN3 Y29 UMI_RX3N AD10/GPIO10 AL8

PCI EXPRESS
INTERFACES
AD11/GPIO11 AL3
R416 590/F_4 PCIE_CALRP_FCH AF29 AM7
R417 2K/F_4 PCIE_CALRN_FCH PCIE_CALRP AD12/GPIO12
+1.1V_PCIE_VDDR AF31 PCIE_CALRN AD13/GPIO13 AJ6
AD14/GPIO14 AK7
0.1U/10V_4 C715 PCIE_TXP0_CARD_C V33 AN8
[22] PCIE_TXP0_CARD GPP_TX0P AD15/GPIO15
[22] PCIE_TXN0_CARD 0.1U/10V_4 C713 PCIE_TXN0_CARD_C V31 AG9
0.1U/10V_4 C716 PCIE_TXP1_C GPP_TX0N AD16/GPIO16
[21] PCIE_TXP1_LAN W 30 GPP_TX1P AD17/GPIO17 AM11
0.1U/10V_4 C718 PCIE_TXN1_C W 32 AJ10
[21] PCIE_TXN1_LAN GPP_TX1N AD18/GPIO18
AB26 GPP_TX2P AD19/GPIO19 AL12
AB27 GPP_TX2N AD20/GPIO20 AK11
AA24 GPP_TX3P AD21/GPIO21 AN12
AA23 GPP_TX3N AD22/GPIO22 AG12
AE12 PCI_AD23 PCI_AD23 [10]
PCIE_RXP0_CARD AD23/GPIO23 PCI_AD24
[22] PCIE_RXP0_CARD AA27 GPP_RX0P AD24/GPIO24 AC12 PCI_AD24 [10]
PCIE_RXN0_CARD AA26 AE13 PCI_AD25 PCI_AD25 [10]
[22] PCIE_RXN0_CARD GPP_RX0N AD25/GPIO25
PCIE_RXP1_LAN W 27 AF13 PCI_AD26 PCI_AD26 [10]
[21] PCIE_RXP1_LAN GPP_RX1P AD26/GPIO26
PCIE_RXN1_LAN V27 AH13 PCI_AD27 PCI_AD27 [10]
C [21] PCIE_RXN1_LAN GPP_RX1N AD27/GPIO27 C

INTERFACE
V26 GPP_RX2P AD28/GPIO28 AH14 DGPU_PWROK [4,6,26,33,34,35]
W 26 AD15 HUDSON_MEMHOT#_R
GPP_RX2N AD29/GPIO29 TP56
W 24 GPP_RX3P AD30/GPIO30 AC15
W 23 AE16

PCI
GPP_RX3N AD31/GPIO31 D4
CBE0# AN3
AJ8 RB500V-40
CBE1# +3V_RTC
CBE2# AN10 1 2 +3VPCU
R129 2K/F_4 CLK_CALRN_FCH F27 AD12
+1.1V_CKVDD CLK_CALRN CBE3# 20MIL 20MIL
FRAME# AG10
AK9 20MIL R102 499/F_4 +3VRTC_1 R99 10/F_4 +3VRTC 1 2
DEVSEL#
SI , change to 22Ω & 47Ω TP97 G30 PCIE_RCLKP IRDY# AL10
for Rise/Fall time issue G28 AF10 D3

+VCCRTC_2
PCIE_RCLKN TRDY# RB500V-40
PAR AE10
[4] CLK_DP_P R26 DISP_CLKP STOP# AH1
T26 AM9 C163
[4] CLK_DP_N DISP_CLKN PERR#
AH8 PCI_SERR# [26] 1U/6.3V_4 20MIL
SERR#
TP98 H33 DISP2_CLKP REQ0# AG15
H31 AG13 C746 100P/50V_4
DISP2_CLKN REQ1#/GPIO40 R97
REQ2#/CLK_REQ8#/GPIO41 AF15
[4] CLK_APU_P T24 APU_CLKP REQ3#/CLK_REQ5#/GPIO42 AM17 TP118
[4] CLK_APU_N T23 AD16 470/F_4
APU_CLKN GNT0#
GNT1#/GPO44 AD13 TP115
4 3 CLK_VGA_P_FCH J30 AD21
[14] CLK_VGA_P SLT_GFX_CLKP GNT2#/SD_LED/GPO45 TP61
CLK_VGA_N_FCH
[14] CLK_VGA_N RP5
2 1
0_4P2R_4
K29 SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46 AK17
AD19 CLKRUN#
TP116 20MIL

+BAT
CLKRUN# CLKRUN# [26]
4 3 CLK_WLAN_P_FCH H27 AH9
[24] CLK_WLAN_P GPP_CLK0P LOCK# TP107
2 1 CLK_WLAN_N_FCH H28
[24] CLK_WLAN_N RP4 0_4P2R_4 GPP_CLK0N
INTE#/GPIO32 AF18 TP120 +BAT

1
[22] CLK_PCIE_CARD_P 2 1CLK_PCIE_CARD_P_FCH J27 GPP_CLK1P INTF#/GPIO33 AE18 TRAVIS_EN#
TP111
[22] CLK_PCIE_CARD_N 4 3CLK_PCIE_CARD_N_FCH K26 GPP_CLK1N INTG#/GPIO34 AC16 TS_INTG#
TS_INTG# [24] CN14
B AD18 ACCEL_INTH# Add G-sensor signal BAT_CONN B
INTH#/GPIO35 ACCEL_INTH# [23]
RP6 0_4P2R_4 F33

2
TP96 GPP_CLK2P
F31 LPC_CLK0
GPP_CLK2N LPC_CLK0 [10]
LPC_CLK1 LPC_CLK1 [10] CLK_33M_KBC [26]
Note: CLK_FCH_SRCP/N is 100MHZ SSC TP92 E33 GPP_CLK3P
E31 B25 R336 22_4 C654 15P/50V_4
GPP_CLK3N LPCCLK0 R337 33_4 C642 15P/50V_4
Note: CLK_PCIE_TRAVISP/N is 100MHZ non-SSC LPCCLK1 D25
M23 D27 LAD0 LAD0 [24,26] R340 *0_4
GPP_CLK4P LAD0 CLKGEN_RTC_X1 [24]
Note: CLK_DP_NSSCP/N is 100MHZ non-SSC M24 C28 LAD1
GPP_CLK4N LAD1 LAD1 [24,26] CLK_33M_DEBUG [24]
LPC
GENERATOR

A26 LAD2
Note: CLK_APU_HCLKP/N is 100MHZ SSC LAD2 LAD2 [24,26]
M27 A29 LAD3 LAD3 [24,26] 6/21/2012 for EMI
TP39 GPP_CLK5P LAD3
Note: CLK_PCIE_VGAP/N is 100MHZ SSC M26 A31 LFRAME# 32K_X1 C671 18P/50V_4
CLOCK

GPP_CLK5N LFRAME# LFRAME# [24,26]


Note: GPP_CLK(0:8)P/N is 100MHZ SSC capable B27 LDRQ#0
LDRQ0# TP30

1
2
N25 AE27 LDRQ#1
TP40 GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 TP48
N26 AE19 SERIRQ FCH PROCHOT#--- (input 0.8V threshold )
GPP_CLK6N SERIRQ/GPIO48 SERIRQ [26]
R346 Y5
When it isasserted, it can generate SCI or 20M_4 32.768KHZ
TP41 R23 GPP_CLK7P
R24 SMI to OS/BIOS

4
3
GPP_CLK7N DMAACTIVE_L 32K_X2 C685 18P/50V_4
DMA_ACTIVE# G25 DMAACTIVE_L [4]
[21] CLK_PCIE_LANP 2 1 CLK_PCIE_LANP_FCH N27 E28 FCH_PROCHOT# FCH_PROCHOT# [4]
CLK_PCIE_LANN_FCH GPP_CLK8P PROCHOT# APU_PWRGD_R R351 *0_4/S USE GROUND GUARD FOR 32K_X1 AND 32K_X2
4 3 R27 E26
APU

[21] CLK_PCIE_LANN GPP_CLK8N APU_PG APU_PWRGD [2,4]


G26 APU_STOP#
LDT_STP# TP32
RP3 0_4P2R_4 F26 APU_RST# APU_RST# [2,4] LDT_STP# let is NC from schematic recommend
APU_RST#
J26 14M_25M_48M_OSC
R350 *0_4
[24] PCH_XTAL25_IN
TP88 G2 32K_X1 C354 0.022U/16V_4
32K_X1
C686 27P/50V_4 25M_X1 C31 G4 32K_X2
25M_X1 32K_X2
S5_CORE_EN is necessary to connect enable
H7 S5_CORE_EN pin of +3VPCU/+5VPCU regulator for S5+
A S5_CORE_EN TP38 A
Y4 R343 F1 CLK_RTC
RTCCLK CLK_RTC [10] mode implementation
25MHZ 25M_X2 C33 F3 INTRUDER_ALERT#
25M_X2 INTRUDER_ALERT# TP37
1M/F_4 E6 VDDBT_RTC_G R145 0_4
PLUS

VDDBT_RTC_G +3V_RTC
TP87
20MIL
S5

C657 27P/50V_4
Hudson-M3-A14
1

G1
*SHORT_ PAD1 C237
INTRUDER_ALERT# Left not connected PROJECT : U56
(FCH has 50-kohm internal pull-up to
0.1U/10V_4
VBAT). Quanta Computer Inc.
2

Size Document Number Rev


Custom 1A
NB5 Hudson-M3 ACPI/PCI/CLOCK
Date: Tuesday, August 07, 2012 Sheet 7 of 39
5 4 3 2 1
5 4 3 2 1

U23D

08
PLACE SATA AC COUPLING U23B

A3
HUDSON-M3 T25
CAPS CLOSE TO HUDSON-M2/M3
VSS_1 Part 5 of 5 VSS_65
A33
B7
VSS_2
VSS_3
VSS_66
VSS_67
T27
U6 [25] SATA_TXP0
SATA_TXP0 AK19 SATA_TX0P
HUDSON-M3 Part 2 of 5
SD_CLK/SCLK_2/GPIO73 AL14
B13 U14 SATA_TXN0 AM19 AN14
VSS_4 VSS_68 [25] SATA_TXN0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74
D9 U17 AJ12
D13
VSS_5 VSS_69
U20
SATA HDD AL20
SD_CD#/GPIO75
AH12
VSS_6 VSS_70 [25] SATA_RXN0 SATA_RX0N SD_W P/GPIO76
E5 VSS_7 VSS_71 U21 [25] SATA_RXP0 AN20 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 AK13
E12 VSS_8 VSS_72 U30 SD_DATA1/SDATO_2/GPIO78 AM13
E16 U32 SATA_TXP1 AN22 AH15
VSS_9 VSS_73 [25] SATA_TXP1 SATA_TX1P SD_DATA2/GPIO79
E29 V11 SATA_TXN1 AL22 AJ14 Vender Size P/N

CARD
VSS_10 VSS_74 [25] SATA_TXN1 SATA_TX1N SD_DATA3/GPIO80
F7 V16
MINISATA

SD
D VSS_11 VSS_75 D
F9 VSS_12 VSS_76 V18 [25] SATA_RXN1 AH20 SATA_RX1N GBE_COL AC4 AMIC 2M AKE38ZN0801
F11 VSS_13 VSS_77 W4 [25] SATA_RXP1 AJ20 SATA_RX1P GBE_CRS AD3
F13 VSS_14 VSS_78 W6 GBE_MDCK AD9 WINBOND 2M AKE38FP0N01
F16 VSS_15 VSS_79 W 25 AJ22 SATA_TX2P GBE_MDIO W 10
F17 VSS_16 VSS_80 W 28 AH22 SATA_TX2N GBE_RXCLK AB8 Socket DFHS08FS023
F19 VSS_17 VSS_81 Y14 GBE_RXD3 AH7
F23 VSS_18 VSS_82 Y16 AM23 SATA_RX2N GBE_RXD2 AF7
F25 VSS_19 VSS_83 Y18 AK23 SATA_RX2P GBE_RXD1 AE7
F29 VSS_20 VSS_84 AA6 GBE_RXD0 AD7
G6 VSS_21 VSS_85 AA12 AH24 SATA_TX3P GBE_RXCTL/RXDV AG8
G16 AA13 AJ24 AD1

GBE
VSS_22 VSS_86 SATA_TX3N GBE_RXERR

LAN
G32 VSS_23 VSS_87 AA14 GBE_TXCLK AB7
H12 AA16 AN24 AF9 +3VS5
VSS_24 VSS_88 SATA_RX3N GBE_TXD3
H15 VSS_25 VSS_89 AA17 AL24 SATA_RX3P GBE_TXD2 AG6
H29 VSS_26 VSS_90 AA25 GBE_TXD1 AE8
J6 VSS_27 VSS_91 AA28 AL26 SATA_TX4P GBE_TXD0 AD8
GROUND

J9 VSS_28 VSS_92 AA30 AN26 SATA_TX4N GBE_TXCTL/TXEN AB9


J10 AA32 AC2 R427
VSS_29 VSS_93 GBE_PHY_PD 10K/F_4
J13 VSS_30 VSS_94 AB25 AJ26 SATA_RX4N GBE_PHY_RST# AA7
J28 AC6 AH26 W9 GBE_PHY_INTR R167 10K/F_4 +3VS5
VSS_31 VSS_95 SATA_RX4P GBE_PHY_INTR

SERIAL
J32 VSS_32 VSS_96 AC18
K7 AC28 R187 *0_4/S SB_SATA_LED# AN29

ATA
VSS_33 VSS_97 [25] SATA_LED# SATA_TX5P
K16 AD27 AL28 V6 SPI_SI
VSS_34 VSS_98 SATA_TX5N SPI_DI/GPIO164 TP110
K27 AE6 V5 SPI_SO SPI_CS0# *0_4/S R428
VSS_35 VSS_99 SPI_DO/GPIO163 TP109 EC_BIOS_CS# [26]
K28 AE15 AK27 V3 SPI_CLK SPI_CLK *0_4/S R426
VSS_36 VSS_100 SATA_RX5N SPI_CLK/GPIO162 TP113 EC_BIOS_SPI_CLK_I [26]
L6 AE21 AM27 T6 SPI_CS0# SPI_SO *0_4/S R425
VSS_37 VSS_101 SATA_RX5P SPI_CS1#/GPIO165 TP114 EC_BIOS_WR# [26]
L12 AE28 V1 FCH_SPI_WP SPI_SI *0_4/S R429

ROM
VSS_38 VSS_102 ROM_RST#/SPI_W P#/GPIO161 TP104 EC_BIOS_RD# [26]

SPI
L13 VSS_39 VSS_103 AF8 AL29 NC6
L15 VSS_40 VSS_104 AF12 AN31 NC7
L16 VSS_41 VSS_105 AF16 VGA_RED L30
C L21 AF33 PV , change AL31 C
VSS_42 VSS_106 NC8
M13 VSS_43 VSS_107 AG30 to short pad AL33 NC9 VGA_GREEN L32
M16 VSS_44 VSS_108 AG32
M21 VSS_45 VSS_109 AH5 AH33 NC10 VGA_BLUE M29
M25 VSS_46 VSS_110 AH11 AH31 NC11
N6 VSS_47 VSS_111 AH18 PLACE SATA_CAL RES VERY
N11 AH19 AJ33 M28
N13
VSS_48 VSS_112
AH21 CLOSE TO BALL OF AJ31
NC12 VGA_HSYNC/GPO68
N30
VSS_49 VSS_113 NC13 VGA_VSYNC/GPO69

DAC
VGA
N23 VSS_50 VSS_114 AH23 HUDSON-M2/M3
N24 VSS_51 VSS_115 AH25 VGA_DDC_SDA/GPO70 M33
P12 VSS_52 VSS_116 AH27 VGA_DDC_SCL/GPO71 N32
P18 AJ18 R181 1K/F_4 SATA_CALRP AF28
VSS_53 VSS_117 R177 931/F_4 SATA_CALRN SATA_CALRP
P20 VSS_54 VSS_118 AJ28 +1.1V_AVDD_SATA AF27 SATA_CALRN VGA_DAC_RSET K31 TP99
P21 VSS_55 VSS_119 AJ29
P31 VSS_56 VSS_120 AK21 4/19 For Comal. AUX_VGA_CH_P V28
P33 AK25 +3V R194 *220/F_6 SB_SATA_LED# AD22 V29
VSS_57 VSS_121 SATA_ACT#/GPIO67 AUX_VGA_CH_N
R4 VSS_58 VSS_122 AL18
R11 VSS_59 VSS_123 AM21 AUXCAL U28 TP102
R25 VSS_60 VSS_124 AM25 AF21 SATA_X1
R28 VSS_61 VSS_125 AN1 ML_VGA_L0P T31
T11 VSS_62 VSS_126 AN18 Integrated Clock Mode: ML_VGA_L0N T33
T16 VSS_63 VSS_127 AN28 Leave unconnected. ML_VGA_L1P T29
T18 VSS_64 VSS_128 AN33 ML_VGA_L1N T28
ML_VGA_L2P R32
N8 VSSAN_HW M VSSPL_DAC T21 AG21 SATA_X2 ML_VGA_L2N R30
VSSAN_DAC L28 ML_VGA_L3P P29
K25 K33 P28

MAINLINK
VSSXL VSSANQ_DAC ML_VGA_L3N
VSSIO_DAC N28
H25 VSSPL_SYS GPIO52 internal pull Hi 8.2K to +3V ML_VGA_HPD/GPIO229 C29 TP33

VGA
EFUSE R6 GPIO53 internal pull Hi 8.2K to +3V
B RF_OFF# SIDE_PORT_ID0 B
GPIO54 internal pull Hi 8.2K to +3V [24] RF_OFF# AH16 FANOUT0/GPIO52 VIN0/GPIO175 N2
Hudson-M3-A14 GPIO56 internal pull Hi 8.2K to +3V BT_OFF# AM15 M3 SIDE_PORT_ID1
TP105 FANOUT1/GPIO53 VIN1/GPIO176
GPIO57 internal pull Hi 8.2K to +3V BT_COMBO_EN# AJ16 L2 SIDE_PORT_ID2
TP63 FANOUT2/GPIO54 VIN2/SDATI_1/GPIO177
GPIO58 internal pull Hi 8.2K to +3V HW N4 BOARD_ID0
MONITOR VIN3/SDATO_1/GPIO178 BOARD_ID1
AK15 FANIN0/GPIO56 VIN4/SLOAD_1/GPIO179 P1
AN16 P3 BOARD_ID2
[25] ACC_LED# FANIN1/GPIO57 VIN5/SCLK_1/GPIO180
AL16 M1 BOARD_ID3
LCD_BK FANIN2/GPIO58 VIN6/GBE_STAT3/GPIO181 BOARD_ID4
ID4 ID3 ID2 ID1 ID0 CONFIG 31- Level BOM Item [27] LCD_BK VIN7/GBE_LED3/GPIO182 M5
TEMPIN0 K6
TEMPIN1 TEMPIN0/GPIO171
K5 TEMPIN1/GPIO172 NC1 AG16
0 0 0 0 0 UMA 1 TEMPIN2 K3 AH10 VIN ( 0 - 7 )
TEMPIN3 TEMPIN2/GPIO173 NC2
M6 TEMPIN3/TALERT#/GPIO174 NC3 A28 Voltage Monitor Not Implemented
NC4 G27 10-KΩ 5% pull-up to +3VS5
0 0 0 1 0 2 NC5 L4 or 10-KΩ 5% pull-down

0 0 1 0 0 3 Hudson-M3-A14
R142 R143 R358 R144
10K/F_4 10K/F_4 10K/F_4 10K/F_4 TEMP( 0 - 3 )
0 0 1 1 0 4 Temp Monitor Not Implemented +3VS5 R380 10K/F_4 BOARD_ID0 R381 *10K/F_4
10-KΩ 5% pull-up to +3VS5
or 10-KΩ 5% pull-down
0 1 0 1 0 5 R384 *10K/F_4 BOARD_ID1 R385 10K/F_4

0 1 1 1 0 6 R387 *10K/F_4 BOARD_ID2 R388 10K/F_4

SIDE_PORT_ID2 SIDE_PORT_ID1 SIDE_PORT_ID0


1 0 0 1 0 7 R366 *10K/F_4 BOARD_ID3 R367 10K/F_4

A 0 0 0 Samsung A
1 0 1 1 0 8 R370 *10K/F_4 BOARD_ID4 R371 10K/F_4

0 0 0 0 1 SG / Muxless 9 0 0 1 Hynix
R374 10K/F_4 SIDE_PORT_ID0 R375 *10K/F_4

0 0 1 0 1 10
PROJECT : U56
0 1 0 NC R363 10K/F_4 SIDE_PORT_ID1 R364 *10K/F_4 Quanta Computer Inc.
1 0 0 1 1 11
R359 *10K/F_4 SIDE_PORT_ID2 R360 10K/F_4 Size Document Number Rev
0 1 1 no supprot side port Custom 1A
1 0 1 1 1 12 NB5 Hudson-M3 SATA/HWM/SPI
Date: Tuesday, August 07, 2012 Sheet 8 of 39
5 4 3 2 1
5 4 3 2 1

+3V R184 *0_8/S


+3.3V_VDDIO
VDDQ--3.3V I/O power 102mA
PLACE ALL THE DECOUPLING CAPS ON
THIS SHEET CLOSE TO SB AS POSSIBLE.
U23C 1007mA for M3
902mA for M2 VDDCR-- S/B CORE power
09
AB17 HUDSON-M3
VDDIO_33_PCIGP_1
Part 3 of 5
VDDCR_11_1 T14 TRACE WIDTH >=100mil +1.1V
C306 C312 C314 C308 C307 AB18 T17
0.1U/10V_4 22U/6.3VS_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDIO_33_PCIGP_2 VDDCR_11_2
AE9 VDDIO_33_PCIGP_3 VDDCR_11_3 T20
AD10 U16 C281 C269 C283 C276 C270
VDDIO_33_PCIGP_4 VDDCR_11_4

PCI/GPIO I/O
AG7 U18 0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 1U/6.3V_4 10U/6.3V_6
VDDIO_33_PCIGP_5 VDDCR_11_5

CORE
AC13 VDDIO_33_PCIGP_6 VDDCR_11_6 V14
D L33 TRACE WIDTH >=15mil AB12 V17 D

S0
+3V VDDIO_33_PCIGP_7 VDDCR_11_7
AB13 VDDIO_33_PCIGP_8 VDDCR_11_8 V20
PBY160808T-221Y-N(220,2A) AB14 Y17 +1.1V_CKVDD
C340 C352 +VDDPL_3.3V VDDIO_33_PCIGP_9 VDDCR_11_9
AB16 VDDIO_33_PCIGP_10
2.2U/6.3V_4 *0.1U/10V_4 47mA 340mA VDDAN_11_CLK-- Internal clock
H24 VDDPL_33_SYS VDDAN_11_CLK_1 H26 Generator I/O power
V22 J25 TRACE WIDTH >=30mil L25 +1.1V
R165 *0_4/S VDDPL_33_DAC VDDAN_11_CLK_2 BLM18PG181SN1D(180,1.5A)_6
U22 VDDPL_33_ML VDDAN_11_CLK_3 K24
+3V L34 TRACE WIDTH >=15mil T22 L22
+FCH_VDDPL_33_SSUSB_S VDDAN_33_DAC VDDAN_11_CLK_4
11mA L18 VDDPL_33_SSUSB_S VDDAN_11_CLK_5 M22 C258 C267 C246 C253 C238

CLKGEN
PBY160808T-221Y-N(220,2A) +FCH_VDDPL_33_SUSB_S 14mA D7 VDDPL_33_USB_S VDDAN_11_CLK_6 N21 1U/6.3V_4 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 22U/6.3VS_8
C353 C341 +FCH_VDDPL_33_PCIE 11mA AH29 N22
+FCH_VDDPL_33_SATA VDDPL_33_PCIE VDDAN_11_CLK_7
2.2U/6.3V_4 *0.1U/10V_4 12mA AG28 P22

I/O
VDDPL_33_SATA VDDAN_11_CLK_8 +1.1V_PCIE_VDDR VDDPL_11_SYS_S : System Clock Gen
VDDAN_11_ML -- UMI 1.1V analog power VDDAN_11_PCIE --PCIE/UMI analog power TRACE WIDTH >=100mil
+LDO_CAP M31
1088mA PLLs analog power
AB24 L28 +1.1V
LDO_CAP VDDAN_11_PCIE_1 BLM18PG181SN1D(180,1.5A)_6
VDDAN_11_PCIE_2 Y21
C711 *2.2U/6.3V_4 V21 AE25 +VDDPL_1.1V
VDDPL_11_DAC VDDAN_11_PCIE_3 C300 C293 C327 C305 C279
VDDAN_11_PCIE_4 AD24
0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 1U/6.3V_4 22U/6.3VS_8 L27

EXPRESS
Y22 VDDAN_11_ML_1 VDDAN_11_PCIE_5 AB23 +1.1VS5
V23 AA22 PBY160808T-221Y-N(220,2A)
VDDAN_11_ML_2 VDDAN_11_PCIE_6
V24 VDDAN_11_ML_3 VDDAN_11_PCIE_7 AF26

PCI
+1.1V_AVDD_SATA

MAIN
R170 *0_4/S V25 AG27 C255 C244

LINK
VDDAN_11_ML_4 VDDAN_11_PCIE_8 2.2U/6.3V_4 0.1U/10V_4
1337mA VDDAN_11_SATA--SATA PHY analog/IO power TRACE WIDTH >=50mil
+3V +VDDPL_3.3V AB10 AA21 L29
VDDIO_33_GBE_S VDDAN_11_SATA_1 +1.1V
Y20 BLM18PG181SN1D(180,1.5A)_6
VDDAN_11_SATA_4

GBE
AB21

LAN
L23 VDDAN_11_SATA_2 C310 C301 C321 C322 C320
VDDPL_33_USB_S : USB PHY PLL analog power VDDAN_11_SATA_3 AB22 if support USB
PBY160808T-221Y-N(220,2A) AB11 AC22 1U/6.3V_4 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 22U/6.3VS_8
C +3V_AVDD_USB +FCH_VDDPL_33_SUSB_S VDDCR_11_GBE_S_1 VDDAN_11_SATA_5 3.0 wake up C
AA11 AC21

SERIAL
C222 C236 VDDCR_11_GBE_S_2 VDDAN_11_SATA_6 should be
VDDAN_11_SATA_7 AA20

ATA
2.2U/6.3V_4 0.1U/10V_4 L50
VDDAN_11_SATA_8 AA18 change pull hi
PBY160808T-221Y-N(220,2A) AA9 AB20 to S5 power
VDDIO_GBE_S_1 VDDAN_11_SATA_9
AA10 VDDIO_GBE_S_2 VDDAN_11_SATA_10 AC19
C688 C684
2.2U/6.3V_4 1U/6.3V_4

VDDAN_33_USB_S : USB PHY I/O analog power +3V_AVDD_USB VDDIO_33_S-- 3.3v S5 I/O power
59mA
TRACE WIDTH >=50mil 470mA G7 N18 TRACE WIDTH >=20mil +3VS5 if support USB
L20 PBY160808T-221Y-N(220,2A) VDDAN_33_USB_S_1 VDDIO_33_S_1
+3VS5 H8 VDDAN_33_USB_S_2 VDDIO_33_S_2 L19 3.0 wake up
J8 VDDAN_33_USB_S_3 VDDIO_33_S_3 M18
K8 V12 C304 C242 C256 C284 C247 C282 should be
VDDAN_33_USB_S_4 VDDIO_33_S_4

3.3V_S5 I/O
C252 C241 C681 C254 C260 K9 VDDAN_33_USB_S_5 VDDIO_33_S_5 V13 *0.1U/10V_4 2.2U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 change pull hi
0.1U/10V_4 10U/6.3V_6 10U/6.3V_6 1U/6.3V_4 1U/6.3V_4 M9 Y12 to S5 power
VDDAN_33_USB_S_6 VDDIO_33_S_6
VDDAN_11_USB_S : USB PHY PLL analog power M10 VDDAN_33_USB_S_7 VDDIO_33_S_7 Y13
N9 VDDAN_33_USB_S_8 VDDIO_33_S_8 W 11
L49 +FCH_VDDAN_11_USB_S N10

USB
+1.1VS5 VDDAN_33_USB_S_9
M12 VDDAN_33_USB_S_10 5mA VDDXL_33_S-- 25MHZ XTAL IO power
PBY160808T-221Y-N(220,2A) C275 0.1U/10V_4 N12 G24 +VDDXL_3.3V L24 +3VS5
VDDAN_33_USB_S_11 VDDXL_33_S PBY160808T-221Y-N(220,2A)
140mA M11 VDDAN_33_USB_S_12
VDDCR_1.1_S-- 1.1V S5 Core power
C683 2.2U/6.3V_4 187mA
TRACE WIDTH >=20mil U12 N20 +VDDCR_1.1V +1.1VS5 C227 C229
C274 0.1U/10V_4 VDDAN_11_USB_S_1 VDDCR_11_S_1 TRACE WIDTH >=15mil *0.1U/10V_4 2.2U/6.3V_4
U13 VDDAN_11_USB_S_2 VDDCR_11_S_2 M20
VDDCR_11_USB_S : USB PHY core power 42mA 70mA
L48 +FCH_VDDCR_11_USB_S T12 J24 C257 C263
+1.1VS5 VDDCR_11_USB_S_1 VDDPL_11_SYS_S +VDDPL_1.1V
TRACE WIDTH >=15mil T13 1U/6.3V_4 2.2U/6.3V_4
PBY160808T-221Y-N(220,2A) VDDCR_11_USB_S_2
B SI , AMD SR C266 C268 C687 M8 12mA +3VS5
B
0.1U/10V_4 0.1U/10V_4 10U/6.3V_6 VDDAN_33_HW M_S
M3 chipset need tool review P16 VDDAN_11_SSUSB_S_1
to stuff for M14 VDDAN_11_SSUSB_S_2
+FCH_VDD_11_SSUSB_S N14 AA4 26mA +3V C259 C228
support USB3.0 VDDAN_11_SSUSB_S_3 VDDIO_AZ_S Trace width >=20 mil 0.1U/10V_4 2.2U/6.3V_4
+1.1VS5
+FCH_VDDAN_11_SSUSB_S_R
282mA P13 VDDAN_11_SSUSB_S_4
L21 P14 VDDAN_11_SSUSB_S_5 C325
VDDAN_11_SSUSB_S : USB3.0 PHY PLL analog power
PBY160808T-221Y-N(220,2A) N16 VDDCR_11_SSUSB_S_1 USB 2.2U/6.3V_4
424mA N17 VDDCR_11_SSUSB_S_2 SS
+FCH_VDDCR_11_SSUSB_S P17 VDDCR_11_SSUSB_S_3
M17 VDDCR_11_SSUSB_S_4

C209 C215 C213 C195 C240 C250 C264 C262


1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 10U/6.3V_6 1U/6.3V_4 0.1U/10V_4 0.1U/10V_4 POWER

VDDCR_11_SSUSB_S : USB3.0 PHY core power


Hudson-M3-A14

if support
Modem wake
up should be
change pull hi to
S5 power

A A
+3VS5 +FCH_VDDPL_33_SSUSB_S
M3 chipset need
to stuff for
L26
PBY160808T-221Y-N(220,2A) support USB3.0

C243 C245
PROJECT : U56
2.2U/6.3V_6 0.1U/10V_4 Quanta Computer Inc.
Size Document Number Rev
Custom 1A
NB5 Hudson-M3 POWER/GND
Date: Tuesday, August 07, 2012 Sheet 9 of 39
5 4 3 2 1
5 4 3 2 1

STRAPS PINS OVERLAP COMMON PADS WHERE


POSSIBLE FOR DUAL-OP RESISTORS.
DEBUG STRAPS
10
+3V +3VS5 +3VS5 +3VS5

D D
FCH has 15K Internal Pull Up for PCI_AD[27:23]
R430 R345 R131 R341
10K/F_4 10K/F_4 *10K/F_4 10K/F_4
PCI_AD27
[7] PCI_AD27 TP112
PCI_AD26
[7] PCI_AD26 TP108
[7] PCI_CLK1 PCI_CLK1
PCI_AD25 remove reserve pull low resistor
[7] PCI_AD25 TP117
PCI_CLK3
[7] PCI_CLK3
PCI_AD24
reserve test point only.
[7] PCI_AD24 TP50
PCI_CLK4
[7] PCI_CLK4
PCI_AD23
[7] PCI_AD23 TP119
LPC_CLK0
[7] LPC_CLK0

[7] LPC_CLK1 LPC_CLK1

EC_PWM2
[6] EC_PWM2

[7] CLK_RTC CLK_RTC

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

PULL USE PCI DISABLE ILA USE FC USE DEFAULT DISABLE PCI
R431 R419 R424 R344 R127 R347
*10K_4 10K/F_4 10K/F_4 10K/F_4 HIGH PLL AUTORUN PLL PCIE STRAPS MEM BOOT
2.2K_4 *2.2K_4

DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

C C

PULL BYPASS ENABLE ILA BYPASS FC USE EEPROM ENABLE PCI


LOW PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT
REQUIRED STRAPS

-------- PCI_CLK1 -------- PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 CLK_RTC

PULL ALLOW USE non_Fusion AMD internal EC CLKGEN LPC ROM S5 PLUS MODE
HIGH PCIE Gen2 DEBUG CLOCK MODE ENABLED ENABLED ENABLED
-------- --------
STRAP DEFAULT DEFAULT
DEFAULT

PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS MODE


-------- PCIE Gen1 -------- DEBUG CLOCK MODE DISABLED DISABLED DISABLED
LOW
STRAP DEFAULT
DEFAULT DEFAULT DEFAULT

B
FCH PWRGD B

+3VS5

R392
10K/F_4

D19 1 2 RB501V-40
[36] CPU_VRM8380_PG
R393 *0_4/S
FCH_PWRGD [6]
D18 1 2 RB501V-40
[4,26] ECPWROK
C714
*2.2U/6.3V_6

A A

PROJECT : U56
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
NB5 Hudson-M3 STRAP/PWRGD
Date: Tuesday, August 07, 2012 Sheet 10 of 39
5 4 3 2 1
5 4 3 2 1

11
+3V 0_4 R81 +TRAVIS3.3V_A
D D
C66 C68 C67
10U/6.3V_6 0.1U/10V_4 0.1U/10V_4

+3V 0_4 R50 +TRAVIS3.3V

C48 C53 C56


10U/6.3V_6 0.1U/10V_4 0.1U/10V_4

+1.2V R321 *0_8 +TRAVIS1.2V

[27] PCH_EDIDDATA
+TRAVIS1.2V
[27] PCH_EDIDCLK
C57
SCA_SDA

SCA_SCL
0.1U/10V_4
FCH_LVDS_HPD R319 0_4 DPRX_HPD
[4] FCH_LVDS_HPD
R316 1K/F_4
C PCH_LA_DATAN0 [27] C
R318
PCH_LA_DATAP0 [27]
100K/F_4

CMC

33

32

31

30

29

28

27

26

25
U16
SCA_SCL pull high => EEPROM mode

TXO0-
SPI_CEB/IRQB/MIICSCL

SPI_SI/SCLK/MIICSCL

TXO0+
SPI_SO/SCSB/MIICSDA

SPI_CK/SDIO/MIICSDA

VCCK
GND

HPD
R80 *1M/F_4
C584 0.1U/10V_4 ANX_eDP_AUXN
SCA_SDA pull low = > EEPROM Free mode
[4] INT_eDP_AUXN 1 AUX-CH_N TXO1- 24 PCH_LA_DATAN1 [27]
C585 0.1U/10V_4 ANX_eDP_AUXP 2 23
[4] INT_eDP_AUXP AUX-CH_P TXO1+ PCH_LA_DATAP1 [27]
R79 *1M/F_4
+3V
+TRAVIS3.3V_A 3 DP_V33 TXO2- 22 PCH_LA_DATAN2 [27]
Address=0xA8
4 21 +TRAVIS3.3V +TRAVIS3.3V +TRAVIS3.3V
DP_GND TXO2+ PCH_LA_DATAP2 [27]
INT_eDP_TXP0 C586 0.1U/10V_4 LANE0P 5 20
[4] INT_eDP_TXP0 LANE0P TXOC- PCH_LA_CLK# [27]
INT_eDP_TXN0 C587 0.1U/10V_4 LANE0N 6 RTD2132S 19 R310 R303
[4] INT_eDP_TXN0 LANE0N TXOC+ PCH_LA_CLK [27]
*4.7K/F_4 4.7K/F_4
+TRAVIS1.2V 7 18 +TRAVIS3.3V U17 C610
DP_V12 PVCC *0.1U/10V_4
8 7
SWR_VCCK

R320 VCC WP

Panel_VCC
SWR_VDD
8 17 C576 SCA_SDA 5 3
CIICSDA1

PWMOUT
CIICSCL1

DP_REXT BL_EN SDA A2


SWR_LX

C69 0.1U/10V_4 SCA_SCL 6 2

PWMIN
12K/F_4 SCL A1
0.1U/10V_4 4 1
GND A0
R305 *SGT-M24C64-WMN6TP
Close to Pin8
PCH_LVDS_BLON [27]
RTD2132S-CG 4.7K/F_4
9

10

11

12

13

14

15

16

B B

+TRAVIS3.3V 4.7K_4 R70 CSCL1


ANX_PWM
4.7K_4 R61 CSDA1
PCH_DISP_ON [27]
+TRAVIS1.2V PCH_DPST_PWM [27]
L43 +3V +1.5V
4.7UH/850mA/TLPC3010C-4R7M
+TRAVIS1.2V +TRAVIS3.3V
R85 R325
10K/F_4 2.2k_4
C572 C564 C531 C544 ANX_PWM

2
0.1U/10V_4 22U/6.3V_8 22U/6.3V_8 0.1U/10V_4
R84 Q15
3 1 APU_BLPWM [4]
*0_4 MMBT3904

Q16A 2N7002KDW
PWM_VADJ [26]
CSCL1 4 3 CSCL1_R *0_4 R90
SCL1 [6,25]

0_4 R89
MBCLK2 [4,23,26]
5

+3V Dual
2

CSDA1 1 6 CSDA1_R *0_4 R83


A SDA1 [6,25] A

Q16B 2N7002KDW 0_4 R88


MBDATA2 [4,23,26]

PROJECT : U56
EE PROM R3054,R3056 Quanta Computer Inc.
EC OPTION R3055,R3057 Size
Custom
Document Number Rev
1A
RTD2132S
NB5 Date: Thursday, August 09, 2012 Sheet 11 of 39
5 4 3 2 1
5 4 3 2 1

[3] M_A_A[15:0] M_A_A0


M_A_A1
M_A_A2
M_A_A3
98
97
96
95
JDIM1A
A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
17
M_A_DQ0
M_A_DQ4
M_A_DQ7
M_A_DQ3
M_A_DQ[63:0] [3]
2.48A +1.5VSUS

75
76
81
JDIM1B
VDD1
VDD2
VSS16
VSS17
44
48
49
12
M_A_A4 A3 DQ3 M_A_DQ1 VDD3 VSS18
92 A4 DQ4 4 82 VDD4 VSS19 54
M_A_A5 91 6 M_A_DQ5 87 55
M_A_A6 A5 DQ5 M_A_DQ2 VDD5 VSS20
90 A6 DQ6 16 88 VDD6 VSS21 60
M_A_A7 86 18 M_A_DQ6 93 61
M_A_A8 A7 DQ7 M_A_DQ13 VDD7 VSS22
89 A8 DQ8 21 94 VDD8 VSS23 65
M_A_A9 85 23 M_A_DQ9 99 66
D M_A_A10 A9 DQ9 M_A_DQ14 VDD9 VSS24 D
107 A10/AP DQ10 33 100 VDD10 VSS25 71
M_A_A11 84 35 M_A_DQ10 105 72
M_A_A12 A11 DQ11 M_A_DQ12 VDD11 VSS26
83 A12/BC# DQ12 22 106 VDD12 VSS27 127

PC2100 DDR3 SDRAM SO-DIMM


M_A_A13 119 24 M_A_DQ8 111 128
M_A_A14 A13 DQ13 M_A_DQ11 VDD13 VSS28
80 A14 DQ14 34 112 VDD14 VSS29 133
M_A_A15 78 36 M_A_DQ15 117 134
A15 DQ15 M_A_DQ21 VDD15 VSS30
DQ16 39 118 VDD16 VSS31 138

PC2100 DDR3 SDRAM SO-DIMM


109 41 M_A_DQ17 123 139
[3] M_A_BS#0 BA0 DQ17 VDD17 VSS32
108 51 M_A_DQ19 124 144
[3] M_A_BS#1 BA1 DQ18 VDD18 VSS33
79 53 M_A_DQ18 145
[3] M_A_BS#2 BA2 DQ19 VSS34
114 40 M_A_DQ20 199 150
[3] M_A_CS#0 S0# DQ20 +3V VDDSPD VSS35
121 42 M_A_DQ16 151
[3] M_A_CS#1 S1# DQ21 M_A_DQ23 VSS36
[3] M_A_CLKP0 101 CK0 DQ22 50 77 NC1 VSS37 155
103 52 M_A_DQ22 122 156
[3] M_A_CLKN0 CK0# DQ23 NC2 VSS38
102 57 M_A_DQ25 125 161
[3] M_A_CLKP1 CK1 DQ24 M_A_DQ24 NCTEST VSS39
[3] M_A_CLKN1 104 CK1# DQ25 59 VSS40 162
73 67 M_A_DQ30 [3] M_A_EVENT# 198 167
[3] M_A_CKE0 CKE0 DQ26 M_A_DQ26 EVENT# VSS41
[3] M_A_CKE1 74 CKE1 DQ27 69 [3] M_A_RST# 30 RESET# VSS42 168
115 56 M_A_DQ28 172
[3] M_A_CAS# CAS# DQ28 VSS43
110 58 M_A_DQ29 173
[3] M_A_RAS# RAS# DQ29 M_A_DQ31 +VREF_DQ0 VSS44
113 68 +VREF_DQ R223 *0_6/S 1 178
[3] M_A_WE# W E# DQ30 VREF_DQ VSS45
DIMM0_SA0 197 70 M_A_DQ27 +VREF_CA0 +VREF_CA0 126 179
DIMM0_SA1 SA0 DQ31 M_A_DQ36 VREF_CA VSS46
201 SA1 DQ32 129 VSS47 184
[6,13] SMB_RUN_CLK SMB_RUN_CLK 202 131 M_A_DQ37 185
SMB_RUN_DAT SCL DQ33 M_A_DQ34 VSS48
[6,13] SMB_RUN_DAT 200 SDA DQ34 141 2 VSS1 VSS49 189
143 M_A_DQ38 3 190
DQ35 M_A_DQ32 VSS2 VSS50
[3] M_A_ODT0 116 ODT0 DQ36 130 8 VSS3 VSS51 195
M_A_DQ33

(204P)
[3] M_A_DM[7..0] [3] M_A_ODT1 120 ODT1 DQ37 132 9 VSS4 VSS52 196
140 M_A_DQ35 13
M_A_DM0 DQ38 M_A_DQ39 VSS5
11 DM0 DQ39 142 14 VSS6
C M_A_DM1 28 147 M_A_DQ41 19 C
M_A_DM2 DM1 DQ40 M_A_DQ45 VSS7
46 DM2 DQ41 149 20 VSS8
M_A_DM3 M_A_DQ47

(204P)
63 DM3 DQ42 157 25 VSS9
M_A_DM4 136 159 M_A_DQ46 26 203
DM4 DQ43 VSS10 VTT1 +0.75V_DDR_VTT
M_A_DM5 153 146 M_A_DQ40 31 204
M_A_DM6 DM5 DQ44 M_A_DQ44 VSS11 VTT2
170 DM6 DQ45 148 32 VSS12
M_A_DM7 187 158 M_A_DQ42 37 205
DM7 DQ46 M_A_DQ43 VSS13 GND
[3] M_A_DQSP[7:0] DQ47 160 38 VSS14 GND 206
M_A_DQSP0 12 163 M_A_DQ49 43 207
M_A_DQSP1 DQS0 DQ48 M_A_DQ48 VSS15 GND
29 DQS1 DQ49 165 GND 208
M_A_DQSP2 47 175 M_A_DQ54
M_A_DQSP3 DQS2 DQ50 M_A_DQ50 DDR3-DIMM1_H=4.0_RVS
64 DQS3 DQ51 177
M_A_DQSP4 137 164 M_A_DQ53 ddr-ddrrk-20401-tp4b-204p-ruv
M_A_DQSP5 DQS4 DQ52 M_A_DQ52 DGMK4000361
154 DQS5 DQ53 166
M_A_DQSP6 171 174 M_A_DQ55 SOCKET DDR3 SODIMM(204P,H4.0,RVS)QBCON
M_A_DQSP7 DQS6 DQ54 M_A_DQ51
[3] M_A_DQSN[7:0] 188 DQS7 DQ55 176
M_A_DQSN0 10 181 M_A_DQ61
M_A_DQSN1 DQS#0 DQ56 M_A_DQ60
27 DQS#1 DQ57 183
M_A_DQSN2 45 191 M_A_DQ59
M_A_DQSN3 DQS#2 DQ58 M_A_DQ63
62 DQS#3 DQ59 193
M_A_DQSN4 135 180 M_A_DQ56
M_A_DQSN5 DQS#4 DQ60 M_A_DQ57
152 DQS#5 DQ61 182
M_A_DQSN6 169 192 M_A_DQ62
M_A_DQSN7 DQS#6 DQ62 M_A_DQ58
186 DQS#7 DQ63 194

DDR3-DIMM1_H=4.0_RVS
ddr-ddrrk-20401-tp4b-204p-ruv
DGMK4000361
SOCKET DDR3 SODIMM(204P,H4.0,RVS)QBCON [2,4,6,8,9,10,11,13,14,20,21,22,23,24,25,26,27,33,34,35,38] +3V
B [2,3,4,5,13,32,34,38] +1.5VSUS B
[13,32] +0.75V_DDR_VTT

Place these Caps near So-Dimm0.


For EMI RESERVE +VREF_CA0
+1.5VSUS +0.75V_DDR_VTT 6/21/2012 for EMI
+1.5VSUS Reserved for AMD suggest
C488 1U/6.3V_4 C455 1U/6.3V_4
C491 120P/50V_4 R228 *0_4/S +1.5VSUS
DDR_VTTREF [13,32]
C465 1U/6.3V_4 C459 1U/6.3V_4
C492 120P/50V_4
C467 1U/6.3V_4 C472 1U/6.3V_4
C396 120P/50V_4 R232 +VREF_DQ
C496 1U/6.3V_4 C476 1U/6.3V_4
C388 120P/50V_4 1K/F_4
C466 10U/6.3VS_6 C482 10U/6.3VS_6
C400 120P/50V_4
C460 10U/6.3VS_6 C486 *10U/6.3V_6 R230 *0_4/S +VREF_DQ
C490 120P/50V_4
C463 10U/6.3VS_6 +VREF_DQ0
C712 120P/50V_4 R229
C495 10U/6.3VS_6 C423 0.1U/10V_4
EC14 180P/50V_4 1K/F_4
C470 10U/6.3VS_6
C427 1000P/50V_4
C461 10U/6.3VS_6

A C489 *10U/6.3V_6 +0.75V_DDR_VTT A


SI , change to 1000P
C487 10U/6.3V_6 +VREF_CA0 C480 *120P/50V_4
to meet ref design
C494 10U/6.3V_6 C479 120P/50V_4
C453 0.1U/10V_4
PROJECT : U56
C452 1000P/50V_4 Quanta Computer Inc.
C451 *0.047U/10V_4 Size Document Number Rev
Custom 1A
System Memory 1/2 (5.2H)
NB5 Date: Wednesday, August 08, 2012 Sheet 12of 39
5 4 3 2 1
5 4 3 2 1

[3] M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
98
97
96
JDIM2A
A0
A1
DQ0
DQ1
5
7
15
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ[63:0] [3]
+1.5VSUS

75
76
81
JDIM2B
VDD1
VDD2
VSS16
VSS17
44
48
49
13
M_B_A3 A2 DQ2 M_B_DQ2 VDD3 VSS18
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ0 87 55
M_B_A5 A4 DQ4 M_B_DQ1 VDD5 VSS20
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
M_B_A7 A6 DQ6 M_B_DQ7 VDD7 VSS22
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 M_B_DQ9
D M_B_A9
89
85
A8 DQ8 21
23 M_B_DQ13
2.48A 99
100
VDD9 VSS24 66
71 D
M_B_A10 A9 DQ9 M_B_DQ14 VDD10 VSS25
107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 84 35 M_B_DQ10 106 127
A11 DQ11 VDD12 VSS27

PC2100 DDR3 SDRAM SO-DIMM


M_B_A12 83 22 M_B_DQ8 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ12 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ11 117 134
M_B_A15 A14 DQ14 M_B_DQ15 VDD15 VSS30
78 A15 DQ15 36 118 VDD16 VSS31 138
39 M_B_DQ20 123 139
DQ16 VDD17 VSS32

PC2100 DDR3 SDRAM SO-DIMM


109 41 M_B_DQ21 124 144
[3] M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ18 145
[3] M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ22 199 150
[3] M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ17 151
[3] M_B_CS#0 S0# DQ20 M_B_DQ16 VSS36
[3] M_B_CS#1 121 S1# DQ21 42 77 NC1 VSS37 155
101 50 M_B_DQ19 122 156
[3] M_B_CLKP0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 125 161
[3] M_B_CLKN0 CK0# DQ23 M_B_DQ25 NCTEST VSS39
[3] M_B_CLKP1 102 CK1 DQ24 57 VSS40 162
104 59 M_B_DQ29 [3,24] M_B_EVENT# M_B_EVENT# 198 167
[3] M_B_CLKN1 CK1# DQ25 M_B_DQ27 EVENT# VSS41
[3] M_B_CKE0 73 CKE0 DQ26 67 [3] M_B_RST# 30 RESET# VSS42 168
74 69 M_B_DQ26 172
[3] M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ28 173
[3] M_B_CAS# CAS# DQ28 M_B_DQ24 +VREF_DQ1 VSS44
110 58 +VREF_DQ R224 *0_6/S 1 178
[3] M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ31 +VREF_CA1 +VREF_CA1 126 179
[3] M_B_WE# W E# DQ30 VREF_CA VSS46
R231 4.7K_4 DIMM1_SA0 197 70 M_B_DQ30 184
+3V SA0 DQ31 VSS47
DIMM1_SA1 201 129 M_B_DQ36 185
SA1 DQ32 M_B_DQ37 VSS48
[6,12] SMB_RUN_CLK 202 SCL DQ33 131 2 VSS1 VSS49 189
[6,12] SMB_RUN_DAT 200 141 M_B_DQ35 3 190
SDA DQ34 M_B_DQ34 VSS2 VSS50
DQ35 143 8 VSS3 VSS51 195
M_B_DQ33

(204P)
[3] M_B_ODT0 116 ODT0 DQ36 130 9 VSS4 VSS52 196
[3] M_B_ODT1 120 132 M_B_DQ32 13
[3] M_B_DM[7..0] ODT1 DQ37 VSS5
140 M_B_DQ39 14
C M_B_DM0 DQ38 M_B_DQ38 VSS6 C
11 DM0 DQ39 142 19 VSS7
M_B_DM1 28 147 M_B_DQ44 20
M_B_DM2 DM1 DQ40 M_B_DQ40 VSS8
46 DM2 DQ41 149 25 VSS9
M_B_DM3 M_B_DQ42

(204P)
63 DM3 DQ42 157 26 VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 31 204
M_B_DM5 DM4 DQ43 M_B_DQ45 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 170 148 M_B_DQ41 37 205
M_B_DM7 DM6 DQ45 M_B_DQ46 VSS13 GND
187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ47 43 207
[3] M_B_DQSP[7:0] DQ47 VSS15 GND
M_B_DQSP0 12 163 M_B_DQ49 208
M_B_DQSP1 DQS0 DQ48 M_B_DQ48 GND
29 DQS1 DQ49 165
M_B_DQSP2 47 175 M_B_DQ54 DDR3-DIMM0_H=4.0_STD
M_B_DQSP3 DQS2 DQ50 M_B_DQ55 ddr-ddrsk-20401-tp4b-204p-ldv
64 DQS3 DQ51 177
M_B_DQSP4 137 164 M_B_DQ52 DGMK4000325
M_B_DQSP5 DQS4 DQ52 M_B_DQ53 SOCKET DDR3 SODIMM(204P,H4.0,STD)QBCON
154 DQS5 DQ53 166
M_B_DQSP6 171 174 M_B_DQ50
M_B_DQSP7 DQS6 DQ54 M_B_DQ51
[3] M_B_DQSN[7:0] 188 DQS7 DQ55 176
M_B_DQSN0 10 181 M_B_DQ61
M_B_DQSN1 DQS#0 DQ56 M_B_DQ56
27 DQS#1 DQ57 183
M_B_DQSN2 45 191 M_B_DQ63
M_B_DQSN3 DQS#2 DQ58 M_B_DQ62
62 DQS#3 DQ59 193
M_B_DQSN4 135 180 M_B_DQ57
M_B_DQSN5 DQS#4 DQ60 M_B_DQ60
152 DQS#5 DQ61 182
M_B_DQSN6 169 192 M_B_DQ58
M_B_DQSN7 DQS#6 DQ62 M_B_DQ59
186 DQS#7 DQ63 194

DDR3-DIMM0_H=4.0_STD
ddr-ddrsk-20401-tp4b-204p-ldv
DGMK4000325
B SOCKET DDR3 SODIMM(204P,H4.0,STD)QBCON [2,4,6,8,9,10,11,12,14,20,21,22,23,24,25,26,27,33,34,35,38] +3V B
[2,3,4,5,12,32,34,38] +1.5VSUS
[12,32] +0.75V_DDR_VTT

Place these Caps near So-Dimm1.


For EMI RESERVE +VREF_CA1
6/21/2012 for EMI
+1.5VSUS +0.75V_DDR_VTT +1.5VSUS

C449 1U/6.3V_4 C419 1U/6.3V_4 C478 120P/50V_4 R233 *0_4/S


DDR_VTTREF [12,32]
C458 1U/6.3V_4 C417 1U/6.3V_4 C748 120P/50V_4

C416 1U/6.3V_4 C440 1U/6.3V_4 C497 120P/50V_4

C444 1U/6.3V_4 C438 1U/6.3V_4 C759 120P/50V_4

C437 10U/6.3VS_6 C443 10U/6.3VS_6 C413 120P/50V_4

C447 10U/6.3VS_6 C424 *10U/6.3V_6 C398 120P/50V_4

C432 10U/6.3VS_6 +VREF_DQ1 C429 120P/50V_4

C435 10U/6.3VS_6 C454 0.1U/10V_4 C475 120P/50V_4

C469 10U/6.3VS_6
C441 1000P/50V_4
A C462 10U/6.3VS_6 A

C442 *10U/6.3V_6 +VREF_CA1


C484 0.1U/10V_4
C439 10U/6.3V_6 +3V

C446 10U/6.3V_6 C485 1000P/50V_4 C434 0.1U/10V_4


PROJECT : U56
C483 *0.047U/10V_4
C430 2.2U/6.3V_6 Quanta Computer Inc.
C498 1000P/50V_4
Size Document Number Rev
Custom 1A
System Memory 2/2 (9.2H)
NB5 Date: Tuesday, August 07, 2012 Sheet 13 of 39
5 4 3 2 1
5 4 3 2 1

U18A U18G

DP E/F POWER DP A/B POWER


14
+1.8V_DPE_VDD18 AG15 AE11
DPE_VDD18#1 DPA_VDD18#1
2.5GT/s bit rate AG16 DPE_VDD18#2 DPA_VDD18#2 AF11
PEG_TXP0 AF30 AH30 C_PEG_RXP0 C210 0.22U/10V_4
[2] PEG_TXP0 PCIE_RX0P PCIE_TX0P PEG_RXP0 [2]
PEG_TXN0 AE31 AG31 C_PEG_RXN0 C211 0.22U/10V_4
[2] PEG_TXN0 PCIE_RX0N PCIE_TX0N PEG_RXN0 [2]
D +1.0V_DPE_VDD10 AG20 DPE_VDD10#1 DPA_VDD10#1 AF6 D
AG21 DPE_VDD10#2 DPA_VDD10#2 AF7
PEG_TXP1 AE29 AG29 C_PEG_RXP1 C191 0.22U/10V_4
[2] PEG_TXP1 PEG_TXN1 PCIE_RX1P PCIE_TX1P C_PEG_RXN1 PEG_RXP1 [2]
AD28 AF28 C192 0.22U/10V_4
[2] PEG_TXN1 PCIE_RX1N PCIE_TX1N PEG_RXN1 [2]
AG14 DPE_VSSR#1 DPA_VSSR#1 AE1
AH14 DPE_VSSR#2 DPA_VSSR#2 AE3
PEG_TXP2 AD30 AF27 C_PEG_RXP2 C193 0.22U/10V_4 AM14 AG1
[2] PEG_TXP2 PCIE_RX2P PCIE_TX2P PEG_RXP2 [2] DPE_VSSR#3 DPA_VSSR#3
PEG_TXN2 AC31 AF26 C_PEG_RXN2 C194 0.22U/10V_4 AM16 AG6
[2] PEG_TXN2 PCIE_RX2N PCIE_TX2N PEG_RXN2 [2] DPE_VSSR#4 DPA_VSSR#4
AM18 DPE_VSSR#5 DPA_VSSR#5 AH5
PEG_TXP3 AC29 AD27 C_PEG_RXP3 C190 0.22U/10V_4
[2] PEG_TXP3 PCIE_RX3P PCIE_TX3P PEG_RXP3 [2]
PEG_TXN3 AB28 AD26 C_PEG_RXN3 C189 0.22U/10V_4
[2] PEG_TXN3 PCIE_RX3N PCIE_TX3N PEG_RXN3 [2]
+1.8V_DPE_VDD18 AF16 AE13
DPF_VDD18#1 DPB_VDD18#1
AG17 DPF_VDD18#2 DPB_VDD18#2 AF13
PEG_TXP4 AB30 AC25 C_PEG_RXP4 C200 0.22U/10V_4
[2] PEG_TXP4 PCIE_RX4P PCIE_TX4P PEG_RXP4 [2]

PCI EXPRESS INTERFACE


PEG_TXN4 AA31 AB25 C_PEG_RXN4 C201 0.22U/10V_4
[2] PEG_TXN4 PCIE_RX4N PCIE_TX4N PEG_RXN4 [2]

+1.0V_DPE_VDD10 AF22 DPF_VDD10#1 DPB_VDD10#1 AF8 NC for Mars


PEG_TXP5 AA29 Y23 C_PEG_RXP5 C198 0.22U/10V_4 AG22 AF9
[2] PEG_TXP5 PCIE_RX5P PCIE_TX5P PEG_RXP5 [2] DPF_VDD10#2 DPB_VDD10#2
PEG_TXN5 Y28 Y24 C_PEG_RXN5 C199 0.22U/10V_4
[2] PEG_TXN5 PCIE_RX5N PCIE_TX5N PEG_RXN5 [2]
AF23 DPF_VSSR#1 DPB_VSSR#1 AF10
PEG_TXP6 Y30 AB27 C_PEG_RXP6 C203 0.22U/10V_4 AG23 AG9
[2] PEG_TXP6 PCIE_RX6P PCIE_TX6P PEG_RXP6 [2] DPF_VSSR#2 DPB_VSSR#2
PEG_TXN6 W 31 AB26 C_PEG_RXN6 C202 0.22U/10V_4 AM20 AH8
[2] PEG_TXN6 PCIE_RX6N PCIE_TX6N PEG_RXN6 [2] DPF_VSSR#3 DPB_VSSR#3
AM22 DPF_VSSR#4 DPB_VSSR#4 AM6
AM24 DPF_VSSR#5 DPB_VSSR#5 AM8
PEG_TXP7 W 29 Y27 C_PEG_RXP7 C207 0.22U/10V_4
[2] PEG_TXP7 PCIE_RX7P PCIE_TX7P PEG_RXP7 [2]
PEG_TXN7 V28 Y26 C_PEG_RXN7 C208 0.22U/10V_4
[2] PEG_TXN7 PCIE_RX7N PCIE_TX7N PEG_RXN7 [2]

C V30 W 24 R71 150/F_4 AF17 AE10 C


PCIE_RX8P PCIE_TX8P DPEF_CALR DPAB_CALR
U31 PCIE_RX8N PCIE_TX8N W 23

U29 V27 +1.8V_DPE_VDD18 AG18 DP PLL POWER AG8


PCIE_RX9P PCIE_TX9P DPE_PVDD DPA_PVDD
T28 PCIE_RX9N PCIE_TX9N U26 AF19 DPE_PVSS DPA_PVSS AG7

T30 PCIE_RX10P PCIE_TX10P U24


R31 U23 +1.8V_DPE_VDD18 AG19 AG10
PCIE_RX10N PCIE_TX10N DPF_PVDD DPB_PVDD
AF20 DPF_PVSS DPB_PVSS AG11

R29 PCIE_RX11P PCIE_TX11P T26


P28 PCIE_RX11N PCIE_TX11N T27
Mars_S3_Pro

P30 PCIE_RX12P PCIE_TX12P T24


N31 PCIE_RX12N PCIE_TX12N T23

N29 PCIE_RX13P PCIE_TX13P P27 (Seymour-S3: LVDS mode 240mA@1.0V)


M28 PCIE_RX13N PCIE_TX13N P26 (Seymour-S3: DP mode 220mA@1.0V)
+1.0V_DPE_VDD10

M30 P24 +1.0V_DPE_VDD10 L17


PCIE_RX14P PCIE_TX14P +1.0V_VGA
L31 P23 *0_6/S
PCIE_RX14N PCIE_TX14N
Mars/ Chelsea Only : Stuff Ra
Do not install For Thames C130 C131 C140
L29 M27 0.1U/10V_4 1U/10V_4 10U/6.3V_6
PCIE_RX15P PCIE_TX15P
B
K30 PCIE_RX15N PCIE_TX15N N26 Ra B
R106 1.69K/F_4 +1.0V_VGA

CLOCK
CLK_VGA_P AK30 Install for Thames ONLY: Stuff Rb (Seymour-S3: LVDS mode 300mA@1.8V)
[7] CLK_VGA_P PCIE_REFCLKP
CLK_VGA_N AK32 Do not install for Chelsea (Seymour-S3: DP mode 300mA@1.8V)
[7] CLK_VGA_N PCIE_REFCLKN
Rb +1.8V_DPE_VDD18 L10 +1.8V_VGA
CALIBRATION M72_PCIE_CALRP R95 *1.27K/F_4 *0_6/S
Install for Mars/ Chelsea PCIE_CALRP Y22
C84 C85 C76
1K/F_4 R259 N10 AA22 Rc 0.1U/10V_4 1U/10V_4 10U/6.3V_6
PW RGOOD PCIE_CALRN M72_PCIE_CALRN R107 1K/F_4 +1.0V_VGA
PEGX_RST# AL27 Install 2k for Thames
PERSTB
Install 1k for Mars
Mars_S3_Pro
100MHz (+/-300ppm) input frequency,
+3V
0-0.7V single-ended swing
Chelsea/MARS Thames

Ra 1.69K n/a

Rb n/a 1.27K
C689
U21 0.1U/10V_4
A C801 *0.1U/10V_4 MC74VHC1G08DFT2G Rc 1K 2K A
5

+1.0V_VGA [15,17,34]
[7] GPU_RST# 2 +1.8V_VGA [15,17,35]
4 PEGX_RST#
[6] VGA_RSTB R357 330_4 DGPU_HIN_RST# 1

R352
PROJECT : U56
3

100K/F_4 Quanta Computer Inc.


Size Document Number Rev
Custom Mars S3 PCIE_Interface 1A
NB5 Date: Tuesday, August 07, 2012 Sheet 14 of 39
5 4 3 2 1
5 4 3 2 1

15
U18B

Thermal Solution(Close to GPU)


M93-S3/M92-S2 TXCAP_DPA3P
AF2
AE9 AF4 C22 0.01U/16V_4
TP9 DVCNTL_0/ DVPDATA_18 TXCAM_DPA3N
TP14 L9
DVCNTL_1 / NC U2
TP16 N9 AG3
DVCNTL_2 / NC TX0P_DPA2P
TP12 AE8
DVDATA_12 / DVPDATA_16 DPA TX0M_DPA2N
AG5
AD9 GPUT_CLK 8 1 +3V_DELAY
TP19 DVDATA_11 / DVPDATA_20 SCLK VCC
TP21 AC10 AH3
DVDATA_10 / DVPDATA_22 TX1P_DPA1P GPUT_DATA GPU_THERMDA
TP1 AD7 AH1 7 2
DVDATA_9 / DVPDATA_12 TX1M_DPA1N SDA DXP
TP18 AC8
DVDATA_8 / DVPDATA_14 VGA_ALERT R463 *0_4 VGA_ALERT_R
TP4 AC7 AK3 6 3
DVDATA_7 / DVPCNTL_0 TX2P_DPA0P ALERT# DXN C31
TP7 AB9 AK1
DVDATA_6 / DVPDATA_8 TX2M_DPA0N R14 10K/F_4 2200P/50V_4
TP8 AB8 +3V_DELAY 4 5
DVDATA_5 / DVPDATA_6 OVERT# GND
TP3 AB7 AK5
D +VDDR4 DVDATA_4 DVPDATA_4 TXCBP_DPB3P GPU_THERMDC D
Memory ID TXCBM_DPB3N
AM3 [4] DGPU_OVT#
DVO G781-1P8
R268 *10K/F_4 MEM_ID3 AB4 AK6
R267 *10K/F_4 MEM_ID2 DVDATA_3 / DVPDATA_19 TX3P_DPB2P
AB2 AM5
R42 *10K/F_4 MEM_ID1 DVDATA_2 / DVPDATA_21 TX3M_DPB2N
Y8
DVDATA_1 / DVPDATA_2 DPB Main:AL000781039 G781-1P8(9Ah)
R269 *10K/F_4 MEM_ID0 Y7 AJ7
DVDATA_0 / DVPDATA_0 TX4P_DPB1P
TX4M_DPB1N
AH6 2nd:AL001412005 EMC1412-2-ACZL-TR(9Ah)
AK8
TX5P_DPB0P
AL7
TX5M_DPB0N

GPIO30 GPIO12 GPIO16 GPIO20 GPIO15 Thames XT M93-S3/M92-S2


W6
DPC_PVDD / DVPDATA_11
V6
DPC_PVSS / GND M92-S2/M93-S3
PWRCNTL4 PWRCNTL3 PWRCNTL2 PWRCNTL1 PWRCNTL0 V-CORE DVPDATA_3/TXCCP_DPC3P
V4
U5
DVPCNTL_2/TXCCM_DPC3N
AC6
DPC_VDD18#1/DVPDAT10
0 0 0 0 0 1.0V AC5
DPC_VDD18#2/DVPDAT23 DVPDATA_7 / TX0P_DPC2P
W3
V2
DVPDATA_1 / TX0M_DPC2N
0 0 0 0 1 0.9V NC for Mars DVPCNTL_MV1 / TX1P_DPC1P
Y4
AA5 W5
DPC_VDD10#1/DVPDAT15 DVPDATA_9 / TX1M_DPC1N
AA6
+3V_DELAY DPC_VDD10#2/DVPDAT17 +1.8V_AVDD_Q
0 0 0 1 0 0.875V DVPDATA_13 / TX2P_DPC0P
AA3
DVPCNTL_1 / TX2M_DPC0N
Y2 1.8V(70mA)
R253 4.7K_4 GPUT_DATA
R250 4.7K_4 GPUT_CLK +1.8V_AVDD_Q
0 0 0 1 1 0.85V U1
DPC_VSSR#1 / DVPCLK +1.8V_VGA
W1 L18 0_6
DPC_VSSR#2 / DVPDAT5
Access+3V_DELAY
to SMBBus ans SDA/SCL is mandatory on all designs U3
DPC_VSSR#3 / GND
0 0 1 0 0 0.8V Add test points on SMBBus and SDA/SCL for debug Y6
DPC_VSSR#4 / GND
AA1 DPC C154 C153 C152
R264 4.7K_4 DPC_VSSR#5/ DVPCNTL_MV0 0.1U/10V_4 1U/10V_4 *10U/6.3V_6
R263 4.7K_4
0 0 1 0 1 0.75V
Mars / Chelsea : AVSSN
TP80 R1 must be short to gnd
SCL
TP78 R3
SDA I2C +VDDD1
C
R
AM26 TP28 1.8V(45mA VDD1DI) C
GENERAL PURPOSE I/O AK26
GPIO0 AVSSN#1 +VDDD1
[16] GPIO0 U6 +1.8V_VGA
GPIO1 GPIO_0 L46 0_6
[16] GPIO1 U10 AL25 TP27
GPIO2 GPIO_1 G
[16] GPIO2 T10 AJ25
R252 *0_4 DGPUT_DATA GPIO_2 AVSSN#2
[26] GPUT_DATA U8
R251 *0_4 DGPUT_CLK GPIO_3_SMBDATA C620 C623 C626
[26] GPUT_CLK U7 AH24 TP29
+3V_DELAY R27 0_4 GPIO5 GPIO_4_SMBCLK B 0.1U/10V_4 1U/10V_4 *10U/6.3V_6
[26] GPU_AC_BATT T9 AG25
GPIO_5_AC_BATT AVSSN#3
[35] VDDCI_GPIO0 T8
GPIO_6 DAC1
R33 10K/F_4 GPU_AC_BATT R30 *10K/F_4 T7 AH26
GPIO_7_BLON HSYNC
P10 AJ27
R41 *10K/F_4 DGPU_TDI GPIO_8_ROMSO VSYNC
P4
GPIO10 GPIO_9_ROMSI
[33] GFX_CORE_CNTRL4 P2
R260 *10K/F_4 DGPU_TMS GPIO11 GPIO_10_ROMSCK R101 499/F_4
[16] GPIO11 N6 AD22
GPIO12 GPIO_11 RSET
SI , add R298 for [16,33] GFX_CORE_CNTRL3 N5
R261 *10K/F_4 DGPU_TDO GPIO13 GPIO_12 +1.8V_AVDD_Q
PP table update [16] GPIO13 N3 AG24 +1.8V_AVDD_Q
TP15 HDMI_HP2 GPIO_13 AVDD
Y9 AE22
R45 *10K/F_4 DGPU_TRSTB GFX_CORE_CNTRL0 GPIO_14_HPD2 AVSSQ
[33] GFX_CORE_CNTRL0 N1
GFX_CORE_CNTRL2 GPIO_15_PWRCNTL_0 +VDDD1
[33] GFX_CORE_CNTRL2 M4 AE23 +VDDD1
R245 *10K/F_4 GPIO_23_CLKREQb VGA_ALERT GPIO_16_SSIN VDD1DI
R6 AD23
HPD3 GPIO_17_THERMAL_INT VSS1DI
TP11 W10
R266 *10K/F_4 DGPU_PROCHOT# TEMP_FAIL GPIO_18_HPD3
M2
GPIO_19_CTF M92-S2/M93-S3
[33] GFX_CORE_CNTRL1 GFX_CORE_CNTRL1 P8 AM12
R456 10K/F_4 VGA_ALERT GPIO_20_PWRCNTL_1 CEC_1
P7 AK12
GPIO_21_BB_EN R2B / NC
GPIO29, 30 are NC on Thems/ whistler/ Seymour N8
GPIO_22_ROMCSB
GPIO_23_CLKREQb N7 AL11
DGPU_PROCHOT# R265 *0_4 GPIO_23_CLKREQB G2 / NC
AK10 AJ11
GPIO_29 G2B / NC
TP85 AM10
R271 10K/F_4 TEMP_FAIL GPIO_30
DGPU_TRSTB L6 AL9
TP10 JTAG_TRSTB B2B / NC
DGPU_TDI L5
TP6 JTAG_TDI
DGPU_TCK L3 Thames INSTALL Ra,Rb.
TP77 JTAG_TCK
DGPU_TMS L1 AH12
TP74 JTAG_TMS C / NC
DGPU_TDO K4 DAC2
TP75 JTAG_TDO Do not install for Mars/ Chelsea
TESTEN AF24 AJ9
TESTEN COMP / NC
PS_0 should be tied to GND on Thames
AB13
GENERICA
W8 AL13
B GENERICB H2SYNC B
W9 AJ13 Rb
GENERICC V2SYNC
W7
GENERICD
AD10
GENERICE_HPD4 PS_1
AD19 TP23
PS_1 PS_0
AC14 AC19 TP20
HPD1 PS_0 R91 *0_4
+3V_DELAY +1.8V_VGA
Fo Mars/ Chelsea
1.8V+R6043(249R)=1.8V/3=0.6V AE20 PS_3 TP26
Change La, Lb R301 499/F_4 PS_3 +1.8V_VGA +1.8V_VGA
Bead to 0 ohm AE17 PS_2 TP22
R98 R302 249/F_4 +0.6V_VREFG PS_2
AC16 Ra
VREFG R87 *0_4
*5.1K/F_4 For Thems: La,Lb: TS_A
AE19
CX8PG471000/BLM18PG471SN1D/1A_6
0_6 1.8V(75mA DPLL_PVDD) C562 0.1U/10V_4 AG13 R304 *715/F_4 R65 R67
TESTEN R2SET / NC 8.45K_4 *8.45K_4
+1.8V_VGA
L11 PS_0 PS_1
La C112 DDC/AUX
C119 C122 AE6
R100 10U/6.3V_6 1U/10V_4 0.1U/10V_4 PLL/CLOCK DDC1CLK R73 C80 R75 C82
AE5
+1.8V_DPLL_PVDD DDC1DATA 2K_4 4.75K/F_4
1K/F_4 AF14 *0.01U/50V_4 0.082U/16V_4
DPLL_PVDD
AE14 AD2
DPLL_PVSS AUX1P
AD4
AUX1N
Lb
+1.0V_VGA L42 0_6 +1.0V_DPLL_VDDC AD14 AC11
DPLL_VDDC DDC2CLK
AC13
C539 C542 C543 DDC2DATA +1.8V_VGA +1.8V_VGA
1.0V(125mA DPLL_VDDC)
10U/6.3V_8 1U/10V_4 0.1U/10V_4 EVGA-XTALI AM28 AD13
EVGA-XTALO XTALIN AUX2P
R96 *0_4
AK28
XTALOUT AUX2N
AD11 BIT5 => BIT0
AC22
NC#2/XO_IN
AB22 AE16
NC#1/XO_IN2 DDCCLK_AUX5P R66 R68
DDCDATA_AUX5N
AD16 PS0 => 11001 *0_4 *0_4
HCB1608KF-121T30(120,3000MA) 1.8V(5mA TSVDD) AC1 For AMD tuning
DDC6CLK TP5
+1.8V_VGA GPU_THERMDA T4 AC3 timing purpose PS1 => 01000 PS_2 PS_3
DPLUS DDC6DATA TP2
L44 GPU_THERMDC T2 THERMAL
DMINUS
AD20
C580 C581 NC/DDCCLK_AUX3P R74 C81 R76 C83
A Reserve for Power Play NC/DDCDATA_AUX3N
AC20 PS2 => 00000 A
C52 GPIO28 R5 4.75K/F_4 0.68U/6.3V_4 4.75K/F_4 *0.01U/50V_4
R270 3.01K/F_4 [16] GPIO28 TS_FDO
GFX_CORE_CNTRL0 10U/6.3V_6 1U/10V_4 0.1U/10V_4 +1.8V_TSVDD AD17
TSVDD
GFX_CORE_CNTRL1 R32 3.01K/F_4
AC17
TSVSS PS3 => 11000
C628 22P/50V_4 EVGA-XTALI
GFX_CORE_CNTRL2 R31 3.01K/F_4
1

GFX_CORE_CNTRL3 R36 3.01K/F_4 Y3 R334


27MHZ 1M/F_4
For Int Clk 27Mhz
R37 *3.01K/F_4
GFX_CORE_CNTRL4 Mars_S3_Pro
PROJECT : U56
2

Ra
GFX_CORE_CNTRL4 R256
Rb
10K/F_4 +3V_DELAY C637 22P/50V_4 EVGA-XTALO Quanta Computer Inc.
GFX_CORE_CNTRL2 R257 *10K/F_4 For Mars: Stuff Ra only=> VDDC 1.1V Size Document Number Rev
R274 *3.01K/F_4 +1.8V_VGA [14,17,35] Custom
VDDCI_GPIO0 For Thems: Stuff Ra, Rb=> VDDC 1.0V Mars S3 Main 1A
+1.0V_VGA [14,17,34]
NB5 Date: Thursday, August 09, 2012 Sheet 15 of 39
5 4 3 2 1
5 4 3 2 1

AA27
AB24
U18E

PCIE_VSS#1 GND#1 A3
A30
U18F

LVDS CONTROL AB11


16
PCIE_VSS#2 GND#2 VARY_BL RECOMMENDED SETTINGS
AB32 PCIE_VSS#3 GND#3 / EVDDQ#2 AA13 DIGON AB12
AC24 AA16 0= DO NOT INSTALL RESISTOR
AC26
PCIE_VSS#4 GND#4
AB10
CONFIGURATION STRAPS-- SEE EACH DATABOOK FOR STRAP DETAILS 1 = INSTALL 3K RESISTOR
PCIE_VSS#5 GND#5
AC27 AB15 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, X = DESIGN DEPENDANT
PCIE_VSS#6 GND#6 / EVDDQ#3
AD25 AB6 NA = NOT APPLICABLE
PCIE_VSS#7 GND#7 THEY MUST NOT CONFLICT DURING RESET
D
AD32 PCIE_VSS#8 GND#8 AC9 TXCLK_UP_DPF3P AH20 D
AE27 PCIE_VSS#9 GND#9 AD6 TXCLK_UN_DPF3N AJ19
AF32 PCIE_VSS#10 GND#10 AD8
AG27 AE7 AL21 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
PCIE_VSS#11 GND#11 TXOUT_U0P_DPF2P
AH32 PCIE_VSS#12 GND#12 AG12 TXOUT_U0N_DPF2N AK20
K28 PCIE_VSS#13 GND#13 AH10
K32 AH28 AH22 TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING
PCIE_VSS#14 GND#14 TXOUT_U1P_DPF1P
L27 PCIE_VSS#15 GND#15 B10 TXOUT_U1N_DPF1N AJ21 0
M32 B12 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED
PCIE_VSS#16 GND#16
N25 PCIE_VSS#17 GND#17 B14 TXOUT_U2P_DPF0P AL23 X
N27 PCIE_VSS#18 GND#18 B16 TXOUT_U2N_DPF0N AK22
P25 B18 RSVD GPIO2 RESERVED 0
PCIE_VSS#19 GND#19 RSVD GPIO8 RESERVED 0
P32 PCIE_VSS#20 GND#20 B20 TXOUT_U3P AK24
R27 PCIE_VSS#21 GND#21 B22 TXOUT_U3N AJ23
T25 PCIE_VSS#22 GND#22 B24
T32 B26 BIF_VGA DIS GPIO9 VGA ENABLED 0
PCIE_VSS#23 GND#23 LVTMDP
U25 PCIE_VSS#24 GND#24 B6
U27 PCIE_VSS#25 GND#25 B8
V32 C1 AL15 RSVD GPIO21 RESERVED 0
PCIE_VSS#26 GND#26 TXCLK_LP_DPE3P
W 25 PCIE_VSS#27 GND#27 C32 TXCLK_LN_DPE3N AK14
W 26 PCIE_VSS#28 GND#28 E28
W 27 F10 AH16 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM 0
PCIE_VSS#29 GND#29 TXOUT_L0P_DPE2P
Y25 PCIE_VSS#30 GND#30 F12 TXOUT_L0N_DPE2N AJ15
Y32 PCIE_VSS#31 GND#31 F14
F16 AL17 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 0 0 1
GND#32 TXOUT_L1P_DPE1P
GND#33 F18 TXOUT_L1N_DPE1N AK16
GND#34 F2
F20 AH18 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS (Removed on Seymour/Whistler) 0
GND#35 TXOUT_L2P_DPE0P
M6 GND#56 GND#36 F22 TXOUT_L2N_DPE0N AJ17
N11 GND#57 GND#37 F24
C F26 AL19 RSVD H2SYNC RESERVED 0 C
GND#38 TXOUT_L3P
N13 GND#59 GND#39 F6 TXOUT_L3N AK18
N16 F8
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
AUD[1]
AUD[0]
HSYNC
VSYNC
SEE DATABOOK FOR DETAIL
SEE DATABOOK FOR DETAIL
0
0
P6 GND#63 GND#43 G31
P9 G8 Mars_S3_Pro
GND#64 GND#44 RSVD GENERICC RESERVED 0
R12 GND#65 GND#45 H14
R15 GND#66 GND#46 H17
R17 GND#67 GND#47 H2
R20 GND#68 GND#48 H20
T13 GND#69 GND#49 H6
T16 J27
T18
GND#70
GND#71
GND#50
GND#51 J31 NOTE1: AMD RESERVED CONFIGURATION STRAPS
T21 GND#72 GND#52 K11
T6 GND#73 GND#53 K2 ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED,
U15 GND#74 GND#54 K22
U17 K6 THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET.
GND#75 GND#55
U20 GND#76 GND#85 T11
U9 GND#77 GND#86 R11
V13 GPIO21 H2SYNC GENERICC GPIO8 GPIO2
GND#78
V16 GND#79
V18 GND#80
Y10 GND#81
Y15 GND#82
Y17 GND#83 VSS_MECH#1 A32
Y20 GND#84 VSS_MECH#2 AM1
VSS_MECH#3 AM32
For Robson &
B B
Seymour should
Mars_S3_Pro
be NC
+3V_DELAY

Power Up/Down Sequence Memory Aperture size


GPIO0 R249 *10K/F_4
GPIO9 GPIO13 GPIO12 GPIO11 [15] GPIO0
GPIO1 R38 *10K/F_4
[15] GPIO1
BIOSROM ROMIDCFG2 ROMIDCFG1 ROMIDCFG0 GPIO2 R44 *10K/F_4
[15] GPIO2
0 128M 0 0 0 GPIO13 R258 *10K/F_4
[15] GPIO13
+VGA_CORE VDDC
0 256M 0 0 1 [15,33] GFX_CORE_CNTRL3
GPIO12 R247 *10K/F_4

GPIO11 R246 10K/F_4


0 64M 0 1 0 [15] GPIO11

+VGA_CORE VDDCI GPIO28 R254 *10K/F_4


Ra
0 32M 0 1 1 [15] GPIO28

Rb R255 10K/F_4

+1.5V_VGA VDDR1 0 512M 1 0 0


Mars : stuff Ra=> disable MLPS
A 0 1G 1 0 1 stuff Rb=> enable MLPS A

+3.3V_Delay VDDR3
0 2G 1 1 0
+1.8V_VGA VDDR4 0 4G 1 1 1 PROJECT : U56
+1.8V_VGA VDD_CT
It is a shared pin strap with CONFIG[2:0] if BIOS_ROM_EN is set to 0.
Quanta Computer Inc.
20ms 20ms Size Document Number Rev
Custom 1A
Mars S3 GND / LVDS/ Straps
+3V_DELAY [15,17]
NB5 Date: Tuesday, August 07, 2012 Sheet 16 of 39
5 4 3 2 1
5 4 3 2 1

17
+1.5V_VGA [18,19,34]
+1.8V_VGA [14,15,35]
+1.0V_VGA [14,15,34]
+VGA_CORE [33,34]
U18D
+3V [2,4,6,8,9,10,11,12,13,14,20,21,22,23,24,25,26,27,33,34,35,38]
+5V [20,22,23,24,25,27,38] MEM I/O
1.5V ( DDR3, MVDDQ = 1.5V@1.2A) PCIE AM30
+1.5V_VGA PCIE_PVDD +1.8V_VGA
H13 VDDR1#1 PCIE_VDDR#1 AB23
H16 VDDR1#2 PCIE_VDDR#2 AC23
H19 AD24 Mars NC
C60 C87 C137 C101 C143 C75 VDDR1#3 PCIE_VDDR#3
J10 VDDR1#4 PCIE_VDDR#4 AE24
2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 J23 AE25
VDDR1#5 PCIE_VDDR#5
J24 VDDR1#6 PCIE_VDDR#6 AE26
D J9 AF25 D
VDDR1#7 PCIE_VDDR#7
K10 VDDR1#8 PCIE_VDDR#8 AG26
K23 VDDR1#9
K24 +1.0V_VGA
VDDR1#10
K9 VDDR1#11 PCIE_VDDC#1 L23
C638 C59 C538 C533 C552 C184 C92 C129 C141 L11 L24 +1.0V_PCIE_VDDC
0.1U/10V_4 0.1U/10V_4 VDDR1#12 PCIE_VDDC#2
10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 L12 VDDR1#13 PCIE_VDDC#3 L25 1.0V(2.0A)
0.1U/10V_4 0.1U/10V_4 L13 L26 +1.0V_PCIE_VDDC L19 *0_8/S
VDDR1#14 PCIE_VDDC#4
L20 VDDR1#15 PCIE_VDDC#5 M22
L21 VDDR1#16 PCIE_VDDC#6 N22
L22 N23 C144 C146 C147 C145 C149 C167 C171 C169
+1.8V_VDD_CT VDDR1#17 PCIE_VDDC#7 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_6
PCIE_VDDC#8 N24
VDDC_CT: 1.8V @250mA PCIE_VDDC#9 R22
L45 0_6 +1.8V_VDD_CT T22
+1.8V_VGA LEVEL PCIE_VDDC#10
PCIE_VDDC#11 U22
TRANSLATION V22
C596 C598 C139 C597 C138 PCIE_VDDC#12 +VGA_CORE
AA20 VDD_CT#1 VDDC+VDDCI
10U/6.3VS_6 1U/10V_4 1U/10V_4 1U/10V_4 0.1U/10V_4 AA21 0.85~1.1V(14.2A peak )( Ripple < 87.2mV)
VDD_CT#2
AB20 VDD_CT#3 VDDC#1 AA15
+3V_DELAY AB21 CORE N15
VDD_CT#4 VDDC#2
VDDR3 : 3.3V @ 60mA VDDC#3 N17
+3V_VGA L16 *0_6/S +3V_DELAY M93-S3/M92-S2 R13 C526 C549 C88 C105 C577 C98 C93 C530
VDDC#4

POWER
R16 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_6
VDDC#5
AA17 VDDR3#1 VDDC#6 R18
C113 C102 C123 C521 AA18 I/O Y21
1U/10V_4 1U/10V_4 1U/10V_4 VDDR3#2 VDDC#7
10U/6.3VS_6 AB17 T12
VDDR3#3 VDDC#8
AB18 VDDR3#4 VDDC#9 T15

1
VDDC#10 T17
V12 T20 +
VDDR4#1 / VDDR5 VDDC#11 C78 C94 C63 C599 C568 C89 C103 C121
Y12 VDDR4#2 VDDC#12 U13
C +VDDR4 U12 U16 1U/10V_4 2.2U/6.3V_4 10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4 330U_2.5V_3528 C

2
VDDR4#3 / VDDR5 VDDC#13 1U/10V_4
VDDR4 : 1.8V @ 300mA VDDC#14 U18
+1.8V_VGA +VDDR4 AA11 V21
L7 0_6 NC#1 / VDDR4 VDDC#15
TP17 Y11 DVCLK / VDDR4 VDDC#16 V15
C35 C86 C77 V17
VDDC#17

1
10U/6.3VS_6 0.1U/10V_4 V11 V20
1U/10V_4 NC#3 / VDDR5 VDDC#18 +
VDDC#20 Y13
Y16 C104 C64 C96 C573 C62 C91 C764
VDDC#21 1U/10V_4 2.2U/6.3V_4 1U/10V_4 1U/10V_4 1U/10V_4 *330U_2.5V_3528
Y18

2
VDDC#22 1U/10V_4
N12
VDDC#23
M11
MEM CLK VDDC#24
AA12
VDDC#25
L17 U11
VDDRHA VDDC#26
For Seymour,PCIE_PVDD is PCIE_VDDR VDDC#19/BIF_VDDC
U21 +1.0V_PCIE_VDDC
L16 R21
VSSRHA VDDC#23 /BIF_VDDC C527 C540 C583 C557 C537 C566
M13 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6
PLL ISOLATED VDDCI#1 M15
CORE I/O VDDCI#2 M16
VDDCI#3
M17
VDDCI#4 R21 and U21
M18
MPV18 VDDCI#5 Must always be connected to PCIE_VDDC for Mars
L8 M20
MPLL_PVDD VDDCI#6
M21
VDDCI#7
1.8V(75mA MPV18) VDDCI#8
N20
1.0V_VGA(100mA SPV10) SPV18 H7 +VGA_CORE R462 *0_8
SPLL_PVDD +VDDCI
L38 BLM18PG181SN1D(180,1.5A)_6 MPV18
+1.8V_VGA
L8 PBY160808T-121Y-N(120,2.5A) +1.0V_VGA_SPV10 H8
+1.0V_VGA SPLL_VDDC
C519 C522 J7
1U/10V_4 0.1U/10V_4 C39 C46 C42 SPLL_PVSS
0.95V~1.1V(2A VDDCI)
B 10U/6.3VS_6 1U/10V_4 +VDDCI B
+VDDCI
1.8V(50mA SPV18) 0.1U/10V_4
BACK BIAS
L9 PBY160808T-121Y-N(120,2.5A) SPV18 C111 C126 C118 C97 C115 C116
+1.8V_VGA
M12 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6
BBP#2
C45 C41
1U/10V_4 0.1U/10V_4
Mars_S3_Pro

A A

PROJECT : U56
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Mars S3 Power_and_NC
NB5 Date: Tuesday, August 07, 2012 Sheet 17 of 39
5 4 3 2 1
5 4 3 2 1

18
U18C

[19] VMA_ODT0 VMA_ODT0


[19] VMA_ODT1 VMA_ODT1 VMA_DQ0 K27 K17 VMA_MA0
VMA_DQ1 DQA_0 MAA_0 VMA_MA1
J29 DQA_1 MAA_1 J20
[19] VMA_RAS0# VMA_RAS0# VMA_DQ2 H30 H23 VMA_MA2
VMA_RAS1# VMA_DQ3 DQA_2 MAA_2 VMA_MA3
[19] VMA_RAS1# H32 DQA_3 MAA_3 G23
VMA_DQ4 G29 G24 VMA_MA4
VMA_CAS0# VMA_DQ5 DQA_4 MAA_4 VMA_MA5
[19] VMA_CAS0# F28 DQA_5 MAA_5 H24
[19] VMA_CAS1# VMA_CAS1# VMA_DQ6 F32 J19 VMA_MA6
VMA_DQ7 DQA_6 MAA_6 VMA_MA7
F30 DQA_7 MAA_7 K19

MEMORY INTERFACE
[19] VMA_WE0# VMA_WE0# VMA_DQ8 C30 J14 VMA_MA8
VMA_WE1# VMA_DQ9 DQA_8 MAA_8 VMA_MA9
D [19] VMA_WE1# F27 DQA_9 MAA_9 K14 D
VMA_DQ10 A28 J11 VMA_MA10
VMA_CS0# VMA_DQ11 DQA_10 MAA_10 VMA_MA11
[19] VMA_CS0# C28 DQA_11 MAA_11 J13
VMA_DQ12 E27 H11 VMA_MA12
VMA_CS1# VMA_DQ13 DQA_12 MAA_12 VMA_BA2
[19] VMA_CS1# G26 DQA_13 MAA_13/BA2 G11
VMA_DQ14 D26 J16 VMA_BA0
VMA_CKE0 VMA_DQ15 DQA_14 MAA_14/BA0 VMA_BA1
[19] VMA_CKE0 F25 DQA_15 MAA_15/BA1 L15
[19] VMA_CKE1 VMA_CKE1 VMA_DQ16 A25
VMA_DQ17 DQA_16 VMA_DM0
C25 DQA_17 DQMA_0 E32
[19] VMA_CLK0 VMA_CLK0 VMA_DQ18 E25 E30 VMA_DM1
VMA_CLK0# VMA_DQ19 DQA_18 DQMA_1 VMA_DM2
[19] VMA_CLK0# D24 DQA_19 DQMA_2 A21
VMA_DQ20 E23 C21 VMA_DM3
VMA_CLK1 VMA_DQ21 DQA_20 DQMA_3 VMA_DM4
[19] VMA_CLK1 F23 DQA_21 DQMA_4 E13
[19] VMA_CLK1# VMA_CLK1# VMA_DQ22 D22 D12 VMA_DM5
VMA_DQ23 DQA_22 DQMA_5 VMA_DM6
F21 DQA_23 DQMA_6 E3
VMA_WDQS[7..0] VMA_DQ24 E21 F4 VMA_DM7
[19] VMA_WDQS[7..0] DQA_24 DQMA_7
VMA_DQ25 D20
VMA_RDQS[7..0] VMA_DQ26 DQA_25 VMA_RDQS0
[19] VMA_RDQS[7..0] F19 DQA_26 RDQSA_0 H28
VMA_DQ27 A19 C27 VMA_RDQS1
VMA_DM[7..0] VMA_DQ28 DQA_27 RDQSA_1 VMA_RDQS2
[19] VMA_DM[7..0] D18 DQA_28 RDQSA_2 A23
VMA_DQ29 F17 E19 VMA_RDQS3
VMA_DQ[63..0] VMA_DQ30 DQA_29 RDQSA_3 VMA_RDQS4
[19] VMA_DQ[63..0] A17 DQA_30 RDQSA_4 E15
VMA_DQ31 C17 D10 VMA_RDQS5

From GPU
VMA_MA[13..0] VMA_DQ32 DQA_31 RDQSA_5 VMA_RDQS6
[19] VMA_MA[13..0] E17 DQA_32 RDQSA_6 D6
VMA_DQ33 D16 G5 VMA_RDQS7
VMA_DQ34 DQA_33 RDQSA_7 25mm (max) 5mm (max) 25mm (max)
F15 DQA_34
[19] VMA_BA0 VMA_BA0 VMA_DQ35 A15 H27 VMA_WDQS0
VMA_BA1 VMA_DQ36 DQA_35 W DQSA_0 VMA_WDQS1
[19] VMA_BA1 D14 DQA_36 W DQSA_1 A27
VMA_BA2 VMA_DQ37 F13 C23 VMA_WDQS2 DRAM_RST R20 10/F_4 DRAM_RST_M
[19] VMA_BA2 DQA_37 W DQSA_2 DRAM_RST_M [19]
VMA_DQ38 A13 C19 VMA_WDQS3 R21 51/F_4
VMA_DQ39 DQA_38 W DQSA_3 VMA_WDQS4
C C13 DQA_39 W DQSA_4 C15 C
support 1Gbit VMA_DQ40 E11 E9 VMA_WDQS5
VMA_DQ41 DQA_40 W DQSA_5 VMA_WDQS6 R13 C25
VRAM ( 64M X 16 ) A11 DQA_41 W DQSA_6 C5
VMA_DQ42 C11 H4 VMA_WDQS7
VMA_DQ43 DQA_42 W DQSA_7 4.99K/F_4 120P/50V_4
F11 DQA_43
VMA_DQ44 A9 L18 VMA_ODT0
VMA_DQ45 DQA_44 ODTA0 VMA_ODT1
C9 DQA_45 ODTA1 K16
VMA_DQ46 F9
VMA_DQ47 DQA_46 VMA_CLK0
D8 DQA_47 CLKA0 H26
VMA_DQ48 E7 H25 VMA_CLK0#
VMA_DQ49 DQA_48 CLKA0B
A7 DQA_49
VMA_DQ50 C7 G9 VMA_CLK1
VMA_DQ51 DQA_50 CLKA1 VMA_CLK1#
F7 DQA_51 CLKA1B H9 Place all these components very close to GPU (Within
VMA_DQ52 A5
VMA_DQ53 E5
DQA_52
G22 VMA_RAS0# 25mm) and keep all component close to each Other (within
DQA_53 RASA0B
VMA_DQ54 C3 DQA_54 RASA1B G17 VMA_RAS1# 5mm) except Rser2
VMA_DQ55 E1
VMA_DQ56 DQA_55 VMA_CAS0# This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
G7 DQA_56 CASA0B G19
+1.5V_VGA VMA_DQ57 G6 G16 VMA_CAS1# Capacitors and Resistor values are an example only. The Series R and
VMA_DQ58 DQA_57 CASA1B
G1 DQA_58 || Cap values will depend on the DRAM load and will have to be
VMA_DQ59 G3 H22 VMA_CS0#
VMA_DQ60 DQA_59 CSA0B_0 calculated for different Memory ,DRAM Load and board to pass Reset
J6 DQA_60 CSA0B_1 J22
R111 VMA_DQ61 J1
Signal Spec.
VMA_DQ62 DQA_61 VMA_CS1#
J3 DQA_62 CSA1B_0 G13
40.2/F_4 VMA_DQ63 J5 K13
DQA_63 CSA1B_1
MVREFD K26 K20 VMA_CKE0
MVREFDA CKEA0 VMA_CKE1
J26 MVREFSA CKEA1 J17
+1.5V_VGA +1.5V_VGA
Ra R108 *243/F_4 J25 G25 VMA_WE0#
B
C177 R112 Rb R248 1K/F_4 MEM_CALRN0 W EA0B VMA_WE1# B
K7 NC/TESTEN#2 W EA1B H10

0.1U/10V_4 100/F_4 R113 Rc R35 *150/F_4 Note 2 J8 AB16 PX_EN


Rd MEM_CALRP1/DPC_CALR PX_EN TP86
R109 120/F_4 Note 1 K25 G14
40.2/F_4 MEM_CALRP0 RSVD#2 VMA_MA13
RSVD#3 G20
DRAM_RST L10
MVREFS DRAM_RST
Ra non-stuff CLKTESTA K8
CLKTESTB CLKTESTA
L7
Rb 1K ohm CLKTESTB
C179 R114 Rc non-stuff
Mars_S3_Pro
0.1U/10V_4 100/F_4
Rd 120 ohm
for Mars C44 C524
*0.1U/10V_4 *0.1U/10V_4

R39 R262
*51.1/F_4 *51.1/F_4

route 50ohms
single-ended/100ohms diff +1.5V_VGA [17,19,34]
and keep short
A A

PROJECT : U56
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
Mars S3 MEM_Interface
NB5 Date: Tuesday, August 07, 2012 Sheet 18 of 39
5 4 3 2 1
5 4 3 2 1

VMA_MA[13..0]

19
[18] VMA_MA[13..0]
512M/1G DDR3
[18] VMA_DQ[63..0]
[18] VMA_DM[7..0] [18] VMA_WDQS[7..0]
[18] VMA_RDQS[7..0]
U5 U19 U3 U13

VREFC_VMA1 M9 E4 VMA_DQ20 VREFC_VMA2 M9 E4 VMA_DQ27 VREFC_VMA3 M9 E4 VMA_DQ38 VREFC_VMA4 M9 E4 VMA_DQ48


VREFD_VMA1 VREFCA DQL0 VMA_DQ18 VREFD_VMA2 VREFCA DQL0 VMA_DQ31 VREFD_VMA3 VREFCA DQL0 VMA_DQ32 VREFD_VMA4 VREFCA DQL0 VMA_DQ52
H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8
F3 VMA_DQ22 F3 VMA_DQ25 F3 VMA_DQ36 F3 VMA_DQ53
VMA_MA0 DQL2 VMA_DQ17 VMA_MA0 DQL2 VMA_DQ29 VMA_MA0 DQL2 VMA_DQ34 VMA_MA0 DQL2 VMA_DQ54
N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9 N4 A0 DQL3 F9
VMA_MA1 P8 H4 VMA_DQ23 VMA_MA1 P8 H4 VMA_DQ30 VMA_MA1 P8 H4 VMA_DQ39 VMA_MA1 P8 H4 VMA_DQ49
VMA_MA2 A1 DQL4 VMA_DQ16 VMA_MA2 A1 DQL4 VMA_DQ28 VMA_MA2 A1 DQL4 VMA_DQ33 VMA_MA2 A1 DQL4 VMA_DQ51
P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9 P4 A2 DQL5 H9
VMA_MA3 N3 G3 VMA_DQ21 VMA_MA3 N3 G3 VMA_DQ24 VMA_MA3 N3 G3 VMA_DQ37 VMA_MA3 N3 G3 VMA_DQ50
VMA_MA4 A3 DQL6 VMA_DQ19 VMA_MA4 A3 DQL6 VMA_DQ26 VMA_MA4 A3 DQL6 VMA_DQ35 VMA_MA4 A3 DQL6 VMA_DQ55
P9 H8 P9 H8 P9 H8 P9 H8
VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7 VMA_MA5 A4 DQL7
P3 P3 P3 P3
D VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 D
R9 R9 R9 R9
VMA_MA7 A6 VMA_DQ0 VMA_MA7 A6 VMA_DQ15 VMA_MA7 A6 VMA_DQ43 VMA_MA7 A6 VMA_DQ60
R3 D8 R3 D8 R3 D8 R3 D8
VMA_MA8 A7 DQU0 VMA_DQ5 VMA_MA8 A7 DQU0 VMA_DQ10 VMA_MA8 A7 DQU0 VMA_DQ44 VMA_MA8 A7 DQU0 VMA_DQ58
T9 C4 T9 C4 T9 C4 T9 C4
VMA_MA9 A8 DQU1 VMA_DQ1 VMA_MA9 A8 DQU1 VMA_DQ13 VMA_MA9 A8 DQU1 VMA_DQ40 VMA_MA9 A8 DQU1 VMA_DQ63
R4 C9 R4 C9 R4 C9 R4 C9
VMA_MA10 A9 DQU2 VMA_DQ4 VMA_MA10 A9 DQU2 VMA_DQ9 VMA_MA10 A9 DQU2 VMA_DQ47 VMA_MA10 A9 DQU2 VMA_DQ56
L8 C3 L8 C3 L8 C3 L8 C3
VMA_MA11 A10/AP DQU3 VMA_DQ2 VMA_MA11 A10/AP DQU3 VMA_DQ12 VMA_MA11 A10/AP DQU3 VMA_DQ42 VMA_MA11 A10/AP DQU3 VMA_DQ61
R8 A8 R8 A8 R8 A8 R8 A8
VMA_MA12 A11 DQU4 VMA_DQ7 VMA_MA12 A11 DQU4 VMA_DQ8 VMA_MA12 A11 DQU4 VMA_DQ45 VMA_MA12 A11 DQU4 VMA_DQ57
N8 A3 N8 A3 N8 A3 N8 A3
VMA_MA13 A12/BC DQU5 VMA_DQ3 VMA_MA13 A12/BC DQU5 VMA_DQ14 VMA_MA13 A12/BC DQU5 VMA_DQ41 VMA_MA13 A12/BC DQU5 VMA_DQ62
T4 B9 T4 B9 T4 B9 T4 B9
A13 DQU6 VMA_DQ6 A13 DQU6 VMA_DQ11 A13 DQU6 VMA_DQ46 A13 DQU6 VMA_DQ59
T8 A4 T8 A4 T8 A4 T8 A4
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M8 M8 M8 M8
A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA A15/BA3 +1.5V_VGA

M3 B3 VMA_BA0 M3 B3 VMA_BA0 M3 B3 VMA_BA0 M3 B3


[18] VMA_BA0 BA0 VDD#B3 BA0 VDD#B3 BA0 VDD#B3 BA0 VDD#B3
N9 D10 VMA_BA1 N9 D10 VMA_BA1 N9 D10 VMA_BA1 N9 D10
[18] VMA_BA1 BA1 VDD#D10 VMA_BA2 BA1 VDD#D10 VMA_BA2 BA1 VDD#D10 VMA_BA2 BA1 VDD#D10
[18] VMA_BA2 M4 BA2 VDD#G8 G8 M4 BA2 VDD#G8 G8 M4 BA2 VDD#G8 G8 M4 BA2 VDD#G8 G8
VDD#K3 K3 VDD#K3 K3 VDD#K3 K3 VDD#K3 K3
VDD#K9 K9 VDD#K9 K9 VDD#K9 K9 VDD#K9 K9
VDD#N2 N2 VDD#N2 N2 VDD#N2 N2 VDD#N2 N2
J8 N10 VMA_CLK0 J8 N10 J8 N10 VMA_CLK1 J8 N10
[18] VMA_CLK0 CK VDD#N10 VMA_CLK0# CK VDD#N10 [18] VMA_CLK1 CK VDD#N10 VMA_CLK1# CK VDD#N10
[18] VMA_CLK0# K8 R2 K8 R2 [18] VMA_CLK1# K8 R2 K8 R2
CK VDD#R2 VMA_CKE0 CK VDD#R2 CK VDD#R2 VMA_CKE1 CK VDD#R2
[18] VMA_CKE0 K10 CKE/CKE0 VDD#R10 R10 K10 CKE/CKE0 VDD#R10 R10 [18] VMA_CKE1 K10 CKE/CKE0 VDD#R10 R10 K10 CKE/CKE0 VDD#R10 R10
+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA

K2 A2 VMA_ODT0 K2 A2 K2 A2 VMA_ODT1 K2 A2
[18] VMA_ODT0 ODT/ODT0 VDDQ#A2 VMA_CS0# ODT/ODT0 VDDQ#A2 [18] VMA_ODT1 ODT/ODT0 VDDQ#A2 VMA_CS1# ODT/ODT0 VDDQ#A2
[18] VMA_CS0# L3 A9 L3 A9 [18] VMA_CS1# L3 A9 L3 A9
CS /CS0 VDDQ#A9 VMA_RAS0# CS /CS0 VDDQ#A9 CS /CS0 VDDQ#A9 VMA_RAS1# CS /CS0 VDDQ#A9
[18] VMA_RAS0# J4 RAS VDDQ#C2 C2 J4 RAS VDDQ#C2 C2 [18] VMA_RAS1# J4 RAS VDDQ#C2 C2 J4 RAS VDDQ#C2 C2
K4 C10 VMA_CAS0# K4 C10 K4 C10 VMA_CAS1# K4 C10
[18] VMA_CAS0# CAS VDDQ#C10 VMA_WE0# CAS VDDQ#C10 [18] VMA_CAS1# CAS VDDQ#C10 VMA_WE1# CAS VDDQ#C10
[18] VMA_WE0# L4 WE VDDQ#D3 D3 L4 WE VDDQ#D3 D3 [18] VMA_WE1# L4 WE VDDQ#D3 D3 L4 WE VDDQ#D3 D3
VDDQ#E10 E10 VDDQ#E10 E10 VDDQ#E10 E10 VDDQ#E10 E10
VDDQ#F2 F2 VDDQ#F2 F2 VDDQ#F2 F2 VDDQ#F2 F2
VMA_RDQS2 F4 H3 VMA_RDQS3 F4 H3 VMA_RDQS4 F4 H3 VMA_RDQS6 F4 H3
VMA_RDQS0 DQSL VDDQ#H3 VMA_RDQS1 DQSL VDDQ#H3 VMA_RDQS5 DQSL VDDQ#H3 VMA_RDQS7 DQSL VDDQ#H3
C8 DQSU VDDQ#H10 H10 C8 DQSU VDDQ#H10 H10 C8 DQSU VDDQ#H10 H10 C8 DQSU VDDQ#H10 H10
C C

VMA_DM2 E8 A10 VMA_DM3 E8 A10 VMA_DM4 E8 A10 VMA_DM6 E8 A10


VMA_DM0 DML VSS#A10 VMA_DM1 DML VSS#A10 VMA_DM5 DML VSS#A10 VMA_DM7 DML VSS#A10
D4 DMU VSS#B4 B4 D4 DMU VSS#B4 B4 D4 DMU VSS#B4 B4 D4 DMU VSS#B4 B4
VSS#E2 E2 VSS#E2 E2 VSS#E2 E2 VSS#E2 E2
VSS#G9 G9 VSS#G9 G9 VSS#G9 G9 VSS#G9 G9
VMA_WDQS2 G4 J3 VMA_WDQS3 G4 J3 VMA_WDQS4 G4 J3 VMA_WDQS6 G4 J3
VMA_WDQS0 DQSL VSS#J3 VMA_WDQS1 DQSL VSS#J3 VMA_WDQS5 DQSL VSS#J3 VMA_WDQS7 DQSL VSS#J3
B8 J9 B8 J9 B8 J9 B8 J9
DQSU VSS#J9 DQSU VSS#J9 DQSU VSS#J9 DQSU VSS#J9
M2 M2 M2 M2
VSS#M2 VSS#M2 VSS#M2 VSS#M2
M10 M10 M10 M10
VSS#M10 VSS#M10 VSS#M10 VSS#M10
P2 P2 P2 P2
VSS#P2 DRAM_RST_M T3 VSS#P2 DRAM_RST_M T3 VSS#P2 DRAM_RST_M T3 VSS#P2
[18] DRAM_RST_M T3 P10 P10 P10 P10
RESET VSS#P10 RESET VSS#P10 RESET VSS#P10 RESET VSS#P10
T2 T2 T2 T2
VMA_ZQ1 VSS#T2 VMA_ZQ2 VSS#T2 VMA_ZQ3 VSS#T2 VMA_ZQ4 VSS#T2
L9 T10 L9 T10 L9 T10 L9 T10
ZQ/ZQ0 VSS#T10 ZQ/ZQ0 VSS#T10 ZQ/ZQ0 VSS#T10 ZQ/ZQ0 VSS#T10
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% A1 B2 Ohms +-1% A1 B2 Ohms +-1% A1 B2 Ohms +-1% A1 B2
NC VSSQ#B2 NC VSSQ#B2 NC VSSQ#B2 NC VSSQ#B2
T1 B10 T1 B10 T1 B10 T1 B10
R115 NC VSSQ#B10 R326 NC VSSQ#B10 R63 NC VSSQ#B10 R242 NC VSSQ#B10
A11 D2 A11 D2 A11 D2 A11 D2
NC VSSQ#D2 NC VSSQ#D2 NC VSSQ#D2 NC VSSQ#D2
243/F_4 T11 D9 243/F_4 T11 D9 243/F_4 T11 D9 243/F_4 T11 D9
NC VSSQ#D9 NC VSSQ#D9 NC VSSQ#D9 NC VSSQ#D9
E3 E3 E3 E3
VSSQ#E3 VSSQ#E3 VSSQ#E3 VSSQ#E3
J2 E9 J2 E9 J2 E9 J2 E9
NC/ODT1 VSSQ#E9 NC/ODT1 VSSQ#E9 NC/ODT1 VSSQ#E9 NC/ODT1 VSSQ#E9
L2 F10 L2 F10 L2 F10 L2 F10
NC/CS1 VSSQ#F10 NC/CS1 VSSQ#F10 NC/CS1 VSSQ#F10 NC/CS1 VSSQ#F10
J10 G2 J10 G2 J10 G2 J10 G2
NC/CE1 VSSQ#G2 NC/CE1 VSSQ#G2 NC/CE1 VSSQ#G2 NC/CE1 VSSQ#G2
L10 G10 L10 G10 L10 G10 L10 G10
NC/ZQ1 VSSQ#G10 NC/ZQ1 VSSQ#G10 NC/ZQ1 VSSQ#G10 NC/ZQ1 VSSQ#G10
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
H5TQ4G63MFR-11C H5TQ4G63MFR-11C H5TQ4G63MFR-11C H5TQ4G63MFR-11C

+1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA +1.5V_VGA


B B

R338 R328 R330 R119 R62 R23 R243 R308


4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4

R339 R327 R329 R118 R64 R22 R244 R307


4.99K/F_4 C670 4.99K/F_4 C617 4.99K/F_4 C619 4.99K/F_4 C662 4.99K/F_4 C70 4.99K/F_4 C26 4.99K/F_4 C517 4.99K/F_4 C571
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4

+1.5V_VGA [17,18,34]
VMA_CLK0 +1.5V_VGA +1.5V_VGA

R117
56.2/F_4
QCI PN
C578 C47 C606 C183 C72 C582 C38 C666 C616 C570 C614 C514 C513 C669 C512 C615
C187
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
VMA_CLK0_COMM
SAM 2G AKD5MGWT500

R116 0.01U/25V_4 +1.5V_VGA +1.5V_VGA HYU 2G AKD5MGWTW00


56.2/F_4
SAMSUNG AKD5EGGT500
VMA_CLK0#
A VMA_CLK1 C569 C136 C135 C133 C515 C516 C132 C134 C661 C667 C668 C663 C664 C665 C186 C185 A
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
HYNIX AKD5LZWTW02
R25
56.2/F_4
+1.5V_VGA +1.5V_VGA
C27
VMA_CLK1_COMM
PROJECT : U56
R24 0.01U/25V_4 C43 C40 C643 C120 C563 C23 C612 C611 C51 C639 C24 C641
Quanta Computer Inc.
56.2/F_4 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6
Size Document Number Rev
Custom Mars S3 VRAM(DDR3 BGA96) 1A
VMA_CLK1# NB5 Date: Tuesday, August 07, 2012 Sheet 19 of 39
5 4 3 2 1
A B C D E

+5VAVDD
U26
+5V
+5V_AVDD1 L51 *0_6/S +5VAVDD
20
5 1 C774 C791 C789 C779
Vout Vin *10U/6.3VS_6 10U/6.3VS_6 1U/6.3V_4 0.1U/10V_4
4 BYP
C773 C771 C49 C768 C769
2.2U/6.3V_6 0.1U/10V_4 2 3 0.1U/10V_4 0.047U/10V_4 1U/6.3V_4
C770 GND EN
4 1U/6.3V_4 TPS793475DBVR Close to CODEC 4
AGND
AGND AGND
AGND R435 10K_4 +5V +5V
Vset=1.242V >40mils trace

+3V_DVDD_CORE

C499
10U/6.3VS_6
C30 C406 C765 C766
0.1U/10V_4 0.1U/10V_4 10U/6.3VS_6 10U/6.3VS_6

+3V R449 *0_4/S


U27
Close to CODEC
C787 C788
1 DVDD_LV AVDD1 21
32 SPK trace width Internal Speaker
1U/6.3V_4 0.1U/10V_4 AVDD2
7 33
DVDD PVDD1
PVDD2 39 Speaker 4 ohm: 40mils
INT SPEAKER CONN
L_SPK+ L12 TI160808U600 L_SPK+_R
L_SPK- L13 TI160808U600 L_SPK-_R 1
PVSS 36 2

Digital
[6] BIT_CLK_AUDIO R447 *0_4/S HD_BCLK 5 R_SPK- L14 TI160808U600 R_SPK-_R
HDA_BCLK R_SPK+ L15 TI160808U600 R_SPK+_R 3
D21 4
[6] ACZ_SDOUT_AUDIO R445 *0_4/S HD_SDOUT 4 34 L_SPK+
C785 *10P/50V_4 HDA_DOUT PORTD_+L L_SPK- EXT_MIC_R VREFOUT_C_L R451 2.2K/F_4 CN3
PORTD_-L 35 1 2 VREFOUT_C
3 33_4 HD_SDIN0 6 3
[6] ACZ_SDIN0 HDA_DIN C775
R448 C796 R436
R450 *0_4/S HD_SYNC RB501V-40 1U/6.3V_4 3.3/F_4
[6] ACZ_SYNC_AUDIO 8 HDA_SYNC
C790 *10P/50V_4 38 R_SPK+ C106 C107 C108 C109
PORTD_+R C776
[6] ACZ_RST#_AUDIO ACZ_RST#_AUDIO 9 R437
HDA_RST# R_SPK- AGND 2200P/50V_4 3.3/F_4 680P/50V_4 680P/50V_4 680P/50V_4 680P/50V_4
PORTD_-R 37
R440 2.49K/F_4 SENSE_A
+5V_AVDD1 C777
R438
C767 1000P/50V_4 EXT_MIC_L1 C786 2.2U/6.3V_6 2200P/50V_4 3.3/F_4
AGND PORT_A_L 22
11 23 EXT_MIC_R1 R446 *0_4/S EXT_MIC_R
SENSE_A PORT_A_R C778
SENSE_B VREFOUT_C
+5V_AVDD1 R455 10K_4 12 SENSE_B VREFOUT_A 19
2200P/50V_4
R439 6/21/2012 for EMI
AGND 3.3/F_4
C794 *1000P/50V_4
C783 10P/50V_4 2 DMIC_CLK/GPIO1 EARP_L1 R444 16/F_4 EARP_L 2200P/50V_4
PORTB_L 25
[27] DIGITAL_CLK R441 100_4 DMIC_CLK_R 3 26 EARP_R1 R442 16/F_4 EARP_R
DMIC0/GPIO2 PORTB_R
R443 *0_4/S DMIC0 40 EAPD MUTE_LED_CNTL MUTE_LED_CNTL [23]
PORTC_L 15
C784 10P/50V_4 16 +5V_AVDD1
[27] DIGITAL_D1 PORTC_R

+3V R234 10K_4 20 R453


VREFOUT_C/GPIO4 10K_4
29 CAP-
[26] VOLMUTE# C793 check value C798
0.1U/10V_4 0.1U/10V_4
D11 RB500V-40 30 AMP_BEEP_L R454 AMP_BEEP_R2
100K/F_4
CAP- CAP+
Analog PORT_F_L 13

3
PORT_F_R 14
EC13
2 *220P/50V_4 C781 R452 2
4.7U/6.3V_6 10 AMP_BEEP