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USN9810 Hardware & Software System

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 The Huawei LTE/SAE solution provides the following functions:


 Supporting the convergence of various 3GPP wireless networks (GERAN, UTRAN, and E-
UTRAN)
 Supporting EPS and compatibility with GPRS protocols and service functions
 Supporting the access of non-3GPP networks (CDMA2000 HRPD network) through the
Mobile IP technology

 PCRF: policy control and charging rules function


 HSGW: HRPD serving gateway
 PDSN: packet data service node
 GERAN: GSM/EDGE Radio Access Network
 UTRAN: UMTS Terrestrial Radio Access Network
 E-UTRAN: Evolved UMTS Terrestrial Radio Access Network (LTE)

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 The USN9810 uses the N68-22E cabinet.


 Dimensions (WxHxD): 600 mm x 800 mm x 2200 mm
 Available space inside the cabinet: 46 U (1 U = 44.45 mm)
 Number of OSTA2.0 subracks: 3
 Weight: 365 kg (full configuration) and 100 kg (empty)

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 The two types of hardware cannot be used together within a subrack or between different
subracks in a cabinet.
 The detailed difference is described in the related chapter.

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 According to service requirements, subracks are classified into the basic subrack and
extension subrack.
 The basic subrack is mandatory and configured in the integrated configuration cabinet.
The basic subrack provides complete service processing functions and external interfaces.
 The extension subrack indicates the service processing subrack selected based on user
capacity requirements. The service processing subrack cooperates with the basic subrack to
process services.
 You can set the subrack number using the DIP switches on the SDM. The SMM obtains the
subrack number by reading the DIP switch information on the SDM. The subrack
numbering rules are as follows:
 Each subrack is allocated a subrack number. The basic subrack is numbered 0.
 The subracks inside the cabinet are numbered based on the installation position from
bottom to top.
 The subracks between cabinets are numbered based on the cabinet number in ascending
order.

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 Interface board slot: Boards are inserted to the rear boards (IO boards) from the rear.
 When the interface board is a passive board, a front board is required before the interface
board is powered on. Boards are inserted to the rear boards and then the front boards.
Then, you can power on the boards.

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 The internal ports and buses communicate with each other over the backplane.
 Quantity and position: A subrack provides a backplane that is located between the front
board and rear board in a subrack.
 Function: The backplane implements the communication between interfaces of boards.

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 The T8280 fan assembly uses the integrated and dual-layer design. That is, two fan
assemblies are configured in each subrack to avoid heat dissipation problems due to single
point of failure. The fans support N+1 redundancy mode. When a fan fails, the system
performance is not affected.

 When a fan fails, the system heat dissipation is not affected. An alarm indicating a fan
failure is reported. To avoid the overheat problem, you must complete fan replacement
within three minutes.
 When the temperature is too high, the SMM forcibly powers off certain server boards.

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 As shown in the figure, the subrack provides 14 service slots in total. Slots 6-7 host the
SWUs and other slots host the UPBs.
 Dimensions of the front board: 355.6 mm x 280 mm x 30.5 mm
 Dimensions of the rear board: 355.6 mm x 70 mm x 30.5 mm
 Two USN9810 boards installed in inconsecutive slots work in an active/standby
mode. Enhanced packet forward unit (EPU/EPUB) boards use the update buses.
According to the ATCA platform, the update bus requires board installation in
consecutive slots. The Enhanced Control Plane Units (ECUs) and OMUs do not use
the update bus. To ensure consistency, the ECUs and OMUs are inserted in
consecutive slots.

 Active/standby boards installed in inconsecutive slots can avoid power failure of a board
when the adjacent board is incorrectly inserted to or plugged out from a slot.

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 According to the power distribution block capability, each PEM can provide power for the
entire subrack.
 Note that the maximum power mentioned here indicates the maximum power supported
by the subrack rather than the maximum power of the subrack in full configuration.
 Each power input module provides two binding posts that can connect two power inputs.

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 Specifications: The input voltage of the power distribution box is –48 V DC or –60 V DC
power. Each power input supports the maximum 100 A current. With the processing of
internal lightning protection and overcurrent protection, the power distribution box
generates two 10-channel –48 V DC power. The maximum current of single channel
power is 50 A.

 Currently, the USN9810 supports dual-channel, dual 2-channel, and dual 3-channel power
distribution boxes. The appearance of these power distribution boxes is the same. The
difference is as below: The extra input terminals on the rear panels of the dual-channel and
dual 2-channel are sealed up using filler panels.

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 Note: Fans in the subrack are not separately described, but described together with the
subrack.

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 The T8290 subrack interworks with the ESU. The overall hardware structure of T8290 is
similar to that of the T8280.

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 The mapping between output of each line and the subrack is related to the power supply
solution. For details, see the related chapters of the product description documents.

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 The figure on the left side shows the connection between the power distribution box and
the subracks under the default setting. You are advised to confirm the connections before
powering on or off a subrack.

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 By default, different PEMs in the same subrack are connected to different PDB output
areas. That is, different terminals in the same PDB output area are connected to different
subracks. The three lines of current input in the subrack come from the line 4, line 7, and
line 10 of the PDB as shown in the figure on the left.

 Advantage: PEMs of the same type in different subracks share the same 100 A input, and
the current can be coordinated among the subracks, which reduces the impact of power
consumption fluctuation in a single subrack.

 The default cable connection of the PDB may be modified based on the different power
distribution requirements of the specific project. For details, see the follow-up description
of each power supply solution.

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 The designed maximum power consumption of the T8290 subrack is 6000 W. The
USN9810 T8290 or ESU architecture consumes a maximum power of only 3500 W.

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 The USN9810 boards are classified into the following types based on the logical functions.
 1. The UPB is classified into the following types:
 OMU: The OMU implements system configuration, maintenance, alarm management, and
performance management functions.
 ECU: The ECU processes the control plane-related services and charging.
 EPU: The EPU processes the user plane-related services.
 EPUB: The EPUB processes the user plane-related services.
 EVU: The EVU processes the value added services.

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 2. The USI is classified into the following types:


 USI: As a rear board of the OMU, the USI provides precise time and maintenance GE
interfaces.
 ETI: As a rear board of the ECU, the ETI provides E1/T1 interfaces for the Gb interfaces, SS7
interfaces, and subsequently-expanded IP over E1 interfaces.
 PFI: As a rear board of the EPU/EPUB, the PFI interworks with the interface subboards to
provide the access functions for broadband interfaces such as ATM, POS, and GE interfaces.
A PFI supports two interface subboards. The interface subboards can be ATM interface
subboard (AIC), Ethernet electrical interface subrack (EEC), and Ethernet optical interface
subrack (EFC).
 3. The SWI is classified into the following types:
 TMI: The TMI is located at the basic subrack used for inter-subrack cascading and
implements clock distribution.
 TSI: The TSI is located at the basic subrack used for inter-subrack cascading and
implements clock receiving.

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 2. The USI is classified into the following types:


 USI: As a rear board of the OMU, the USI provides precise time and maintenance GE
interfaces.
 ETI: As a rear board of the ECU, the ETI provides E1/T1 interfaces for the Gb interfaces, SS7
interfaces, and subsequently-expanded IP over E1 interfaces.
 PFI: As a rear board of the EPU/EPUB, the PFI interworks with the interface subboards to
provide the access functions for broadband interfaces such as ATM, POS, and GE interfaces.
A PFI supports two interface subboards. The interface subboards can be ATM interface
subboard (AIC), Ethernet electrical interface subrack (EEC), and Ethernet optical interface
subrack (EFC).
 3. The SWI is classified into the following types:
 TMI: The TMI is located at the basic subrack used for inter-subrack cascading and
implements clock distribution.
 TSI: The TSI is located at the basic subrack used for inter-subrack cascading and
implements clock receiving.

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 The subrack provides 14 vertical-insertion slots numbered from 0 to 13. The subrack also
provides 2 horizontal-insertion slots numbered 14 and 15 at the bottom of the subrack.
 The SMM, SDM, SWU, and SWI are mandatory for each subrack. Each subrack is
configured with two SMMs, SDMs, SWUs, and SWIs to achieve the active/standby work
mode.
 The SMM and SDM are permanently installed in the horizontal-insertion slots on the
bottom of the subrack. The SMM works as a front board and SDM works as a rear board.
 The boards installed in the vertical-insertion slots must be inserted in consecutive slots.
Slots 0 and 2, slots 1 and 3, slots 4 and 8, slots 5 and 9, slots 10 and 12, and slots 11 and
13 are mutually consecutive slots.
 The SWU and SWI are permanently installed in slots 6 and 7 of each subrack.
 The OMUs are permanently installed in slots 0 and 2 of the basic slot.
 Other UPBs and USIs are installed in the basic subrack and extension subrack according to
the delivery requirements.

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 The device management module consists of SMMs and SDMs. The SMM is located at the
front bottom of the subrack and the SDM is located at the rear bottom of the subrack.
They both are under the fan box.
 The device management module manages all the devices in the subrack (including the
external power distribution boxes of the subrack) in a unified manner.

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 SMM: Shelf Management Module.


 Function:
 The SMM manages all the hardware devices in the subrack.
 The SMM implements functions such as device, hot-swap, alarm, log, inventory,
and power management.
 The SMM supports the KVM Over IP function.
 The SMM is located at the rear bottom of the subrack and it has two slots. The
SMM works in the 1+1 active-standby mode. The active SMM and standby SMM
are connected by dedicated Intelligent Platform Management Bus (IPMB) and
network ports for synchronizing data.
 The USN9810 V900R011C02 version adds SMME that can smoothly replace SMMD. SMME
and SMMD have different exteriors.
 These two ejector levers are matched with two sensors and work only when opened or
closed at the same time.

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 SDM: The SDM is the shelf data module.


 Function:

 The SDM records the asset information of the subrack (subrack name, BOM code,
manufacturer, and delivery date) and slot address information.
 The SMM obtains data from the SDM to manage all the hardware devices in the
system.
 The SDM is located at the rear bottom of the subrack and works as the rear board
of the SMM. The SDMs work in active/standby mode.
 Port:

 The SDM provides a network port and an RS232 serial port (COM1) on the front
panel for O&M. The SDM provides an RS485 serial port (COM2) that is connected
to the power distribution box of the subrack to maintain and manage the power
distribution box.

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 The SDM ejector levers are used to plug or fix SDMs. The ejector levers cannot be used to
power on or power off the SDMs. One of the active and standby SMMs can be used to
provide power for the SDMs.

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 The physical boards of the OMU are classified into UPBA2 and UPBA6.
 The OMU implements system configuration, maintenance, alarm management, and
performance management functions.
 This section uses the UPBA2 as an example to introduce the OMU.
 The OMU supports powerful processing capability and works as a hardware carrier
for service running. The full configuration of the OMU is as follows:
 CPU: Two Intel low-power consumption 4-core processors are used. The 4-core
processors support 12 MB L2 cache and 1333 MHz front side bus (FSB). The CPU
provides a transmission rate of 21 Gbit/s.
 Memory: Six DDR2 RDIMM memories with 24 GB in total are used. Each memory
supports 4 GB dual ranks and ECC. The highest work frequency is 667 MHz. The
memories are compatible with 533 MHz VLR DDR2 RDIMM backwards.
 Hard disk: Two hot swappable 2.5-inch SASs are used. The hard disk capacity is 73
GB or 146 GB. The hard disks are configured before they are delivered to the sites.
The hard disks of the OMU use the RAID 1 technology. Two hard disks work in
mirroring mode.
 Subboard: none

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 The USI works as the interface board of the OMU and provides external ports.
 The external ports are as follows:
 One USB port: connecting to the KVM
 One VGA port: connecting to the display.
 More than four GE ports

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 The switching module consists of SMUs and SWIs located at slots 6 and 7 of the subrack.
 The SMUs exchange data over the Base plane and Fabric GE plane.
 The SWIs provide external ports for cascading over the Base plane and GE Fabric plane.

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 Base plane:
 12 network ports: connecting to 12 UPB slots
 2 network ports: connecting to the active and standby SMMs
 1 network port: connecting to the Base plane of another SWU to implement
redundancy on the Base plane
 8 network ports: working as external network ports over the SWI
 GE Fabric plane:
 12 network ports: connecting to 12 UPB slots
 1 network port: connecting to the Fabric plane of another SWU to implement
redundancy on the Fabric plane
 8 network ports: working as external network ports over the SWI
 Based on different installation positions, the SMU is classified into SWUA0 and SWUA1
(the SWUA0 is used in the service subrack and the SWUA1 is used in the basic subrack).
The physical specifications of the SWUA0 and SWUA1 are the same. The only difference is
that the SWUA1 requires a TDM subboard.

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 The SWIA1 is an interface board of the SFU and must be used with the SFU. The SWIA1 is
installed in slots 6 and 7 at the rear of the subrack. The SWIA1 provides external service
ports and cascading ports for the SFU. The TMI is configured in the basic subrack for
cascading or in other subracks to perform clock collection and distribution.
 The SWIA1 supports the following functions:
 The SWIA1 provides eight 10/100/1000 Mbit/s BASE-T cascading ports on the Base plane
to transmit Base-plane cascading and TDM clock cascading data.
 The SWIA1 provides two line clock inputs and one BITS clock input.
 The SWIA1 supports 2-level and 3-level clock modules.
 As a manageable module, the SWIA1 is uniformly managed by the BMC. The SWIA1 can
monitor the voltage, temperature, and work status of the SWIA0 and store the information
about field replaceable unit (FRU), system event log (SEL), and sensor data record (SDR).

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 The SWIA0 is an interface board of the SFU and must be used with the SFU. The SWIA0 is
installed in slots 6 and 7 at the rear of the subrack. The SWIA0 provides external service
ports and cascading ports for the SFU.
 The SWIA0 supports the following functions:
 The SWIA0 provides eight 1000 Mbit/s BASE-T cascading ports on the Base plane to
transmit Base-plane cascading and TDM clock cascading data.
 The SWIA0 provides eight 10/100/1000 Mbit/s BASE-T cascading ports on the GE Fabric
plane.
 As a manageable module, the SWIA1 is uniformly managed by the BMC. The SWIA1 can
monitor the voltage, temperature, and work status of the SWIA0 and store the information
about the FRU, SEL, and SDR.

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 The USN9810 UPB is classified into UPBA2/UPBA6 (OMU) and UPBA3 (ECU).

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 The UPB is the universal process blade.


 The ECU processes the control plane-related services and charging.

 CPU: The ECU uses two Intel® Xeon® low power consumption and 4-core processors. The 4-core
processors support 4 MB L2 cache and 1333 MHz FSB. The CPU provides a transmission rate of
21 Gbit/s.
 Memory: The ECU uses six FBDIMM DDR2 memories. The total capacity is 24 GB. Each memory
supports 4 GB capacity. The memories support ECC. The highest work frequency is 667 MHz.
 Hard disk: The ECU supports two hot swappable 2.5-inch SASs. Generally, only a hard disk is
configured for the ECU.
 Subboard: none
 The ECU is classified into CN21UPBA3 and CN22UPBA3. The configuration of the CN21UPBA3 is
described above. The configuration of the CN22UPBA3 is as follows:
 CPU: The CN22UPBA3 supports an Intel@ Westmere 6-core processor and 64-bit QuickPath
Interconnect (QPI) data bus. The highest data transmission rate is 64 Gbit/s.
 Memory: The CN22UPBA3 supports a maximum of 96 GB capacity. Actually 24 GB capacity is
configured (6 DDR3 RDIMMs). The memory supports the error checking correcting (ECC) function.
The memory supports the DDR3 RDIMM with the highest work frequency 1066 MHz.
 Hard disk: The CN22UPBA3 supports two 2.5-inch SASs. Actually a hot swappable 2.5-inch SSD is
configured. The hard disk capacity is 64 GB and is configured before delivery.
 Subboard: none

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 The ETIA0 provides the following functions:


 Provide E1/T1 ports.
 Process narrowband services.
 Process TDM services and signaling.
 Provide clock reference.
 Support hot swapping.
 Support GEA1/GEA2/GEA3 encryption.

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 Function:
 1. Each TSCA supports the mapping from 63 E1 or 84 E1s to the STM-1.
 2. Each SSIA2 consists of a TSCA and an ETMA. The SSIA2 provides an external
channelized optical port and an E/1T1 port.
 3. The SSIA2 provides the line clock extraction function and sends the clock
signals to the SFU over the clock port on the panel.
 4. The SSIA2 supports hot swapping.

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 Function:
 Each TSCA supports the STM-1 payload mapping of 63 E1 or 84 T1 ports.
 Each TSCA supports two channelized STM-1 interfaces and one is used to enable
transmission over SDH through E1/T1 interfaces.
 The SSIA0 provides the line clock extraction function and sends the clock signals to
the SFU over the clock port on the panel.
 The SSIA0 supports hot swap.
 The SSIA0 provides the GEA1, GEA2, and GEA3 encryption functions.

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 Processing functions:

 The MSPB0 supports a multi-core processor that uses the multi-core and multi-thread architecture.

 The MSPB0 supports two DIMM memory boards. The capacity of each memory board is 4 GB. The capacity of the
board memory is 8 GB.
 Interface functions:

 The MSPB0 provides two Ethernet 10/100/1000 Mbit/s Base-T Base ports.

 The MSPB0 provides two Ethernet 1000M Base-B Fabric ports.

 The MSPB0 provides one Ethernet 2.5 Gbit/s SerDes X 4 Update port.

 The MSPB0 provides a commissioning network port.

 The MSPB0 provides six SerDes ports that connect to the RPUA.
 Management functions:

 The MSPB0 provides the BMC module that uses independent power supply. The BMC module connects to the
SMM over the redundancy IPMB.
 The BMC module supports the following functions:

 FRU, SDR, and SEL management

 Temperature, voltage detection, and alarm

 Hot swapping control, power-on/power-off control, and reset control

 Online software loading

 Serial over LAN (SOL)

 Integration

 Dual-channel GE controller

 IPMI

 Hot swapping

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 Supports one Intel® Xeon six-core Westmere-EP processor with full power consumption
 Provides six DDR3 registered dual in-line memory module (RDIMM) memory slots. The total
capacity is 24 GB.
 Two 10/100/1000 M BASE-T Ethernet Base interfaces connecting to the backplane and
used for communicating with the switch blades, supporting boards started from the
network.
 Two 20 G RXAUI Ethernet Fabric interfaces connecting to the backplane and used for
communicating with the switch blades
 One update interface connecting to the backplane and used for communicating with other
processor boards. Data types can be customized.
 Four 10 Gbit/s transmission channels connecting to the interface boards for connecting
external devices
 Four 1 Gbit/s transmission channels connecting to the interface boards for connecting
external devices
 Provides one serial advanced technology attachment (SATA) port for connecting one solid-
state drive (SSD).

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 The PFIA0 supports hot swapping. The PFIA0 supports three types of subboards, namely,
AICA, EECA, and EFCA.
 The AICI provides the following functions:
 The AICI provides four swappable SFP LC optical ports. You can select the STM-1 or STM-4
optical modules based on actual situations. The AICI supports two combinations of links,
namely, (4xSTM-1) and (2xSTM-4+2xSTM-1).
 The AICI converts the SDH/SONET frames and ATM cells so that ATM messages are
transmitted over the SDH/SONET network.
 The AICI provides the ATM physical-layer functions or PPP over SDH/SONET physical-layer
functions.
 The AICI provides 8 kHz synchronization clock source.
 The EECA provides four external 10 M/100 M/1000 M Ethernet electrical ports.
 The EFCA provides four external 1000 M Ethernet optical ports.

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 The features of the ESU are as follows:


 Integrates control and forwarding functions.
 Possesses strong service processing and forwarding capability.
 Supports all types of rear boards that can interwork with the ECU or EPU.
 Supports QXI and provides the 10 GE interface.
 Hardware description
 Supports one Intel® Xeon six-core Westmere-EP processor with full power consumption
 Provides six DDR3 registered dual in-line memory module (RDIMM) memory slots. Each RDIMM
providing the capacity of 8 GB, with the maximum total capacity of 48 GB.
 Two 10/100/1000 M BASE-T Ethernet Base interfaces connecting to the backplane and used for
communicating with the switch blades, supporting boards started from the network.
 Two 20 G RXAUI Ethernet Fabric interfaces connecting to the backplane and used for
communicating with the switch blades
 One update interface connecting to the backplane and used for communicating with other
processor boards. Data types can be customized.
 Four 10 Gbit/s transmission channels connecting to the interface boards for connecting external
devices
 Four 1 Gbit/s transmission channels connecting to the interface boards for connecting external
devices
 Provides one serial advanced technology attachment (SATA) port for connecting one solid-state
drive (SSD).

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 Processing functions
 Supports two Intel® Xeon™ eight-core Haswell-EP CPUs with full power
consumption.
 Supports two QuickPath interconnect (QPI) full-width ports, providing the
maximum data transmission rate of 9.6 GT/s.
 Provides 10 memory slots and supports eight double data rate 4 (DDR4), 1866
MHz, 16 GB registered dual in-line memory modules (RDIMMs), with the maximum
memory capacity of 128 GB.
 Supports error checking and correcting (ECC).
 Interface features
 Two GE Base ports for connecting to the switch unit Base plane through the
backplane
 Two 20GE Fabric ports
 One 8*6.25GE Serdes Update port for connecting to the backplane and
communicating with other server boards
 One baseboard management controller (BMC) serial port (also serving as the
system serial port) on the front panel, complying with RS232 specifications and
using the RJ45 connector.
 One onboard USB 2.0 port (compatible with USB 1.1).

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 The QXI provides external interfaces for the ESU to connect to external devices. The QXI
provides four GE and four10 GE external interfaces to transmit data to other external
devices.

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 The QXIB0 provides ports for universal forwarding and control board to connect to
external devices. The QXIB0 has the following features: The QXIB0 supports hot swap.
 The QXIB0 is managed by the baseboard management controller (BMC) of the universal
forwarding and control board. The management functions are as follows:
 Monitors the QXIB0 running status
 Stores the field replaceable unit (FRU) information, sensor data records (SDRs), and
system event logs (SELs) of the QXIB0
 Manages the indicators and ejector levers of the QXIB0
 The QXIB0 provides four gigabit Ethernet (GE) ports and four 10 GE ports for the universal
forwarding and control board to transmit data to external devices.

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 Supports an Intel Xeon six-core Westmere processor with full power consumption.
 Supports six DDR3 registered dual in-line memory module (RDIMM) memory slots and a
maximum of 48 GB memory.
 Provides two 10/100/1000 Mbit/s BASE-T Ethernet Base interfaces connecting to the
backplane and used for communicating with the switch blades and supports boards
started from the network.
 Provides two 10 Gbit/s XAUI Ethernet Fabric interfaces connecting to the backplane and
used for communicating with the switch blades.
 Provides one update interface connecting to the backplane and used for communicating
with other processor boards, where data types can be defined by users.
 Provides two 10 Gbit/s transmission channels connecting to the interface boards for
connecting external devices.
 Provides four 1 Gbit/s transmission channels connecting to the interface boards for
connecting external devices.
 Provides one serial advanced technology attachment (SATA) port for connecting to one
solid-state drive (SSD).

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 Note: For details about the PFI, EECA, and EFCA, see the description about the service
processing modules.

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 The OSTA2.0 hardware platform is logically divided into three buses and four subsystems.
 The SWU uses extra Base and Fabric buses in dual star structure. The buses are interconnected over the
backplane and transmit data in a point-to-point mode.
 The primary IPMB, Base, and Fabric buses transmit data while the secondary IPMB, Base, and Fabric buses
receive data. Therefore, 28 buses in total are provided by 14 slots.
 The IPMB bus implements board temperature measurement, voltage detection, reset control, fan box in-
position detection, rotation detection, rotation control, power subrack voltage detection, and power subrack
current detection.
 Upon detecting a fault, the IPMC of the FRU reports an alarm to the SMM.
 The Base bus uses the dual star structure. The Base bus is used for software loading, alarm, and maintenance
information transmission.
 Each SWU provides:
 12 ports that connect to 12 general process units
 2 ports that connect to active/standby SMMs
 1 port that connects to the Base plane of another SWU
 8 ports that connect to the rear boards. The SWI provides eight external network ports as cascading
extension interfaces.
 The SMM and each process unit provide two Base bus ports that connect to dual-bus on the Base plane to
exchange data with the SWU.
 The subsystems are as follows:
 Device management subsystem: SMM and SDM
 Switching subsystem: SWU and SWI
 Service processing subsystem: UPB and USI
 Electrical subsystem: including the backplane, fan enclosure, and power distribution module

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 The IPMB bus is used for OSTA2.0 subrack monitoring and device management. The IPMB
bus connects all the devices in the OSTA2.0 subrack.
 The SMM can manage the hardware systems in the subrack in a unified manner over the
IPMB bus. The IPMB bus in each slot is connected in dual star structure. The IPMB buses in
the fan enclosure, power subrack, and other subracks are connected in dual-bus mode.
The active and standby SMMs are connected to two IPMB buses to synchronize data.

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 The Base bus is used as the management and control bus in the OSTA2.0 subrack. The
Base bus is used for software loading, alarm, and maintenance information transmission.
 The SWU is the switching core on the Base plane. The SWU exchanges data on the control
plane and provides cascading ports on the Base plane. All the boards are connected to the
SWU over the Base plane to exchange control plane information.

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 The Fabric bus provides data channels on the service plane and transmits service-related
data.
 The SWU is the switching core on the Fabric plane. The SWU exchanges data on the
service data plane and provides cascading ports. All the boards are connected to the SWU
over the Fabric plane to exchange service information.

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 Note:
 1. The RTC module is located on the OMU rear board (USI7).
 2. The OMU sets and reads board time using the CPU.
 3. The intra-subrack and inter-subrack boards synchronize time using the NTP protocol on
the Base plane.
 4. The RTC module provides a level-2 (0.4 PPM) oscillator that ensures time precision upon
NTP server failure.

 The NTP server supports maintenance networking and service networking modes. This
slide uses the maintenance networking as an example to describe how the EPU/EPUB
connects to the NTP server over the PFI.

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 NE software
 The NE software is used for signaling access and processing, service control, resource management, and charging information generation. The
NE software cooperates with the background software to respond to the operation commands. The NE software provides the data
management, device management, alarm management, performance measurement, and signaling trace functions for NEs.
 The NE software uses the top-down and hierarchical modular design. The operating system, middleware, and various application software are
deployed from the bottom to the top.
 Operating system
 The NE software uses the Linux system that is a real-time operating system.
 Middleware
 The USN9810 uses the middleware DDPRA technology between the operating system and application software so that the upper-layer service
software is independent from the bottom-layer operating system. The middleware facilitates the portability of software between platforms. Due
to less service software changes, the middleware supports stable software versions.
 Application software
 The application software provides functions of the USN9810. Different boards can use different types of application software to implement
different functions. The USN9810 application software includes the following types:
 Signaling bearing software: processing the access of narrowband signaling and bottom-layer protocols
 Service processing software: performing signaling processing, session management, mobility management, and resource management
 Database software: managing device data and dynamic user data
 System support software: implementing system management and device interconnection
 O&M software: receiving operation commands from the OMU and sending back command execution results
 Background software
 The background software interworks with the NE software and provides human-machine interfaces. The background software is used by the
maintenance staff to implement data management, device management, alarm management, performance measurement, signaling trace, and
CDR management.
 The background software uses the client/server architecture. The background software mainly includes the OMU server software, OMS
software, and WebUI. The OMU server software is installed on the OMU and the OMS software and WebUI are installed on the PCs.
 OMU server software
 The OMU server software runs on the OMU. The OMU server software integrates the communication server and database server. The OMU
server software forwards the O&M commands from workstations to the NEs and transmits the responses or operation results from the NEs to
the corresponding workstations. The OMU server software is the core of the terminal OAM software.
 The OMU server software runs in the Linux operating system. Multiple service processes (for example, maintenance process, data management
process, alarm process, and performance measurement process) work together to provide major functions of the OAM software.

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 Switching system
 Function: providing GE ports and implementing inter-subrack interconnection
 Hardware: SWU/TMI/TSI
 Packet data transfer system
 Function: providing Gn/GP, Iu-PS, and MME ports and routing and forwarding interface data
 Hardware: EPU/EPUB/ESU
 Service processing system
 Function: processing narrowband signaling link layer management (MTP2 and FR), SS7 protocols, and
high-layer protocols, and providing high-layer functions such as MAP, MM, EMM, SM, CAMEL, and
lawful interception
 Hardware: ECU/ESU
 Charging system
 Function: collecting, storing, encoding, and transmitting CDRs
 Hardware: ECU/ESU
 O&M system
 Function: providing external O&M ports and implements system maintenance, configuration,
performance, alarm, and logs
 Hardware: OMU
 Clock system
 Function: providing level-2 and level 3 clocks
 Hardware: subboard TMI of the SWU

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 The USN9810 system processes are classified into CGP processes and USN9810 processes. The CGP
process includes the host process and server process.
 The host process includes: monitoring process, IMU process, RMU process, SMU process, and
service process.
 Server process includes: O&M access process, service processing process, device access process, and
resource monitoring process.
 Process group
 A process group includes processes of several types with certain percentage, for example,
SPPx8+GBPx8+SGPx8+LLPx8+CDP.
 The USN process group is as follows:
 OMPGP (OMPGP), ECUGP (ECUGP), EPUGP (EPUGP_8), LIPGP (LIPGP), LCPGP (LCPGP), UIPGP
(UIPGP), EVUGP, and CHRGP
 Each process group includes the following processes:
 OMPGP: OMPx1
 ECUGP: SPPx8+GBPx8+SGPx8+LLPx8+CDPx1
 EPUGP: GTPx8+PCPx1+UMPx1
 ESUGP: SPP*12+GBP*12+SGP*12+LLP*12+CDP*1+UPP*1+AMP*1
 The function of the UPP on the ESU is similar to that of the GTP, PCP, and PFP on the EPU. The
function of the AMP on the ESU is similar to the UMP on the EPU.
 LIPGP: LIPx1
 LCPGP: LCPx1
 UIPGP: UIPx1
 EVUGP: FPP*1+TPP*2+UMP*1+PCP*1
 CHRGP: CRP*6

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 GTP: GPRS tunnel protocol


 PCP: packet forward control process
 UMP: user plane management process
 PFP: packet forward process
 LIP: lawful interception process

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 GTP: GPRS tunnel protocol


 PCP: packet forward control process
 UMP: user plane management process
 LIP: lawful interception process

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 The power monitoring module monitors the power supply system in real time and reports
the power operating status. The power monitoring module generates alarms for
abnormalities. The power monitoring module is located at the power distribution box.
 The principles for power distribution box monitoring are as follows:
 A monitoring board is installed in the power distribution box to collect the running status
information of the power distribution box.
 The monitoring board provides an active RS485 serial port and a standby RS485 serial port
and provides external RS485 serial port cables that are connected to the SDMs (COM2) of
the active and standby SMMs.
 The SMM processes the information collected by the monitoring board and reports the
information to the OMU over the internal Base bus. Then, the OMU reports the
information to the OMC system. The OMC system generates the corresponding alarms and
sends the alarms to the alarm console or alarm boxes.

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 The SMM manages all the hardware devices in the cabinet. The SMM performs device
management, event management, asset management, power management, remote
maintenance, configuration restoration, and power-saving control.
 The SMM connects to the fan assembly over the IPMB bus to manage and monitor the fan
assembly.
 The power distribution box provides four external Boolean detection ports that are
connected to sensors such as access control, water, and smoke sensors.
 The Boolean detection ports collect the ambient information of the equipment room.
 The paths for reporting the ambient information of the equipment room and the status of
the power distribution box are the same.

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 The MAS CLK indicates the master clock input.


 The SLA CLK indicates the slave clock input.
 The ETIA0 that connects to the MAS CLK is configured as the LINE1 clock source while the
ETIA0 that connects to the SLA CLK is configured as the LINE2 clock source.

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 The process is as follows:


 1. The BSS sends an Attach Request message to the ECU over the Gb interface and
ETI board (1->2).
 2. The LLP and GBP process the Attach Request message and then send the
message to the SPP (3->4).
 3. After processing the message, the SPP initiates the location update procedure
and sends the Update Location Ack message to the HLR over the SGP and LLP (5-
>6->7->8).
 4. The HLR sends an Update Location Req message to the SPP (9->10->11->12).
 5. The SPP sends an Attach Accept message to the MS (13->14->15->16).
 Note:
 During the preceding procedure, the LLP provides the FR and MTP2 layer functions. The
GBP provides the NS, BSSGP, LLC, and SNDCP layer functions. The SPP provides the MM,
MAP, and TC layer functions. The SGP provides the SCCP and MTP3 layer functions.

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 The process is as follows:


 1. The BSS sends an Attach Request message to the ESU over the Gb interface and
ETI board (1->2).
 2. The LLP and GBP process the Attach Request message and then send the
message to the SPP (3->4).
 3. After processing the message, the SPP initiates the location update procedure
and sends the Update Location Ack message to the HLR over the SGP and LLP (5-
>6->7->8).
 4. The HLR sends an Update Location Req message to the SPP (9->10->11->12).
 5. The SPP sends an Attach Accept message to the MS (13->14->15->16).
 Note:
 During the preceding procedure, the LLP provides the FR and MTP2 layer functions. The
GBP provides the NS, BSSGP, LLC, and SNDCP layer functions. The SPP provides the MM,
MAP, and TC layer functions. The SGP provides the SCCP and MTP3 layer functions.

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 The process is as follows:


 1. The BSS sends an Active PDP context request message to the ECU over the Gb interface
and ETI board (1->2).
 2. The LLP and GBP process the Active PDP context request message and then send the
message to the SPP (3->4).
 3. After processing the message, the SPP requests the GTP process on the EPU/EPUB to
create user-plane resources (5).
 4. The SPP sends a Create PDP context request message to the GGSN and notifies the
GGSN of the allocated TEID and addresses of the SGSN on the user plane and signaling
plane (6->7->8).
 5. The GGSN sends a Create PDP context accept message to the SGSN and notifies the
SGSN of the allocated TEID and addresses of the SGSN on the user plane and signaling
plane. Till now, the tunnel information is exchanged between the SGSN and the GGSN (9-
>10->11).
 6. The SPP sends an Active PDP context accept message to the 2G MS and requests the
GBP to create SNDCP resources (12->13->14->15).
 Note:
 During the preceding procedure, the LLP provides the FR layer functions. The GBP provides the NS,
BSSGP, LLC, and SNDCP layer functions. The SPP provides the SM and GTPC layer functions. The
GTP provides the GTPU function. The PFP provides the GTPU and IP layer functions.

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 The process is as follows:


 1. The BSS sends an Activate PDP context request message to the ESU over the Gb
interface and ETI board (1->2).
 2. The LLP and GBP process the Activate PDP context request message and then send the
message to the SPP (3->4).
 3. After processing the message, the SPP requests the UPP process to create user-plane
resources (5).
 4. The SPP sends a Create PDP context request message to the GGSN and notifies the
GGSN of the allocated TEID and addresses of the SGSN on the user plane and signaling
plane (6->7).
 5. The GGSN sends a Create PDP context accept message to the SGSN and notifies the
SGSN of the allocated TEID and addresses of the SGSN on the user plane and signaling
plane. Till now, the tunnel information is exchanged between the SGSN and the GGSN (8-
>9->10).
 6. The SPP sends an Activate PDP context accept message to the 2G MS and requests the
GBP to create SNDCP resources (11->12->13->14).
 Note:
 During the preceding procedure, the LLP provides the FR layer functions. The GBP provides the NS,
BSSGP, LLC, and SNDCP layer functions. The SPP provides the SM and GTPC layer functions. The
GTP provides the GTPU function. The PFP provides the GTPU and IP layer functions.

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 Uplink data flow:


 When the uplink data flow from the MS reaches the ECU, the data flow is sent to
the GBP over the LLP. The GBP forwards the data packets to the PFP on the EPU.
After processing the data packets, the PFP sends the processed data packets to the
GGSN (1->2->3->4).
 Downlink data flow:
 The EPU receives the service data from the GGSN. The PFP forwards the data
packets to the GBP on the ECU. Then, the GBP processes the data packets and
sends the data packets to the MS (5->6->7->8).
 Note:
 During the preceding procedure, the LLP provides the FR layer functions. The GBP provides
the LLC and SNDCP layer functions. The PFP provides the GTPU and IP layer functions.

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 Uplink data flow:


 When the uplink data flow from the MS reaches the ESU, the data flow is sent to
the GBP over the LLP. The GBP forwards the data packets to the UPP on the ESU.
After processing the data packets, the UPP sends the processed data packets to the
GGSN (1->2->3->4).
 Downlink data flow:
 The ESU receives the service data from the GGSN. The UPP forwards the data
packets to the GBP on the ESU. Then, the GBP processes the data packets and
sends the data packets to the MS (5->6->7->8).
 Note:
 During the preceding procedure, the LLP provides the FR layer functions. The GBP provides
the LLC and SNDCP layer functions. The PFP provides the GTPU and IP layer functions.

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 The process is as follows:


 1. The BSS sends an Attach Request message to the EPU over the Gb interface and
PFI (1->2).
 2. The PFP and GBP process the message and then send the message to the SPP (3-
>4).
 3. After processing the message, the SPP initiates the location update procedure
and sends the Update Location Req message to the HLR over the SGP and LLP (5-
>6->7->8).
 4. The HLR sends an Update Location Ack message to the SPP (9->10->11->12).
 5. The SPP sends an Attach Accept message to the MS (13->14->15->16).
 Note:
 During the preceding procedure, the PFP provides the IP layer functions. The LLP provides
the FR and MTP2 layer functions. The GBP provides the NS, BSSGP, LLC, and SNDCP layer
functions. The SPP provides the MM, MAP, and TC layer functions. The SGP provides the
SCCP and MTP3 layer functions.

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 The process is as follows:


 1. The BSS sends an Attach Request message to the ESU over the Gb interface and
QXI (1->2).
 2. The UPP and GBP process the message and then send the message to the SPP
(3->4).
 3. After processing the message, the SPP initiates the location update procedure
and sends the Update Location Req message to the HLR over the SGP and LLP (5-
>6->7).
 4. The HLR sends an Update Location Ack message to the SPP (8->9->10).
 5. The SPP sends an Attach Accept message to the MS (11->12->13->14).
 Note:
 During the preceding procedure, the UPP provides the IP layer functions. The LLP provides
the FR and MTP2 layer functions. The GBP provides the NS, BSSGP, LLC, and SNDCP layer
functions. The SPP provides the MM, MAP, and TC layer functions. The SGP provides the
SCCP and MTP3 layer functions.

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 The process is as follows:


 The BSS sends an Active PDP context request to the EPU over the Gb interface and PFI (1-
>2).
 The PFP and GBP process the Active PDP context request message and then send the
message to the SPP (3->4).
 After processing the message, the SPP requests the GTP process on the EPU to create user-
plane resources (5).
 The SPP sends a Create PDP context request message to the GGSN and notifies the GGSN
of the allocated TEID and addresses of the SGSN on the user plane and signaling plane (6-
>7->8).
 The GGSN sends a Create PDP context accept message to the SGSN and notifies the SGSN
of the allocated TEID and addresses of the SGSN on the user plane and signaling plane. Till
now, the tunnel information is exchanged between the SGSN and the GGSN (9->10->11).
 The SPP sends an Active PDP context accept message to the 2G MS and requests the GBP
to create SNDCP resources (12->13->14->15).
 Note:
 During the preceding procedure, the PFP provides the IP layer functions. The GBP
provides the NS, BSSGP, LLC, and SNDCP layer functions. The SPP provides the SM and GTPC layer
functions. The GTP provides the GTPU function. The PFP provides the GTPU and IP layer functions.

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 The process is as follows:


 The BSS sends an Activate PDP context request to the ESU over the Gb interface
and QXI (1->2).
 The UPP and GBP process the Activate PDP context request message and then send
the message to the SPP (3->4).
 After processing the message, the SPP requests the UPP process on the ESU of the
Gn side to create user-plane resources (5).
 The SPP sends a Create PDP context request message to the GGSN and notifies the
GGSN of the allocated TEID and addresses of the SGSN on the user plane and
signaling plane (6->7).
 The GGSN sends a Create PDP context accept message to the SGSN and notifies
the SGSN of the allocated TEID and addresses of the SGSN on the user plane and
signaling plane. Till now, the tunnel information is exchanged between the SGSN
and the GGSN (8->9->10).
 The SPP sends an Activate PDP context accept message to the 2G MS and requests
the GBP to create SNDCP resources (11->12->13->14).
 Note:
 During the preceding procedure, the UPP provides the GTPU and IP layer
functions. The GBP provides the NS, BSSGP, LLC, and SNDCP layer functions. The SPP
provides the SM and GTPC layer functions. The GTP provides the GTPU function.

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 Uplink data flow:


 When the uplink data flow from the MS reaches the EPU, the data flow is sent to
the GBP over the PFP. The GBP forwards the data packets to the PFP on the EPU.
After processing the data packets, the PFP sends the processed data packets to the
GGSN (1->2->3->4->5->6).
 Downlink data flow:
 The EPU receives the service data from the GGSN. The EPU forwards the data
packets to the GBP on the ECU over the PFP. Then, the GBP forwards the data
packets to the PFP on the EPU. The PFP processes the data packets and sends the
data packets to MS.
 (7->8->9->10->11->12).
 Note:
 During the preceding procedure, the GBP provides the LLC and SNDCP layer function and
the PFP provides the GTPU and IP layer function.

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USN9810 Hardware & Software System

 Uplink data flow:


 When the uplink data flow from the MS reaches the ESU, the data flow is sent to
the GBP over the UPP. The GBP forwards the data packets to the UPP on the ESU
of the Gn side. After processing the data packets, the UPP sends the processed
data packets to the GGSN (1->2->3->4).
 Downlink data flow:
 When the downlink data flow from the GGSN reaches the ESU, the data flow is
sent to the GBP on the Gb side over the UPP. The GBP forwards the data packets
to the UPP on the ESU. After processing the data packets, the UPP sends the
processed data packets to the MS (5->6->7->8).
 Note:
 During the preceding procedure, the GBP provides the LLC and SNDCP layer function and
the UPP provides the GTPU and IP layer function.

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USN9810 Hardware & Software System

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USN9810 Hardware & Software System

 The process is as follows:


 1. The RNC sends an Attach Request message to the EPU over the Iu interface and
PFI board (1->2).
 2. The PFP and SGP process the message and then send the processed message to
the SPP (3->4).
 3. After processing the message, the SPP initiates the location update procedure and
sends the Update Location Req message to the HLR over the SGP and LLP (5->6->7-
>8).
 4. The HLR sends an Update Location Ack message to the SPP (9->10->11->12).
 5. The SPP sends an Attach Accept message to the MS (13->14->15->16).
 Note:
 During the preceding procedure, the PFP provides the IP layer functions. The LLP provides
the MTP2 layer functions. The SGP provides the SCCP and MTP3 layer functions. The SPP
provides the MM, MAP, and TCAP layer functions.

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USN9810 Hardware & Software System

 The process is as follows:


 1. The RNC sends an Attach Request message to the ESU over the Iu interface and
PFI board (1->2).
 2. The UPP and SGP process the message and then send the processed message to
the SPP (3->4).
 3. After processing the message, the SPP initiates the location update procedure
and sends the Update Location Req message to the HLR over the SGP and LLP (5-
>6->7->8).
 4. The HLR sends an Update Location Ack message to the SPP (9->10->11->12).
 5. The SPP sends an Attach Accept message to the MS (13->14->15->16).
 Note:
 During the preceding procedure, the UPP provides the IP layer functions. The LLP provides
the MTP2 layer functions. The SGP provides the SCCP and MTP3 layer functions. The SPP
provides the MM, MAP, and TCAP layer functions.

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USN9810 Hardware & Software System

 The process is as follows:


 1. The RNC sends an Active PDP context request message to the EPU over the Iu
interface (1->2).
 2. The PFP and SGP process the message and then send the processed message to
the SPP (3->4).
 3. After processing the message, the SPP requests the GTP process on the EPU to
create user-plane resources (5).
 4. The SPP sends a Create PDP context request message to the GGSN and notifies
the GGSN of the allocated TEID and addresses of the SGSN on the user plane and
signaling plane (6->7->8).
 5. The GGSN sends a Create PDP context accept message to the SGSN and notifies
the SGSN of the allocated TEID and addresses of the SGSN on the user plane and
signaling plane. Till now, the tunnel information is exchanged between the SGSN
and the GGSN (9->10->11).
 6. The SPP sends an Active PDP context accept message to the MS and requests
the SBP to create GTP resources (12->13->14->15).
 Note:
 During the preceding procedure, the PFP provides the GTP and IP layer function. The SGP
provides the SCTP, M3UA, and SCCP layer functions. The SPP provides the SM and GTPC
functions. The GTP provides the GTPU layer functions.

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USN9810 Hardware & Software System

 The process is as follows:


 1. The RNC sends an Activate PDP context request message to the ESU over the Iu
interface and the PFI (1->2).
 2. The UPP and SGP process the message and then send the processed message to
the SPP (3->4).
 3. After processing the message, the SPP requests the UPP process on the ESU of
the Gn side to create user-plane resources (5).
 4. The SPP sends a Create PDP context request message to the GGSN and notifies
the GGSN of the allocated TEID and addresses of the SGSN on the user plane and
signaling plane (6->7).
 5. The GGSN sends a Create PDP context accept message to the SGSN and notifies
the SGSN of the allocated TEID and addresses of the SGSN on the user plane and
signaling plane. Till now, the tunnel information is exchanged between the SGSN
and the GGSN (8->9->10).
 6. The SPP sends an Activate PDP context accept message to the MS and requests
the SBP to create GTP resources (11->12->13->14).
 Note:
 During the preceding procedure, the UPP provides the GTP and IP layer function. The SGP
provides the SCTP, M3UA, and SCCP layer functions. The SPP provides the SM and GTPC
functions.

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USN9810 Hardware & Software System

 Uplink data flow:


 After the uplink data packets from the MS reach the EPU over the PFI, the PFP
processes the data packets and sends the processed data packets to the GGSN (1-
>2->3->4).
 Downlink data flow:
 After the downlink data packets from the GGSN to the EPU, the PFP processes the
data packets and sends the processed data packets to the MS (5->6->7->8).
 Note:
 During the preceding procedure, the PFP provides the GTPU and IP layer functions.

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USN9810 Hardware & Software System

 The process is as follows:


 1. The BSS sends an Attach Request message to the ESU over the Gb interface and
QXI (1->2).
 2. The UPP and GBP process the message and then send the message to the SPP
(3->4).
 3. After processing the message, the SPP initiates the location update procedure
and sends the Update Location Req message to the HLR over the SGP and LLP (5-
>6->7).
 4. The HLR sends an Update Location Ack message to the SPP (8->9->10).
 5. The SPP sends an Attach Accept message to the MS (11->12->13->14).
 Note:
 During the preceding procedure, the UPP provides the IP layer functions. The LLP provides
the FR and MTP2 layer functions. The GBP provides the NS, BSSGP, LLC, and SNDCP layer
functions. The SPP provides the MM, MAP, and TC layer functions. The SGP provides the
SCCP and MTP3 layer functions.

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USN9810 Hardware & Software System

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USN9810 Hardware & Software System

 The process is as follows:


 1. The eNodeB sends an Attach Request message to the EPU over the S1-MME
interface and PFI (1->2).
 2. The PFP and SGP process the message and then send the processed message to
the SPP (3->4).
 3. After processing the message, the SPP initiates the location update procedure
and sends the Update Location Req message to the HSS over the SGP and FP (5->6-
>7->8).
 4. The HSS sends an Update Location Ack message to the SPP (9->10->11->12).
 5. The SPP send a Create Session Req message to the S-GW (13->14->15).
 6. The S-GW sends a Create Session Rsp message to the SPP (16->17->18).
 7. The SPP sends an Attach Accept message to the MS (19->20->21->22).
 Note:
 During the preceding procedure, the PFP performs the IP layer function; the SGP performs
the Diameter and S1-AP functions; the SPP performs the MM, SM, GTPC functions.

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USN9810 Hardware & Software System

 The process is as follows:


 1. The eNodeB sends an Attach Request message to the ESU over the S1-MME
interface and PFI (1->2).
 2. The UPP and SGP process the message and then send the processed message to
the SPP (3->4).
 3. After processing the message, the SPP initiates the location update procedure
and sends the Update Location Req message to the HSS over the SGP and FP (5-
>6->7->8).
 4. The HSS sends a location update response message to the SPP (9->10->11->12).
 5. The SPP sends a Create Session Req message to the S-GW (13->14->15).
 6. The S-GW sends a Create Session Rsp message to the SPP (16->17->18).
 7. The SPP sends an Attach Accept message to the MS (19->20->21->22).
 Note:
 During the preceding procedure, the UPP performs the IP layer function; the SGP performs
the Diameter and S1-AP functions; the SPP performs the MM, SM, GTPC functions.

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USN9810 Hardware & Software System

Confidential Information of Huawei. No Spreading Without Permission


USN9810 Hardware & Software System

Confidential Information of Huawei. No Spreading Without Permission


USN9810 Hardware & Software System

Confidential Information of Huawei. No Spreading Without Permission

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