Cadence EDI System What's New 12.0 PDF

EDI System What's New 12.
0
Product Version 12.0
December 2012
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EDI System What's New 12.0
Table of Contents
Contents
1. 11
About This Manual 11
How This Document Is Organized 11
Related Documents 11
EDI System Product Documentation 11
2. 13
Release Overview 13
Release 12.0 Overview 13
New Text Commands and Global Variables 13
New Command Parameters 15
Obsolete Text Commands and Global Variables 21
Supported in this Release 21
Removed from Software 23
Obsolete Command Parameters 24
Supported in this Release 24
Removed from the Software 25
Default Behavior Changes 28
3. 29
Licensing Changes for Release 12 29
Release 12.0 Enhancements 29
Product Changes for 20nm Support 29
Multi-CPU Acceleration Tokens for ETS-XL Changed to Four 29
4. 30
Foundation Flows 30
New Variables for Foundation Flow 30
Support for Power Domain - Delay Corner Binding Via 30
Hierarchical Two-Pass Automated Re-budgeting Flow Extended 30
5. 31
EDI System Display and Tools 31
Ruler Enhancements 31
New and Enhanced Ruler Modes 31
Total Ruler Length Display 33
Auto Snap to Object Edges 33
Custom Colors 33
Enhancements in Pin Display and Selection 33
New Option for Viewing Enlarged Logical Pins 33
December 2012 3 Product Version 12.0

Table of Contents
New Pin Shapes Option in Layer Control Bar 34

New Option for Highlighting Pin Shapes on Net Selection 35
Enhancements in Flightline Preferences 35
New Option for Displaying Only Clock Nets 35
New Options for Controlling Flightline Color and Width 35
Enhancement in the Ungroup Feature 36
Log File Enhancement 36
find_global Enhancement 36
set_object_color Enhancement 36
New Command for Limiting Display of Return Values 37
New Command To Launch DB Browser 37
New Form for Going to a Specific Location 37
New DBTCL Option 37
New Command to Control Message Severity Level 37
6. 39
Multiple CPU Processing 39
Memory Reporting Improved 39
7. 41
Importing and Exporting the Design 41
lefOut and defOut Enhanced To Support Embedded Bumps 41
lefOut Enhanced To Output PG Bump Information along with PG Physical Pins 41
New Global Variable To Uniquify the Design 41
New Global Variable for Power Routing 42
New Options for Command add_shape 42
8. 43
LEF-DEF Properties 43
LEF 5.8 Properties for Creating New DRC Rules for 32-28 nm and Smaller Nodes 43
Cut Layer Enhancements 43
Routing Layer Enhancements 44
9. 46
Wire Editing 46
New setSpecialRouteOption options for Supporting Multiple-Layer P/G Pins 46
New Option for Selecting/Deselecting Via along with Wire 47
New setViaEdit Option for Creating Special Vias 47
New setViaEdit Option To Prevent Replacement of Existing Via with New, Overlapping Via 48
New setEdit Option for Stretching Wires Along with Via 48
10. 50
Flip Chip 50

Table of Contents
Flip Chip Flightline Enhancements 50

Highlight by Selection 50
Colored Flightlines 51
Object-Specific Flightlines 51
DIFFPAIR-Based Highlighting 52
New Display Flightline Form 53
Add Bump to Array Form Renamed and Enhanced 53
New changeBumpMaster Parameters 54
New Change Bump Master Form 54
Enhanced Assign/Unassign Signals Form 55
New Auto Zoom Feature 55
New Filter Options 55
New Criterion for Assigning Bumps 55
Support for Assigning Multiple PG Pads to Multi Bumps 56
New assignPGBumps Parameter 56
New Option for Flip Chip Routing in View Area 56
Obsolete fcroute Parameters 57
11. 59
Partitioning 59
Support for Promoting Macro Pins 59
New Parameters for Specifying Offset 59
Pin Editor Capability Enhanced 60
Specify Partition GUI Form Updated 62
alignPtnClone Command Enhanced 62
checkPinAssignment Command Enhanced 63
New Parameter to Specify Keep Out Spacing 63
Pin Constraint Commands Consolidated 64
Multi-threading Support for savePartition Command 65
Support for Saving and Loading Selective Floorplan Data 65
New Parameter Added to the savePartition Command 65
New Parameter Added to the assembleDesign Command 65
New set_ptn_fplan_mode Command Added 66
New get_ptn_fplan_mode Command Added 66
12. 67
Floorplanning 67
createPGPin Command Enhanced 67
createObsAroundInst Command is now Obsolete 67
add_ndr Command Enhanced 68
Support for Reporting Narrow Channels 68
Support for Handling Master/Clones in Different Hierarchy 69
Enhanced Power Domain Placement Capability 69
Enhanced Auto-shaping for Placing Modules 69

Table of Contents
Support for Virtual fence Option to Handle User-specified Seeds 69

New Command to Generate Partition Fences Around Flexmodels 70
Support for Bus Guides in Relative Floorplan 71
Blackblob Capability made Obsolete 71
13. 73
Structured Data Path 73
readSdpFile Command Enhanced To Support More Than 10 skipSpace Variables 73
Support Added for Reusing SDP Instantiations 73
New Buttons in the SDP Browser 73
14. 75
Multiple Supply Voltage (MSV) 75
New Options for optPowerSwitch 75
New Options for reportPowerDomain 75
New Option for replacePowerSwitch 75
15. 76
NanoRoute Router 76
NanoRoute Support for LEF Properties Enhanced 76
getNanoRouteMode and setNanoRouteMode Commands Modified 76
Enhanced Violation Marker Support 77
16. 78
TrialRoute Router 78
TrialRoute Support for get_metric APIs 78
17. 79
Timing Budgeting 79
Power Pin Support in Budgeted Timing Models for Low Power Designs 79
Justify Budget Enhanced 80
18. 82
RC Extraction 82
RCDB Reading Enhanced to Fix Errors 82
New Command for Providing Information about the Contents of the RCDB 82
Obsolete Command Parameters - Removed from the Software 83
TQRC/IQRC Enhanced to Complete Broken RC Networks 84
TQRC/IQRC Enhanced to Perform Incremental Extraction After defIn and Metal Fill
Commands 84
Accuracy of PreRoute Extraction Enhanced for Signal Nets 84
Reduction in Peak Memory Consumption by spefIn in Sequential Mode 85

Table of Contents
19. 86
Timing 86
Constraint Handling Enhancements 86
Ability to Override Local Clock Latency Value 86
Reporting Enhancements 86
Added New Global Variable to Track Reported Paths Limit 86
Ability to Report on AOCV Stage Counts 87
Timing Report Enhanced to Show Markers for Pins 88
Added New Command to Report AOCV Derating Factors 88
Added New Parameters for Statistical Derating 88
Ability to Perform Arc-Based AOCV Weight Analysis 89
Added New Global to Improve Reporting of Clock Objects 89
Added New Property Attribute 89
Added New Property to Report Constants 89
Added New Library Properties 89
Report_timing Command Enhanced 90
Timing Modeling 90
Ability to Perform AOCV-Based ETM Extraction 90
do_extract_model Command Enhancements 91
Other Enhancements 91
Ability to Perform AOCV Analysis on Data Paths 91
Added New Property to Report Macros 91
Added New Global to Control Clock Reconvergence 91
20. 92
Timing Debug 92
New Options for load_timing_debug_report 92
21. 93
Verification 93
New Command To Support 20nm and Lower DRC Rules 93
Verify Geometry Enhancements 93
Option -minPinArea Now Obsolete 93
Option -warning Now Obsolete 93
Violation Browser Enhancements 93
Auto Zoom Enhanced To Display Only Active Layers for Violations 93
Option Added for Limiting Number of Errors Displayed Per Type 94
Support Added for Complex Logical Expressions for Filtering Violations 95
New Forms Added for Loading and Saving DRC Markers 95
22. 97
Power Calculation 97
read_activity_file Parameters Consolidated 97

Table of Contents
Multi-Threading Support for Dynamic Vector-Based Power Analysis Flow 97

Power Analysis Reporting Enhanced 98
Clock-Gating Efficiency Reports Improved 98
Variation in Switching Power Numbers when Running Power Analysis from EDI 99
23. 100
Rail Analysis 100
Simplification of Auto-Fetch DC Sources Commands 100
Body Bias Analysis Supported 102
On-Chip Voltage Regulator Analysis Supported 103
Support for Region-Based Snapping 104
Edit Pad Location Form Enhanced 104
view_esd_violation Enhanced to View Bumps Within a Resistor Range 105
Ability to Control Layer Processing 106
Rail Analysis Reporting Improved 106
Support for Non Zero Capacitance Filler Cells for Decap Optimization Flow 107
Sub_Via Support Added 107
Change in Extraction Results for Designs with Dangling Resistors 107
Block Level DEF Pin Checking Capability Enhanced 107
Via Clustering Enhanced 107
New Parameters to Ignore Filler and Decap Cells 108
24. 109
Early Rail Analysis 109
New Parameter to Support Fast Mode Extraction 109
Power Gate Analysis Behavior Enhanced 109
25. 111
Mixed Signal Interoperability 111
run_vsr GUI Updated 111
setIntegRouteConstraint Command Enhanced 111
Integration Constraints Editor GUI Updated 114
Floating Shields Supported 114
26. 115
Clock Concurrent Optimization 115
setCCOptMode Command Enhanced to Set the Minimum Fanout Number for Top Nets 115
27. 116
Clock Tree Synthesis 116
AssumeShielding Option in the Clock Specification File is Obsolete 116
clockDesign Parameters not Supported with CCOpt Engine 116
reportClockTree Command Enhanced to Write Out Information for Cell Types 117

Table of Contents
28. 118
OpenAccess 118
New Command to Access the 5.x Library Structure 118
New Parameter to Add Voltage Information to the Nets 118
29. 119
TSV 119
Embedded Bump Flow Supported in Hierarchical Designs 119
New Parameter Added to Output Selected Bumps 119
30. 120
Timing Optimization 120
New Command Introduced 120
timeDesign Command Updated 120
reclaimArea Command Updated 120
setOptMode Command Updated 120
New Parameters Added 120
GigaOpt as the Default Optimization Engine 121
Obsolete Parameters 121
31. 122
Placement 122
Release 12 Enhancements 122
New Commands 122
New Options for setPlaceMode 122
New Option for addFillerGap 122
32. 124
Yield Analysis 124
Yield Analysis Discontinued 124
33. 125
Delay Calculation 125
Vectorized Delay Calculation Support in MMMC with AAE 125
34. 126
Netlist-to-Netlist 126
runN2NOpt -optimizeYield Parameter Now Obsolete 126
35. 127
Prototyping Foundation Flow 127

Table of Contents
New Command to Control Initial Floorplan 127

New Command to Generate Floorplan for Prototyping 127
set_proto_mode Command Updated 127
set_proto_model Command Updated 128
load_timing_debug_report Command Updated 128
36. 129
Signal Integrity Analysis 129
setSIMode Command Enhanced 129

About This Manual
1
About This Manual
This manual provides information about Product Version 12 of the Cadence® Encounter® Digital
Implementation System family of products.
The Encounter Digital Implementation System (EDI System) family encompasses the following
products:
Encounter Digital Implementation System L
Encounter Digital Implementation System XL
NanoRoute® Ultra SoC Routing Solution
Virtuoso® Digital Implementation
Encounter Timing System L
Encounter Timing System XL
Encounter Power System L
Encounter Power System XL
First Encounter™ L
First Encounter XL
First Encounter GXL
How This Document Is Organized

This What's New manual is organized into chapters that cover broad areas of EDI System
software functionality. Each chapter contains topics that may address one or more of the following
areas:
New functionality in the EDI System software and enhancements made to existing forms
and commands to support a new feature.
Changes in default behavior, name changes to existing commands and forms, and syntax
changes.
Features that were removed since version 10 of the software.
Major documentation changes, such as a new chapter or substantial reorganization.
Related Documents
For more information about the EDI System family of products, see the following documents. You
can access these and other Cadence documents with the Cadence Help documentation system.
EDI System Product Documentation

About This Manual
EDI System Known Problems and Solutions

Describes important Cadence Change Requests (CCRs) for the EDI System family of
products, including solutions for working around known problems.
EDI System User Guide

Describes how to install and configure the EDI System software, and provides strategies for
implementing digital integrated circuits.
EDI System Text Command Reference

Describes the EDI System text commands, including syntax and examples.
EDI System Menu Reference

Provides information specific to the forms and commands available from the EDI System
graphical user interface.
EDI System Database Access Command Reference

Lists all of the EDI System database access commands and provides a brief description of
syntax and usage.
EDI System Foundation Flows User Guide

Describes how to use the scripts that represent the recommended implementation flows for
digital timing closure with the EDI System software.
EDI System Library Development Guide
Describes library development guidelines for the independent tools that make up the EDI
System family of products.
Mixed Signal Interoperability Guide

Describes the digital mixed-signal flow.
README file
Contains installation, compatibility, and other prerequisite information, including a list of
Cadence Change Requests (CCRs) that were resolved in this release. You can read this
file online at downloads.cadence.com.

Release Overview
2
Release Overview
Release 12.0 Overview
New Text Commands and Global Variables
New Command Parameters
Obsolete Text Commands and Global Variables
Supported in this Release
Removed from Software
Obsolete Command Parameters
Removed from the Software
Default Behavior Changes
Release 12.0 Overview

New Text Commands and Global Variables
The following table lists the commands that were added to the EDI System software. The second
column identifies the chapter of the EDI System Text Command Reference where the command
is documented.
New Commands and Globals Chapter
create_power_pads Rail Analysis

Commands
create_route_type Basic
Database
Access Tcl
Commands
db_browser GUI
Commands
dd_get OpenAccess
Commands
delete_route_type Basic
Database
Access Tcl
Commands
generate_fence Floorplan
Commands
and Global
Variables
get_ptn_fplan_mode Partition
Commands
and Global

Release Overview
Variables
get_well_tap_mode Placement
Commands
and Global
Variables
getPinConstraint Partition
Commands
and Global
Variables
init_design_uniquify Import and
Export
Commands
and Global
Variables
place_connnected Placement
Commands
and Global
Variables
proto_design Prototyping
Foundation
Flow
Commands
report_pba_aocv_derate Timing
Analysis
Commands
report_rcdb RC
Extraction
Commands
set_message General
Commands
and Global
Variables
set_voltage_regulator_module Rail Analysis

Commands
set_well_tap_mode Placement
Commands
and Global
Variables
set_ptn_fplan_mode Partition
Commands
and Global
Variables
set_proto_design_mode Prototyping
Foundation
Flow
Commands

Release Overview
timing_cppr_skip_clock_reconvergence Timing
Global
Variables
timing_extract_model_aocv_mode Timing
Global
Variables
timing_property_clock_used_as_data_unconstrained_clock_source_paths Timing
Global
Variables
timing_report_enable_markers Timing
Global
Variables
timing_report_enable_max_path_limit_crossed Timing
Global
Variables
verify_drc Verify
Commands
New Command Parameters

The following table lists the parameters that were added to the EDI System software. The second
column identifies the chapter of the EDI System Text Command Reference where the command
is documented.
New Parameters Chapter
add_ndr Floorplan Commands and Global

-hard_spacing Variables
-name
add_shape Import and Export Commands and
-shape Global Variables
-shield_net
-status
-user_class
addFillerGap Placement Commands and Global

-radius Variables
alignPtnClone Partition Commands and Global
-layer Variables
-track
analyze_early_rail Rail Analysis Commands
-turbo
-off_rails
assembleDesign Partition Commands and Global
-fplan Variables

Release Overview
assignBump Flip Chip Commands and Global

-ratio Variables
assignIoPins Partition Commands and Global
-promoteMacroPin Variables
assignPGBumps Flip Chip Commands and Global
-checkerboard Variables
assignPtnPin Partition Commands and Global
-promoteMacroPin Variables
autoGenRelativeFPlan Floorplan Commands and Global
-busGuide Variables
changeBumpMaster Flip Chip Commands and Global
-bump_name Variables
-selected
checkFPlan Floorplan Commands and Global
-narrow_channel Variables
checkPinAssignment Partition Commands and Global
-ignore Variables
-report_violating_pin
createNetGroup Partition Commands and Global
-keep_out_spacing Variables
createPGPin Floorplan Commands and Global
-length Variables
-onDie
-selected
-width
createPinBlkg Partition Commands and Global
-offset_end Variables
-offset_start
createPinGroup Partition Commands and Global
-keep_out_spacing Variables
createPinGuide Partition Commands and Global
-offset_end Variables
-offset_start
dbShape Basic Database Access Tcl
-maxPoint Commands
do_extract_model Timing Modeling Commands

-pg
editPin Partition Command and Global
-include_rectilinear_edge Variables
-layer_priority
-pattern
-reverse_alternate
editSelect Wire Edit Commands

Release Overview
-wires_only
editDeselect Wire Edit Commands
-wires_only
getFlipChipMode Flip Chip Commands and Global
-prevent_via_under_bump Variables
load_timing_debug_report Timing Debug Commands
-additonal_slack_past_wns
-num_path
-proto
optPowerSwitch Low Power Commands

-setDontUseCells
-idsatmargin
-reportOnly
-area
getPlanDesignMode Floorplan Commands and Global

-virtualFence Variables
Timing Optimization Commands
reclaimArea
-hold
relativeFPlan Floorplan Commands and Global
-masterSlave Variables
-masterType
-masterName
-slaveType
-slaveName
replacePowerSwitch Low Power Commands
-xyRangeFromCenterInst
read_activity_file Power Calculation Commands
-scale_duration
-block
-scope
reportClockTree Clock Tree Synthesis Commands

-area
reportPowerDomain Low Power Commands

-pin
-verbose
report_power Power Calculation Commands

–cluster_gating_efficiency
report_resource Multiple-CPU Processing
-verbose Commands
savePartition Partition Commands and Global

Release Overview
-fplan Variables
set_clock_latency Timing Constraint Commands
-clock_gate
setDelayCalMode Delay Calculation Commands
-combine_mmmc
setEdit Wire Edit Commands

-stretch_with_intersect
setFlipChipMode Flip Chip Commands and Global
-prevent_via_under_bump Variables
setOaxMode OpenAccess Commands
-saveNetVoltage
Timing Optimization Commands
setOptMode
-timeDesignNumPaths
-timeDesignExpandedView
-timeDesignReportNet
-postRouteAreaReclaim
setPinConstraint Partition Commands and Global

-area Variables
-corner
-corner_to_pin_distance
-depth
-global
-side
-target_layers
-use_min_width_as_depth
-width
setPlaceMode Placement Commands and Global

-fillerGapRadius Variables
-prerouteAsObs
-congRepairEffort

Release Overview
setPlanDesignMode Floorplan Commands and Global

-virtualFence Variables
set_power_analysis_mode Power Calculation Commands
–bulk_pins
set_proto_mode Prototyping Foundation Flow
Commands
-flexfiller_route_blockage
-create_characterize_percent_rt_blockage
-identify_partition_min_inst
-identify_partition_max_inst
set_proto_model Prototyping Foundation Flow

Commands
-create_gate_area
-create_gate_count
set_rail_analysis_mode Rail Analysis Commands

-process_bulk_pins_for_body_bias
–cluster_via_rule
–cluster_via1_ports
–ignore_fillers
–ignore_decaps
setSIMode Signal Integrity Commands
-accumulated_small_attacker_mode

Release Overview
-accumulated_small_attacker_threshold
-individual_attacker_threshold
-separate_delta_delay_on_data
-delta_delay_annotation_mode
-switch_prob
-receiver_peak_limit
-input_glitch_thresh
setSpecialRouteOption Wire Edit Commands

-multi_layer_pin
-multi_layer_via
set_timing_derate Timing Analysis Commands

-corner
-statistical
setViaEdit Wire Edit Commands
-auto_replace
-force_special

Release Overview
setCCOptMode Clock Concurrent Optimization

-top_net_min_fanout (CCOpt) Commands
unsetPinConstraint Partition Commands and Global
-all Variables
-all_area
-area
-corner
-corner_to_pin_distance
-depth
-global
-side
-target_layers
-width
viewBumpConnection Flip Chip Commands and Global

-bump Variables
-honor_color
-io_inst
-net
-selected
view_analysis_results Rail Analysis Commands

-process_layer_off
view_esd_violation Rail Analysis Commands
-limit
violationBrowser Verify Commands
-filter_query
-max_error_per_type
writeBumpLocation TSV Design Commands
-selected
Obsolete Text Commands and Global Variables
The following obsolete text commands and global variables will continue to be supported in this
release, but will be removed in the next major release of the software.
createObsAroundInst
Use the createPlaceBlockage command instead.
auto_fetch_dc_sources
Use the create_power_pads command instead.
add_pad_location
This command has not been replaced.
clear_pad_loc_display

Release Overview
delete_pad_location
display_pad_loc
getAllowedPinLayersOnEdge
getGlobalMinPinSpacing
getLayerPinDepth
getLayerPinWidth
getMinPinSpacing
getMinPinSpacingOnEdge
getPinDepth
getPinToCornerDistance
getPinWidth
Use the getPinConstraint command instead. It provides the needed functionality for
all these commands.
load_pad_location
save_pad_location
setAllowedPinLayersOnEdge
setGlobalMinPinSpacing
setLayerPinDepth
setLayerPinWidth
setMinPinSpacing
setMinPinSpacingOnEdge
setPinDepth
setPinToCornerDistance
setPinWidth
Use the setPinConstraint command instead. It provides the needed functionality for
all these commands.
setOptMode
congOpt
considerNonActivePathGroup

Release Overview
critPathCellYield
postRouteAllowOverlap
yieldEffort

unsetMinPinSpacing
Use the unsetPinConstraint command instead.
Removed from Software
The following obsolete text commands and global variables have been removed from the
software.
createNdr
This command has been replaced by add_ndr .
elaborateBlackBlob
initNdr
loadBlackBlobNetlist
loadYieldTechFile
modifyNdrViaList
reportYield
setPrerouteAsObs
This command has been replaced with the setPlaceMode option -
prerouteAsObs

Release Overview
setNdrSpacing
setNdrWidth
specifyBlackBlob
unplaceBlackBlob
unspecifyBlackBlob
Obsolete Command Parameters
The following obsolete text command parameters will continue to be supported in this release, but
will be removed in the next major release of the software. Update your scripts to avoid warnings
and to ensure compatibility with future releases.
checkPinAssignment
-busGuideCheck
-netGroupCheck
-pinAbutmentCheck
-pinDepthCheck
-pinGroupCheck
-pinGuideCheck
-pinLayerCheck
-pinMinAreaCheck
-pinOnFenceCheck
-pinOnTrackCheck
-pinSpacingCheck
-pinWidthCheck
Use -ignore {bus_guide net_group pin_abutment pin_depth
pin_group pin_guide pin_layer pin_min_area pin_on_fence
pin_on_track pin_spacing pin_width clones} instead.
optPowerSwitch -reportViolationsOnly
Use -reportOnly instead.
-unchainByInstances
The -unchainByInstances parameter of the addPowerSwitch command has been

Release Overview
replaced by commandrechainPowerSwitch.
-chainByInstances
The -chainByInstances parameter of the addPowerSwitch command has
been replaced by the command rechainPowerSwitch parameter -
chainByInstances.
-powerDomainBufList
The -powerDomainBufList parameter of the bufferTreeSynthesis command
will be removed in the next release. You can specify both always-on and regular buffers in
the buffer list. bufferTreeSynthesis will be able to pick up the right buffer.
-srpgEnablePins
The -srpgEnablePins parameter of the bufferTreeSynthesis command will
be removed in the next release. optDesign is able to optimize the always-on nets
automatically.
getVerifyGeometryMode -minPinArea
setVerifyGeometryMode -minPinArea
verifyGeometry -minPinArea
Use the -sameCellViol parameter of these commands instead to report minimum area
violations for pin shapes in the cell, along with other cell violations.
getVerifyGeometryMode -warning
setVerifyGeometryMode -warning
verifyGeometry -warning
This parameter is not being replaced as Verify Geometry does not write warning markers.
runN2NOpt -optimizeYield
This parameter is not being replaced as the Yield Analysis feature is becoming obsolete.
read_activity_file -scale_tcf_duration, -scale_fsdb_duration,

and -scale_vcd_duration.
Use -scale_duration instead.
read_activity_file -fsdb_block, -tcf_block, and -vcd_block.

Use -block instead.
read_activity_file -fsdb_scope, -tcf_scope, and -vcd_scope.

Use -scope instead.
Removed from the Software
The following obsolete text command parameters have been removed from the software.
fcroute

Release Overview
-allowOverCongestion
This parameter is not being replaced.
-balancePairThreshold
Use the THRESHOLD keyword in the DIFFPAIR section of the constraint file.
-connectPowerCellToBump
Use setFlipChipMode -connectPowerCellToBump instead.
-differentialPairRoute
Specify the pair of nets in the DIFFPAIR section of the constraint file.
-differentialRoute
Use the exta configuration file option
srouteDifferentialRouteTolerance instead.
-differentialRouteTolerance
Use the TOLERANCE keyword in the MATCH section of the constraint file instead.
-interleaveStyle
Use SPLITSTYLE keyword in the constraint file instead.
-multiBumpsToPad
Use setFlipChipMode -multipleConnection multiBumpsToPad instead.
-multiPadsToBump
Use setFlipChipMode -multipleConnection multiPadsToBump instead.
-optWidth
Use the exta configuration file option srouteGrouteOptimizeWidth instead.
-preventViaUnderBump
Use setFlipChipMode -prevent_via_under_bump instead.
-routeStyle
Use setFlipChipMode -route_style instead.
-shieldBump
Use the SHIELDBUMP keyword in the SHIELDING section of the constraint file instead.
-shieldLayers
Use the SHIELDSTYLE keyword in the SHIELDING section of the constraint file instead.
-shieldNet
Use the SHIELDNET keyword in the SHIELDING section of the constraint file instead.

Release Overview
-shieldWidth
Use the SHIELDWIDTH keyword in the SHIELDING section of the constraint file instead.
-splitGap
Use the SPLITGAP keyword in the constraint file instead.
-widthLimit
Use the SPLITWIDTH keyword in the constraint file instead.
getNanoRouteMode and setNanoRouteMode
-dbCheckRule
-dbReportWireExtraction
-dbReportWireExtractionEcoOnly
-drouteAutoCreateShield
-drouteCheckMinstepOnTopLevelPin
-drouteElapsedTimeLimit
-routeAutoGgrid
-routeDeleteAntennaReroute
-routeInsertAntennaInVerticalRow
-routeMergeSpecialWire
-routeSiEffort
-routeTdrEffort
-routeUseBlockageForAutoGgrid
-routeWithSiPostRouteFix
-timingEngine
These parameters are not being replaced.
setExtractRCMode
-ipdb
This parameter is no longer required as this feature is now ON by default.
-noReduce
This parameter is no longer required as the software does not perform RC reduction by
default.
-rcdb
This parameter is no longer required as the software generates the RCDB in the current
working directory by default.
-scOpTemp
This parameter is not supported in the MMMC mode. Use the -T parameter of the
create_rc_corner and update_rc_corner commands instead.
-useNDRForClockNets
This parameter is no longer required as this feature is now ON by default.
setPlaceMode
-blockedShifterCols

Release Overview
-blockedShifterRows
-colShiftersOnly
-dividedShifterCols
-dividedShifterRows
-rowShiftersOnly
-strictShifterSide
-strictShifterSpot
-rpSpreadEffort
spefIn -dumpMissedNet
This parameter is no longer required as the software prints the missing nets in file
rc_corner_name.missing_nets.rpt by default.
setPlanDesignMode and getPlanDesignMode

-groupHardMacro
-groupIOLogic
-handleFlat
-numSeed
-seedSize
-setSeedHierLevel
-useFlexModel
These parameters are not being replaced.
Default Behavior Changes

The following list briefly describes changes in default behavior that take effect in this release.
Note: Each description in this list is also the section in the What's New where you can find more
detailed information on the specific behavior change.
Chapter Default Behavior Change
Power Variation in Switching Power Numbers when Running Power Analysis from
Calculation EDI
Rail Analysis Change in Extraction Results for Designs with Dangling Resistors
Block Level DEF Pin Checking Capability Enhanced

Licensing Changes for Release 12
3
Licensing Changes for Release 12
Release 12.0 Enhancements
Product Changes for 20nm Support
Multi-CPU Acceleration Tokens for ETS-XL Changed to Four

Product Changes for 20nm Support
The product options ENC-T20 and ENC-S20 are now allowed to be checked out dynamically from
FE-L and FE-XL. If FE is used to load a lef with 20nm rules, one of the 20nm option licenses is
checked out.
For more information, see Checking Out Licenses for Product Options in the Product and
Licensing Information chapter of the EDI System User Guide.
Multi-CPU Acceleration Tokens for ETS-XL Changed to Four

In this release, the multi-CPU acceleration tokens for ETS-XL has been increased to four. This
means that a base license for ETS-XL now enables four CPUs. Moreover, each additional multi-
CPU license for ETS-XL enables four more CPUs for acceleration.

Foundation Flows
4
Foundation Flows
New Variables for Foundation Flow
Support for Power Domain - Delay Corner Binding Via
Hierarchical Two-Pass Automated Re-budgeting Flow Extended

New Variables for Foundation Flow
The new variables in this release of Foundation Flows are:
vars(oa_fp): to be used for OA floorplan support.
set vars(enable_dlm) true | false : Enables new flex ILM hierarchical flow
set vars(enable_celtic_steps) true | false : Enable the Celtic SI fixing steps
(Default: Off in 12.0)
Support for Power Domain - Delay Corner Binding Via
Foundation Flows now supports power domains. The variables are:

set vars(library_sets): List of library sets
set vars(delay_corners): List of delay corners
set vars(power_domains): List of power domains to bind
set vars(dc,power_domains): List of power domains
set vars(dc,ls,power_domains): List of power domains. This allows bind to a
specify delay corner AND library set
Hierarchical Two-Pass Automated Re-budgeting Flow Extended

EDI System Foundation Flow extends the two-pass hierarchical flow to include automated ILM and
FlexILM-based re-budgeting flow for regular implementation of the flow.

EDI System Display and Tools
5
Ruler Enhancements
New and Enhanced Ruler Modes
Total Ruler Length Display
Auto Snap to Object Edges
Custom Colors
Enhancements in Pin Display and Selection
New Option for Viewing Enlarged Logical Pins
New Pin Shapes Option in Layer Control Bar
New Option for Highlighting Pin Shapes on Net Selection
Enhancements in Flightline Preferences
New Option for Displaying Only Clock Nets
New Options for Controlling Flightline Color and Width
Enhancement in the Ungroup Feature
Log File Enhancement
find_global Enhancement
set_object_color Enhancement
New Command for Limiting Display of Return Values
New Command To Launch DB Browser
New Form for Going to a Specific Location
New DBTCL Option
New Command to Control Message Severity Level

Ruler Enhancements
In this release, the following enhancements have been made to the ruler to make it easier to use:
New and Enhanced Ruler Modes

In this release, existing ruler modes have been reorganinzed and new ruler modes have been
introduced to make the ruler easier to use. The following ruler modes are now available in the
Create Ruler Preferences form:
Ruler Purpose Old Modes

Mode Replaced
Single Specifies that ruler line can be drawn in a single direction. This is Vertical
edge the default ruler mode. Horizontal
Use this option if you want to measure a single edge in one of the Any
following directions: Angles
45
Vertical 135
Horizontal X
Diagonal (45 degrees, 135 degrees)
Any angle
To draw a vertical, horizontal, or diagonal (45 or 135 degrees)
ruler, simply click at the point where you want the ruler to start and
move the mouse in the required direction. The ruler line will follow
one of the following defined directions automatically.

To draw a ruler at an angle other than the above eight directions,

keep the Shift key pressed and then start drawing the ruler at
the required angle.
To end a Single edge ruler, either click at the point where you
want to end the ruler or press Enter.
Orthogonal Specifies that ruler lines can be drawn in horizontal as well as Orthogonal
edges vertical directions. Use this option if you want to measure
orthogonal edges, such as follows:
Note: You can draw an Orthogonal ruler without opening the

Create Ruler Preferences form. Just keep the Ctrl key pressed
and then start drawing the ruler to measure orthogonal edges. To
end the ruler, press Enter.
Multiple Specifies that ruler lines can be turned in multiple directions. Use -
edges this option if you want to measure multiple segments in a complex
pattern.
To draw a Multiple edge ruler, click at the point where you want
the ruler to start. Move the mouse in the required direction, clicking
at evey point you want the ruler to turn. To end the ruler, press
Enter .
Note: To draw a ruler in a direction other than horizontal, vertical

or diagonal (45 or 135 degrees), keep the Shift key pressed
and then start drawing the ruler at the required angle.
Cross Specifies that ruler lines can be drawn in a + shape. Use this -
Ruler option to measure two edges at the same time, see the overall X

and Y length, or to check alignment of macros.
To draw a cross ruler, click anywhere in the design. A + ruler is

displayed occupying the entire display area in both X and Y
directions. The center of the + moves with the cursor. Move the
center of the + to the point where you want the origin of the ruler.
Press Enter to place and end the ruler.
You can access the Create Ruler Preferences form either by choosing Tools - Create Ruler or
clicking the Create Ruler widget and press the F3 key.
Total Ruler Length Display

You can now easily view the total length of your ruler. As soon as you end a ruler, its total length is
displayed alongside, in additon to the length of the individual segments of the ruler.
Auto Snap to Object Edges

In this release, edge detection has been enhanced so that a ruler can automatically snap to an
object’s edges or corners.
Custom Colors
You can now change the color of the ruler from the default yellow to any color of your choice. In
the color preferences form, click the color box next to Ruler on the View-Only page and choose
the desired color.
Enhancements in Pin Display and Selection

New Option for Viewing Enlarged Logical Pins
Use the new Enlarge Logical Pin In Fit View option on the Display page of the Preferences form
to check pin distribution in a block design. When this option is selected, the tool displays larger
symbols for logical pins in the Fit view. This is helpful for feedthrough planning as it gives you an
approximate idea of where pins are dense and where spaces exist for feedthrough pins in the
design. As you zoom into the design, the logical pin view gradually disappears and the real
physical pin locations are shown in the zoomed-in view.

New Pin Shapes Option in Layer Control Bar

You can now control whether pin shapes are visible and selectable by using the Pin Shapes
option under Cell in conjunction with the Terminal option under Miscellaneous on the Layer
Control bar.
Instance pin/term display behavior has been modified as follows:
Terminal Visibility Pin Shape Visibility Main Window Displays

Toggle Toggle
On (Default) Off (Default) Yellow squares (Representing instance

terms)

On On Pin shape
Off On Pin shape
Off Off Null
You can get a pin's instance terminal (InstTerm) information by selecting the pin and then running
the dbGet selected command.
New Option for Highlighting Pin Shapes on Net Selection

In this release, a new selection preference option has been added to view connected cell term
shapes when you select a net. If the new Hilite Pin Shapes When Selecting a Net option on the
Selection page of the Preferences form is turned on, all visible cell term shapes are highlighted
when you select a net.
Enhancements in Flightline Preferences

New Option for Displaying Only Clock Nets
By default, EDI System shows the flightlines of all nets. However, during floorplanning, you might
want to place the hierarchical module and focus on checking the connectivity of clock and reset
nets based on flightlines. You can now select the new Show Clock Net Only option on the
Flightline page of the Preferences form to view the flightlines of only clock and reset nets.
New Options for Controlling Flightline Color and Width

By default, EDI System displays all flightlines in blue color. In previous releases, you could choose
to use different colors for input, output, and inout connections. In this release, EDI System provides
you additonal options to control flightline color and width based on the number of connections.
You can now choose from the following Flightline Color Control options:
Single Color: Uses a single color for all flightlines.
Default: Blue
Different Color by Type of Connections: Displays the input, output, and inout net
connections using different colors.
Input - Green
Output - Yellow
Inout - Pink
Mixture - Blue
Different Color by Number of Connections: Displays small, medium, and large number of

net connections using different colors.

Small - Green
Medium - Yellow
Large - Pink
Different Width by Number of Connections: Displays small, medium, and large number of
net connections using lines of different widths.
Small - Thin line
Medium - Medium line
Large - Thick line
Number of Connections: Specifies the thresholds for determining whether number of
connections is small, medium, or large. By default, connections lower than 20 is
considered Small, connections equal to or between 20 and 80 is considered Medium, and
connections greater than 80 is considered Large.
Default Low Threshold: 20
Default High Threshold: 80
Enhancement in the Ungroup Feature

In this release, if you try to ungroup a module that contains only standard cells and marcos but
does not contain any submodules, the tool ignores the ungroup request and issues the following
warning:
**WARN: (ENCSYT-3162): Cannot ungroup Module 'DTMF_INST/RAM_128x16_TEST_INST' because it has no child.
This enhancement prevents any accidental ungrouping and therefore saves you the effort of
finding and regrouping standard cells and macros that were in the module.
Log File Enhancement

The EDI System tool has been enhanced so that all messages displayed in the xterm
(stdin/stdout/stderr) window are also captured in the .log file. Earlier, it was difficult to determine
which information displayed on the xterm window would also be available in the log file.
Note: puts to a $channel (file pointer) is not logged.
find_global Enhancement
The find_global command has been enhanced to display the variables it returns in alphabetical
order. This makes the find_global results easier to read.
set_object_color Enhancement

The set_object_color command is used to set the color of objects of an instance, hierarchical
instance, SDP, or module. In this release, the set_object_color command has been
enhanced to support power domains and instance groups as well. You can now use
set_object_color -object_name to set the color of objects of a specific power domain or
instance group. Alternatively, you can use set_object_color -object_type to set the
color of all power domain objects or instance group objects. For example, use the following
command to color all power domain objects in multiple colors:
set_object_color -object_type PowerDomain -multicolor
New Command for Limiting Display of Return Values

You can now use the new set_return_limit command to control the display of Tcl return values in
screen output or log file.
Impact on Other Commands, Parameters, and Globals: None
New Command To Launch DB Browser

In this release, you can use the new db_browser command to launch the DB Browser and retrieve
information about various database objects. In previous releases, you could launch the browser
only from the GUI or by using the v bindkey.
New Form for Going to a Specific Location

Use the new Goto form to find specific locations accurately in the main window display. You
can specify one or more sets of X and Y coordinates either directly in the form or by loading a file.
You can then click the Goto button to create an X marker on the location specified by the selected
coordinates and zoom into that location in the main window display. By creating additional
markers for other locations in the list, you can view relative locations of multiple sets of X and Y
coordinates.
New DBTCL Option

The command dbShape now supports the parameter -maxPoint which helps specify
the maximum number of points for output in a polygon. The minimum being 5 and maximum 8000.
New Command to Control Message Severity Level

You can now use the set_message command to change the message severity level, INFO,
WARNING or ERROR, at the beginning of the message. This command allows you to control the
messages that are displayed for a particular design. For example, if there are some warnings that
are critical for the design, you can change the message severity to ERROR. Similarly, if there are
messages that you want to ignore, you can change the message severity to INFO. The syntax of
the command is given below:
set_message
[-help]
[-id list_of_msgIDs]

-severity {warn error info reset}

Multiple CPU Processing
6
Memory Reporting Improved

Memory Reporting Improved
In this release, memory reporting has been improved to indicate how much memory is being used
at any time and of what form (physical, virtual, and master/slave). Previously, peak memory was
the only number which had some physical significance. You can now use the -verbose
parameter of the report_resource command to get detailed memory usage information.
When you run report_resource -verbose, the following detailed memory information is
displayed:
Current (total cpu=0:00:12.9, real=0:05:48, peak res=275.8M,

current mem=383.9M)
Cpu(s) 2, load average: 4.63
Mem: 16443800k total, 16378412k used, 65388k free, 105704k buffers
Swap:16777208k total, 17460k used, 16759748k free, 12528212k
cached
Memory Detailed Usage:
Data Resident Private Virtual Resident
Set(DRS) Dirty(DRT) Size(VIRT) Size(RES)
Total 383.9M 275.8M 854.1M 358.9M
current:
peak: 383.9M 275.8M 854.1M 358.9M
The -verbose parameter also works in conjunction with the -peak and -start/-end
parameters of the report_resource command. When you run the local distributed slave
(setDistributeHost -local) command, the memory information will include the memory
consumed by master and slaves.

For -start/-end parameters, use -verbose with the -end parameter only.
For details on memory information, refer to the Accelerating the Design Process By Using Multiple-
CPU Processing chapter of the EDI System User Guide.

Importing and Exporting the Design
7
lefOut and defOut Enhanced To Support Embedded Bumps
lefOut Enhanced To Output PG Bump Information along with PG Physical Pins
New Global Variable To Uniquify the Design
New Global Variable for Power Routing
New Options for Command add_shape

lefOut and defOut Enhanced To Support Embedded Bumps
In previous releases, when you use lefOut to export a multi-block design, the bumps in each block
are described as PIN in the export LEF file. This makes it difficult to distinguish bumps from normal
pins. When you are implementing a hierarchical flow in a 3DIC design, the tool needs to export all
the bump information in each chip correctly. This is because all embedded bump metal layer
information is required for analysis in top-level RC extraction.
In this release, the PASSIVATION layer is used to define an embedded bump in the block. If a
PORT in a block has a PASSIVATION layer, the tool treats it as an embedded bump. lefOut has
been enhanced to output both metal layer and PASSIVATION layer information for the embedded
bump to the LEF file. In addition, the defOut -bumpAsPin option has been enhanced to catch
embedded bumps and output all their layer information (metal layers as well as PASSIVATION
layer geometry) in the PIN section of the DEF file in the same way as for normal bumps.
lefOut Enhanced To Output PG Bump Information along with PG

Physical Pins
In previous releases, if your block-level design had both Power/Ground (PG) physical pins and PG
bumps, lefOut would print only the physical pin geometry to the block LEF file. lefOut has now
been enhanced to outpout both PG bump and PG physical pin information. This is useful if you
want to import the block LEF files in a third-party tool and need the PG bump geometry as well as
the PG physical pin information for top level connections.
New Global Variable To Uniquify the Design

In this release, the rda_Input(ui_uniquify_netlist) variable has been replaced with
the new init_design_uniquify global variable in accordance with the init_design model introduced

in EDI11. You can use the init_design_uniquify global variable to uniquify the design
automatically during the read and flatten process.
New Global Variable for Power Routing

In this release, you can use the new init_oa_special_rule variable to specify the OpenAccess
constraint group that defines the vias to be used by SROUTE. If nothing is specified, then the
constraint group with the nameLEFSpecialRouteSpec is searched in OpenAccess.
New Options for Command add_shape

A few new options have been added to the command add_shape. They are, as follows:
-shape: Defines the wiring shape.
-shield_net: The name or pointer of the net to be shielded by the via instance.
-status: Defines the wiring status.
-user_class: Defines the attribute class by user.

LEF-DEF Properties
8
LEF-DEF Properties
LEF 5.8 Properties for Creating New DRC Rules for 32-28
nm and Smaller Nodes
Cut Layer Enhancements
You can define new CUT LAYER properties to create rules for cut layers that:
Add ANTENNAGATEPWL rule, to define a PWL (piece-wise linear) table that is indexed by
the real gate area, and returns an “effective gate-area” interpolated from the table. If the
table it not defined, the real gate area is used.
Add BELOWENCLOSURE in PARALLEL to cut layer ENCLOSURE rules, to indicate that the
enclosure rule only applies if the enclosure on the below metal layer is less than the
specified below enclosure value on either sides perpendicular to the side having neighbors
or the wire direction containing the cut on the above metal layer.
Add parLength2 in PARALLEL and parWithin2 in WITHIN to cut

layer ENCLOSURE rules, to indicate that the rule does not apply if there is no neighbor on
either side based on parWithin2 and parLength2. The variable parLength2 must be smaller
than parLength and parWithin2 must be larger than parWithin.
The following cut layer enhancements have been made:

Enhanced ANTENNAGATEPLUSDIFF rule, to represent the protection provided by
the diffusion area that is added to the gate area value in the PAR (partial antenna
ratio) equation, which can be considered as the “additional effective gate-area”.
Enhanced PARALLEL in CONCAVECORNER in cut layer SPACING rules. An

enclosure can now be on one of the two opposite sides on the specified second
layer. Earlier, the enclosure could be defined on both the two opposite sides of a
layer.
For more information, see Defining Cut Layer Properties to Create 32/28 nm and Smaller Nodes
Rules in the "LEF Syntax" chapter of the LEF/DEF Language Reference Guide.

LEF-DEF Properties
Routing Layer Enhancements
You can define new ROUTING LAYER properties to create rules for routing layers that:
Add JOINTCORNERSPACING rule, to indicate that the spacing between two facing joints
of joint corners with parallel run length less than zero to be the spacing.
Add ENCLOSURESPACING rule, to specify the spacing on an edge with enclosure less
than the specified enclosure.
Add ANTENNAGATEPWL rule, to define a PWL (piece-wise linear) table that is indexed by
the real gate area, and returns an “effective gate-area” interpolated from the table. If this
table it not defined, the real gate area is used.
Add CONCAVECORNERS in NOADJACENTEOL to routing layer MINSTEP rules, to indicate
that the adjacent EOL minimum step rules only apply if both the neighbor edges of the EOL
have concave corner on the other end.
Add following keywords to routing layer OPPOSITEEOLSPACING rules:

JOINTEXTENSION in JOINTWIDTH: Specifies the extension on both sides of a
joint to be the joint extension.
JOINTCORNERONLY in JOINTWIDTH : Specifies that the joint must form a joint
corner, which is a convex corner consisting of two consecutive joints.
SIDEEDGELENGTH in WIDTH: Specifies that a side fulfilling other conditions must
also on an edge with length greater than the specified side edge length.
JOINTTOSIDE: Specifies a spacing requirement similar to SIDETOJOINT, but
having joint spacing to be the first spacing.
SIDETOSIDE: Specifies a spacing requirement between two sides of an EOL edge
with a middle wire.
Add SAMEMASK to routing layer EOLEXTENSIONSPACING rules, to specify that the EOL
extension spacing only applies to same-mask objects.
Add the following new variables and keywords to routing layer FORBIDDENSPACING
rules:
minSpacing2 and maxSpacing2, to define an additional second set of forbidden

spacing range.
TWOEDGES in WIDTH, to indicate that the forbidden spacing only applies if the wire
width is less than the maximum width that has neighbors on both sides within the
specified within value.

LEF-DEF Properties
The following routing layer enhancements have been made:

Enhanced ANTENNAGATEPLUSDIFF rule, for protection provided by the diffusion area
that is added to the gate-area value in the PAR equation, which can be considered as
“additional effective gate-area”.
For more information, see Defining Routing Layer Properties to Create 32/28 nm and Smaller
Nodes Rules in the "LEF Syntax" chapter of the LEF/DEF Language Reference Guide.

Wire Editing
9
Wire Editing
New setSpecialRouteOption options for Supporting Multiple-Layer P/G Pins
New Option for Selecting/Deselecting Via along with Wire
New setViaEdit Option for Creating Special Vias
New setViaEdit Option To Prevent Replacement of Existing Via with New,
Overlapping Via
New setEdit Option for Stretching Wires Along with Via

New setSpecialRouteOption options for Supporting Multiple-
Layer P/G Pins
EDI System now supports multiple-layer Power/Ground pins. In earlier releases, the mulitple-layer
pin feature was only supported by signal pins. With this enhancement, you can generate multi-
layer (two-layer) boundary pins for special wire.
To turn on the multi-layer P/G pin feature, you must set the new setSpecialRouteOption -
multi_layer_pin option to 1. You can specify the name of the via cell on which you want to
base the multi-layer pin by using the new -multi_layer_via option of
the setSpecialRouteOption command.
You can do the same from the GUI by using the highlighted options in the Special Route Options
form. The Special Route Options form can be accessed by clicking the Options button in the Edit
Route form:

Wire Editing
New Option for Selecting/Deselecting Via along with Wire

EDI System now enables you to select or deselect a via along with the wire. This enhancement
makes it possible for you to perform certain operations on a wire and associated via
simultaneously. For instance, you can change the net of a wire and associated vias by first
selecting the wire and via with the editSelect command and then using the editChangeNet
command to change the net.
Via selection/deselection happens by default when you select/deselect a wire. If you want to
select/deselect only the wire and not the associated via, use the new -wires_only option of
editSelect and editDeselect, respectively.
Impact on Other Commands, Parameters, and Globals: If you specify the editSelect -
wires_only option and then run editChangeNet, the net will be changed only for the wire
and not for the via.
New setViaEdit Option for Creating Special Vias

In this release, you can use the new setViaEdit -force_special option to force editAddVia to
create special vias instead of regular ones. This option is useful for flip chip flow in which all routing
wire segments are special nets. In previous releases, if you added a via manually with
editAddVia and the connected pin was signal, a regular via was created and this via could not
be changed to a special via. The new setViaEdit -force_special option can now be
used to ensure that the vias created with editAddVia are always special. You can do the same
from the GUI by using the new Force Special option in the Edit Via form:

Wire Editing
Impact on Other Commands, Parameters, and Globals: If you specify setViaEdit -

force_special 1 and then run editAddVia, vias created will be always special. To create
regular vias, specify setViaEdit -force_special 0 before running editAddVia.
New setViaEdit Option To Prevent Replacement of Existing Via

with New, Overlapping Via
You can use the new setViaEdit -auto_replace option to control whether existing vias are
replaced with the new ones created using editAddVia in case of any overlap. You can also
use the new Auto Replace option in the Edit Via form to control whether exisiting vias are
replaced.
Impact on Other Commands, Parameters, and Globals: If you specify setViaEdit -

auto_replace 0 and then run editAddVia, existing vias will be retained even if there is
some overalp with the new vias being added. Specify setViaEdit -auto_replace 1 to
replace existing vias with the new ones editAddVia in case of any overlap.
New setEdit Option for Stretching Wires Along with Via

Use the new setEdit -stretch_with_intersect option to stretch power wires with intersects
easily. If this option is set to 1, you can select the via and the edge of metals and then stretch
the wires and via together in a single step. In previous releases, the process for stretching wires
with intersects was more complex and required multiple steps.

Wire Editing

Flip Chip
10
Flip Chip
Flip Chip Flightline Enhancements
Highlight by Selection
Colored Flightlines
Object-Specific Flightlines
DIFFPAIR-Based Highlighting
New Display Flightline Form
Add Bump to Array Form Renamed and Enhanced
New changeBumpMaster Parameters
New Change Bump Master Form
Enhanced Assign/Unassign Signals Form
New Auto Zoom Feature
New Filter Options
New Criterion for Assigning Bumps
Support for Assigning Multiple PG Pads to Multi Bumps
New assignPGBumps Parameter
New Option for Flip Chip Routing in View Area
Obsolete fcroute Parameters

Flip Chip Flightline Enhancements
In flip chip designs, flightlines are used extensively to interact with the design. You can display flip
chip related flightlines using viewBumpConnection . In this release, flip chip flightlines have
been enhanced in the following ways to make them more user-friendly:
Highlight by Selection
When you select an object, the corresponding flightlines are now highlighted in bold.
When a bump or IO pad is selected, its corresponding flightline is highlighted in bold.
When multiple bumps/IO pads are selected, all their flightlines are highlighted in bold.
If a block with multiple IO pins is selected, all its flightlines are highlighted in bold.
When the objects are deselected, the corresponding flightlines return to non-bold status.
1. Run
viewBumpConnection
to display all flip chip
flightlines.
2. Click on an object to
highlight its flightline in
bold.

Flip Chip
Colored Flightlines
By default, all flip chip flightlines are displayed in yellow. You can now use the new
viewBumpConnnection –honor_color option to color these flightlines based on either
bump type or the nets to which the bumps are assigned:
To color flightlines by bump type, simply run viewBumpConnection –honor_color.
The tool displays flightlines using the default colors of the bumps:
Blue for signal bumps
Red for power bumps
Yellow for ground bumps
To color flightlines based on the nets to which they are assigned, you must:
a. Define bump color settings in a bump color map file using the following format :
net_name color_name
Example:
int cyan
reset pink
b. Load the bump color file using the ciopLoadBumpColorMapFile command.
c. Run viewBumpConnection –honor_color.
For bumps whose nets are not defined in the bump color file, the default colors are
used as follows--blue for signal bumps, red for power bumps, and yellow for ground
bumps. A flightline has the same color as its bump.
Impact on Other Commands, Parameters, and Globals: If you want to assign custom colors to
flightlines, you must specify the colors as required in the bump color map file and
run ciopLoadBumpColorMapFile before running viewBumpConnection –
honor_color.
Object-Specific Flightlines
You can now easily view connections for specific objects, such as bumps, nets, and IO instances,
using the following new viewBumpConnection parameters:
-bumps {bump_list}: Use this parameter to view connections of specified bumps.

-io_inst {io_inst_list}: Use this parameter to view connections of specified IO
instances or blocks.
-nets {net_list}: Use this parameter to view connections of specified nets.
-selected: Use this parameter to view connections of selected bumps or IO pads in
bold. If a block with multiple IO pins is selected, all its flightlines are displayed in bold.

Flip Chip
For example, the following command displays the flightlines for the port_pad_data_out[10]
net, the Bump_29 bump, and the IOPADS_INST/Ptdspop07 instance. It also displays in bold
the flightline for the selected bump:
viewBumpConnection \
-net {port_pad_data_out[10]} \
-bump Bump_29 \
-io_inst IOPADS_INST/Ptdspop07 \
-selected \
-honor_color
DIFFPAIR-Based Highlighting
Flip chip flightlines now honor the DIFFPAIR constraints specified in the flip chip router constraint
file. This means that when you select any one bump or IO pad that is part of a DIFFPAIR
constraint, the tool highlights all flightlines of that DIFFPAIR in bold.
For example, suppose the flip chip router constraint file, diffpair.const, has the following
setting:
DIFFPAIR
port_pad_data_in[15]
port_pad_data_in[13]
END DIFFPAIR
Now after setFlipChipMode -constraintFile diffpair.const is set, the flightlines

for the DIFFPAIR are highlighted in bold when any one bump or IO pad of the DIFFPAIR is
selected:

Flip Chip
Currently, you cannot turn off normal flightlines to focus on DIFFPAIR flightlines. However, you can
use viewBumpConnection –nets net_list as a workaround. Here, net_list specifies
nets of the DIFFPAIR. This way, you can display only the flightlines for the DIFFPAIR and turn off all
other flightlines.
New Display Flightline Form

Use the new Display Flightline form to configure flip chip related flightlines from the GUI. The
options in this form are equivalent to viewBumpConnection options. You can access the
Display Flightline form by choosing Tools - Flip Chip Toolbox - Display Flightline .
Add Bump to Array Form Renamed and Enhanced

The Add Bump to Array form has been renamed as Edit Bump. In addition, the form has been
enhanced to include three tabs:
Add - Use this page to add bumps to a bump array. This page provides the same options
as the original Add Bump to Array form in previous releases. It is also equivalent to the
addBumpToArrayGrid command.
Remove - Use this page to remove the selected or specified bump from its assigned bump
array grid. This page provides options equivalent to the removeBumpFromArray
command.
Delete - Use this page to to delete bumps from the design. This page provides options
equivalent to the deleteBumps command.

Flip Chip
New changeBumpMaster Parameters

In previous releases, you could choose to change the cell master of all bumps, bumps belonging
to a specific cell master, or bumps connected to a specific net. In this release, changeBumpMaster
provides two additional options for identifying the bumps for which you want to change bump
master:
-bump_name: Specifies the list of bumps for which you want to change the cell master.
Use this parameter if you want to change the cell master of specific bumps, which may or
may not have the same cell master originally.
-selected: Changes the cell master of the bumps that are currently selected in the
design area.
In both cases, the tool changes the cell master to the one specified using the existing -
bumpMasterName parameter.
Impact on Other Commands, Parameters, and Globals:

You cannot use -bump_name or -selected together.
You cannot use -bump_name or -selected at the same time as either -allBumps or
-netName.
If you use -fromBumpMasterName oldBumpMasterName along with -
bump_name bump_list , cell master replacement happens only for those bumps in the
list that belong to the cell master specified by oldBumpMasterName . If none of the
bumps in the list belong to the specified cell master, the tool displays a warning.
If you use -fromBumpMasterName oldBumpMasterName along with -
selected, cell master replacement happens only for those of the selected bumps that
belong to the cell master specified by oldBumpMasterName . If none of the selected
bumps belong to the specified cell master, the tool displays a warning, such as the
following:
WARN: (ENCSIP-7279): No bump with bump-master 'BUMP_GND' was
found in selected bumps.
New Change Bump Master Form

You can now change the cell master for bumps from the GUI by using the new Change Bump
Master form. This form provides options equivalent to the changeBumpMaster command.

Flip Chip
Enhanced Assign/Unassign Signals Form
In this release, the following enhancements have been made to the Assign/Unassign Signals form
to make it easy for you to search for pads, bumps, or nets:
New Auto Zoom Feature

Use the new Auto Zoom check box to automatically zoom to the object selected in the Signal List
table. This enhancement makes it easy for you to locate an IO signal in the display area.
New Filter Options

Use the Filter options to narrow down the list of signals displayed in the Signal List table. You can
filter the list by the following object types—IO Signal, Side, Driver, Driver Cell, Driver Pin, Driver
Location, Bump, or Bump Location. After you have selected the object type, specify a suitable
Operator and Value and then click Filter. All objects that meet the specified criteria are listed in the
Signal List table.
New Criterion for Assigning Bumps

You can now assign signals to a specified set of bumps by using the new In Bump Names option.
You can specify the bump names manually in the In Bump Names text box. Alternatively, click

Flip Chip
the Get Selected Bump button to compile the names of selected bumps in the text box
automatically. After the required bump names are specified in the In Bump Names text box,
click Assign to call the assignIOPinToBump command. This command assigns the signals
highlighted in the Signal List table to the specified bumps.
Assume that the number of IO Signal selected in the Signal List table is X and the number of
bumps specified in the In Bump Names text box is Y. The bump assignment happens as follows:
If X is equal to Y, the tool completes X assignments.
If X is greater than Y, the tool displays a warning and assigns the first Y pins in selection
order to the bumps.
If X is smaller than Y, the tool displays a warning and assigns all pins to X bumps in the
specified order in the In Bump Names text box.
Support for Assigning Multiple PG Pads to Multi Bumps

In previous releases, the tool assigns one power and ground (PG) pad to one bump in the same
way as it assigns one signal pad to one bump. However, unlike signal pads, PG pads usually
share the same PG nets with each other. In this release, the tool can automatically assign multiple
PG (multi-PG) pads on the same net to multiple bumps as per a controlled ratio that you define.
Different PG nets can have different ratios. This enhancement not only saves a lot of bump
resource, it also requires less manual effort for bump assignment.
Use the new assignBump -ratio parameter to assign multiple PG pads to one bump.
For more information, see the Multi-PG Pads to Multi Bumps Assignment with a Controlled
Ratio section in the Flip Chip Methodologies chapter of the EDI System User Guide.
New assignPGBumps Parameter

Till now, you could assign PG bumps in only two ways, horizontal and vertical. In this release, you
can use the new assignPGBumps -checkerboard parameter to assign PG bumps to the
specified pair of nets in a checkerboard pattern.
The -checkerboard parameter is to be used typically for a regular (rectangular) bump array.
However, you can also it for an irregular (rectilinear) bump array. To do so, first form a regular array
by creating virtual bumps in the areas where there are no bumps. Then, apply the checkboard
pattern. Once you have assigned the bumps, you can remove the virtual bumps.
Impact on Other Commands, Parameters, and Globals: The checkerboard style can be
used only with two nets. If -checkerboard is specified and the number of nets defined with -
nets is more than two, the tool reports an error and does not assign any bumps.
New Option for Flip Chip Routing in View Area

Previously, you could restrict flip chip routing to a specific portion of the design by either entering
the exact coordinates or by interactively selecting the area in the design display window. In this
release, the Flip Chip Route form provides you another option of restricting routing with the click of
a button. When you click the new View Area button, the coordinates of the view area in the
design display are automatically entered in the X1 Y1 X2 Y2 fields. This makes it easier for you to
specify the area to which you want to restrict flip chip routing.

Flip Chip
Obsolete fcroute Parameters

The following fcroute parameters have been removed from the software. Update your scripts to
use the suggested replacements.
Obsolete fcroute Parameter Suggested Replacement Syntax

-allowOverCongestion This option is not being replaced N/A
-balancePairThreshold Use the THRESHOLD keyword in the DIFFPAIR

DIFFPAIR section of the constraint file.
THRESHOLD value
net_name_1 net_name_2
END DIFFPAIR
-connectPowerCellToBump Use setFlipChipMode - setFlipChipMode -

connectPowerCellToBump instead. connectPowerCellToBump true
-differentialPairRoute Specify the pair of nets in the DIFFPAIR DIFFPAIR

section of the constraint file.
THRESHOLD value
net_name_1 net_name_2
END DIFFPAIR
-differentialRoute Use the exta configuration file option srouteDifferentialRouteTolerance

srouteDifferentialRouteTolerance value
instead.

Flip Chip
-differentialRouteTolerance Use the TOLERANCE keyword in the MATCH MATCH

section of the constraint file to specify the
threshold for differential routing TOLERANCE value
net_name_1 net_name_2 ...
END MATCH
-interleaveStyle Use the SPLITSTYLE keyword in the SPLITSTYLE RIVER | MESH

constraint file to specify the splitting style.
SPLITWID TH value
SPLITGAP value
SPLITKEEPTOTALWIDTH TRUE | FALSE
-multiBumpsToPad Use setFlipChipMode - setFlipChipMode -

multipleConnection multipleConnection
multiBumpsToPad instead. multiBumpsToPad
-multiPadsToBump Use setFlipChipMode - setFlipChipMode -
multipleConnection multipleConnection
multiPadsToBump instead. multiPadsToBump
-optWidth Use the exta configuration file option
srouteGrouteOptimizeWidth instead. srouteGrouteOptimizeWidth TRUE
-preventViaUnderBump Use setFlipChipMode - setFlipChipMode -

prevent_via_under_bump instead. prevent_via_under_bump true
-routeStyle Use setFlipChipMode - setFlipChipMode -route_style

route_style instead. {manhattan | 45DegreeRoute}
-shield Bump Use the SHIELDBUMP keyword in the SHIELDING
SHIELDING section of the constraint file to
specify whether bumps are to be shielded . SHIELDBUMP TRUE | FALSE
SHIELDWIDTH value
-shieldLayers Use the SHIELDSYLE keyword in the SHIELDGAP value
SHIELDSTYLE a | b | c
SHIELDNET netName
specify where shield layers are created.
<nets>
- shieldNet Use the SHIELDNET keyword in the END SHIELDING
specify the special net used to shield the net.
- shieldWidth Use the SHIELDWIDTH keyword in the

specify the width of the shield net.
-splitGap Use the SPLITGAP keyword in the constraint SPLITSTYLE RIVER | MESH
file to specify the minimum distance between
split wire segments. SPLITWID TH value
SPLITGAP value
-widthLimit Use the SPLITWIDTH keyword in the
constraint file to specify the maximum width SPLITKEEPTOTALWIDTH TRUE | FALSE
limit for each wire after the split :

Partitioning
11
Partitioning
Support for Promoting Macro Pins
New Parameters for Specifying Offset
Pin Editor Capability Enhanced
Specify Partition GUI Form Updated
alignPtnClone Command Enhanced
checkPinAssignment Command Enhanced
New Parameter to Specify Keep Out Spacing
Pin Constraint Commands Consolidated
Multi-threading Support for savePartition Command
Support for Saving and Loading Selective Floorplan Data
New Parameter Added to the savePartition Command
New Parameter Added to the assembleDesign Command
New set_ptn_fplan_mode Command Added
New get_ptn_fplan_mode Command Added

Support for Promoting Macro Pins
In this release, the -promoteMacroPin parameter has been added to the assignPtnPin
and the assignIoPins commands. Using this parameter, partition pins are promoted to hard
macro pins.
New Parameters for Specifying Offset

In this release, the -offset_start and -offset_end parameters have been added to the
createPinGuide and createPinBlkg commands to enable the user to specify a distance
(offset) from the starting co-ordinate of the edge to draw the pin guide (or pin blockage) and
similarly stop the pin guide (or pin blockage) at a certain distance from the ending co-ordinate.
Now, even if the floorplan is changed and the modules are moved to a different location, the pin
guides can easily be recreated by specifying the edge and offset instead of co-ordinates.

Partitioning
Pin Editor Capability Enhanced

In earlier releases, you could only specify one layer at a time while editing the pin lists. This
required you to run multiple passes when multiple layers were needed. In this release, the pin
editor capability has been enhanced to support the assignment pin lists to multiple layers.
Additionally, you now have a choice of multiple patterns for distributing the pins to the different
layers.
To accommodate this capability, the Pin Editor GUI form has been updated to allow assignment of
multiple layers:

Partitioning
Additionally, the editPin command has been updated to include the following new parameters:
-include_rectilinear_edge
Specifies that all the edges coming in the solution space should be included.
-layer_priority

Partitioning
Specifies that the input layer is given based on its priority.
-pattern {fill_track | fill_layer | fill_optimised |

fill_diagonal | fill_sinusoidal | fill_checkerboard}
Specifies the multi-layer-spread-pattern must be followed by the set of selected pins.
-reverse_alternate
Specifies that the reverse of the multi-layer-spread-pattern must be followed by the set of
selected pins.
For more information, refer to the syntax of the editPin command in the Text Command Menu
Reference.
Specify Partition GUI Form Updated

In this release, the Specify Partition GUI form has been updated to remove the Save Partition to
spec option that was use to output the partition assignment to the partition specification file. This
option was used by the specifyPartition command to load the partition definition. However,
since the specifyPartition command is now obsolete and will be removed in the next major
release of the software, the GUI has been updated to match the definePartition command
functionality.
alignPtnClone Command Enhanced

In this release, the alignPtnClone command has been enhanced to report clone pins that are
off the grid and align objects to correct tracks in double patterning (20nm) designs. The
alignPtnClone command now supports blackboxes.
The following new parameters have been added to the alignPtnClone command:
-layer layerV layerH
Specifies a vertical and a horizontal layer for checking alignment with the power grid.
-track
Checks the alignment of partition clones with the master on track basis. This parameter
only generates a report and does not modify the design.

Partitioning
checkPinAssignment Command Enhanced

The checkPinAssignment command checks the generated partition pins and I/O pins for
violations. By default, it check for the following pin violations:
Bus guide constraints.
Ordering and exclusion checks on nets.
Pin positions for abutted partitions.
Pin depth constraints.
Ordering and exclusion checks on pins.
Pin guide constraints.
Pin layer constraints.
Pins that are floating from inside the partition or floating from both inside the partition and at
the top level.
Pins that are placed on the fence.
Pins that are placed on layer tracks.
Pin spacing constraints.
Pin width constraints.
Pin violations on clones in a master clone design.
With enhancements in this release, the -ignore parameter has been added using which you
can choose to ignore any of the above mentioned violations while checking the pin assignment.
The following is the updated syntax of the checkPinAssignment command:
checkPinAssignment
[-help]
[topCellName | -ptn ptnName ]
[-pin { pinName | pinNameList }]
[-report_violating_pin ]
[-outFile fileName ]
[-ignore {bus_guide net_group pin_abutment pin_depth pin_group
pin_guide pin_layer pin_min_area pin_on_fence pin_on_track
pin_spacing pin_width clones}]
Additionally, the -report_violating_pin parameter has been added which reports the pins
with violations.
New Parameter to Specify Keep Out Spacing

Partitioning
In this release, you can use the new -keep_out_spacing parameter to specify minimum keep
out spacing for a pin group or net group. All pins that are foreign to the pin/net group will be
placed beyond the specified keep out spacing of the pin group.
This parameter has been added to the createNetGroup and the createPinGroup
commands.
Pin Constraint Commands Consolidated

In this release, the following commands related to Pin Constraints have been consolidated into
the setPinConstraint command. Consequently the setPinConstraint command has
been enhanced to support global cell level and pin level constraints.
setAllowedPinLayersOnEdge
setGlobalMinPinSpacing
setLayerPinDepth
setLayerPinWidth
setMinPinSpacing
setMinPinSpacingOnEdge
setPinDepth
setPinToCornerDistance
setPinWidth
Note: These commands are now obsolete as the setPinConstraint command provides the
required functionality . Even though they continue to work in this release, they will be removed in
the next major release of the software.
Similarly, the unsetMinPinSpacing command has been replaced by

the unsetPinConstraint command. This release also introduces the getPinConstraint
command which supports the global cell level and pin level constraints. The
getPinConstraint command replaces the following obsolete commands:
getAllowedPinLayersOnEdge
getGlobalMinPinSpacing
getLayerPinDepth
getLayerPinWidth
getMinPinSpacing
getMinPinSpacingOnEdge
getPinDepth
getPinToCornerDistance

Partitioning
getPinWidth
Earlier when constraints were specified for pin placement they got lost during the
saveDesign/restoreDesign cycle. With enhancements in this release, all the pin
constraints are retained even after the saveDesign/restoreDesign cycle and are honored
during pin assignment.
Impact on Other Commands, Parameters, and Globals: This change impacts commands
related to pin constraints.
Multi-threading Support for savePartition Command

In this release, multi-threading support has been added to the savePartition command. This
reduces the run time for huge designs by saving individual blocks parallely.
Support for Saving and Loading Selective Floorplan Data

In Gigascale designs, since multiple iteration are required, it is expensive to run partition and
assembleDesign for each iteration. With enhancements in this release, you can now quickly
pass new updated floorplan information such as partition boundary, pins, macro placement to the
partition block level and bring this data back to full chip level design from a partition block.
To enable this capability, the following changes have been made:
New Parameter Added to the savePartition Command
A new –fplan parameter has been added to the savePartition command for pushing
down floorplan changes from a full chip level design to a partition block. This option allows you to
run the savePartition command for an uncommitted partition without running the
partition command. For committed partition savePartition –fplan reports an error.
Note: After savePartition –fplan command, an un-committed partition still remains

uncommitted.
New Parameter Added to the assembleDesign Command
A new –fplan parameter has been added to the assembleDesign command to bring back
the floorplan changes from a partition block to full-chip level design. The assembleDesign -
fplan command only supports un-committed partitions and replaces the top level uncommitted
partitions with updated block floorplan data.
Note: After assembleDesign –fplan command, any signal net at top-level design may be
overlapped with other floorplan objects. You may need to reroute or ECO route the design.

Partitioning
Additionally, PG net of CHIP, place, and route data may not be brought back.
New set_ptn_fplan_mode Command Added
You can now use the new set_ptn_fplan_mode command to set what floorplan objects will
be written-out and/or read back in. The set_ptn_fplan_mode command allows you to specify
which objects should be written out during savePartition –fplan or read back in during
assembleDesign –fplan.
New get_ptn_fplan_mode Command Added
You can use the new get_ptn_fplan_mode command to retrieve information about the option
values set using set_ptn_fplan_mode command.

Floorplanning
12
Floorplanning
createPGPin Command Enhanced
createObsAroundInst Command is now Obsolete
add_ndr Command Enhanced
Support for Reporting Narrow Channels
Support for Handling Master/Clones in Different Hierarchy
Enhanced Power Domain Placement Capability
Enhanced Auto-shaping for Placing Modules
Support for Virtual fence Option to Handle User-specified Seeds
New Command to Generate Partition Fences Around Flexmodels
Support for Bus Guides in Relative Floorplan
Blackblob Capability made Obsolete

createPGPin Command Enhanced
EDI System now supports the creation of power/ground pins from selected power objects which
touch the DIE boundary. To support this capability, the –onDie parameter has been added to the
createPGPin command.
The following is the updated syntax of the createPGPin command.
createPGPin
[-help]
{-onDie {-selected | -net netName} [-width value] [-length value]} |
{pgPinName [-net netName] [-geom layerName llx lly urx ury]}
createObsAroundInst Command is now Obsolete

The createObsAroundInst command, which was used to create obstructions around a
specified instance, is now obsolete. It has been replaced by the createPlaceBlockage
blockage command that has more options than the createObsAroundInst command and is
used to create cell placement blockages that can be placed even outside the core area.

Floorplanning
The createObsAroundInst still works in this release but will not be supported in future
releases. To ensure compatibility with future releases, update your scripts to use the
createPlaceBlockage command instead.
add_ndr Command Enhanced

In this release, the –hard_spacing parameter has been added to the add_ndr command.
With this parameter specified, you can set the non-default rule to HARDSPACING.
Changes have also been made to the syntax of the add_ndr command. You can now specify
the name of the non-default rule using the add_ndr –name parameter.
Updated syntax of the add_ndr command is as follows:
add_ndr
[-help]
{ ndrRuleName | -name ndrRuleName }
[-init ndrRuleName ]
[-hard_spacing]
[-width {layer1[:layer2] width ... }]
[-spacing {layer1[:layer2] spacing ... }]
[-min_cut {layer1[:layer2] min_cut ... }]
[-via {via_name1 via_name2 ... }]
[-add_via {via_name1 via_name2 ... }]
[-generate_via]
Additionally, non-default rule manipulation commands like createNdr, initNdr,

modifyNdrViaList, setNdrSpacing, and setNdrWidth are now obsolete. These
commands have been replaced by the add_ndr command. To ensure compatibility with future
releases, update your scripts to use the add_ndr command instead.
Support for Reporting Narrow Channels

In earlier releases, it was difficult to report narrow channels with unwanted gaps between
placement blockages, two macros, placement blockage and boundary. In this release, the
checkFPlan command has been enhanced to report narrow channels whose width, in
microns, is smaller than a specified value. This functionality can be achieved by using the new –
narrow_channel parameter.

Floorplanning
Support for Handling Master/Clones in Different Hierarchy

With enhancements in this release, clones can now be in a different physical hierarchy than their
master where master/clones will have the same boundary shape.
Enhanced Power Domain Placement Capability

In this release, the planDesign has been enhanced to place power domains inside the core
boundary without any overlaps with other flexModels or macros (especially rectilinear macros).
This has improved the QoR of power domain placement.
Enhanced Auto-shaping for Placing Modules

With enhancements in this release, the Automatic Floorplan Synthesis capability now
automatically generates better module shapes (including rectilinear shapes) to have a correct
utilization. Now, it does not leave many empty spaces/gaps between flexModels.
Support for Virtual fence Option to Handle User-specified Seeds

In the previous release, the planDesign capability did not honor guide boundaries.
Consequently, during macro packing, macros in guide constraints (both user specified guides and
automatically created guide constraints) were packed along the chip boundary as shown in the
following image.
Even the macros belonging to the same guide were separated as the guide boundary was
ignored.

Floorplanning
In this release, the –virtualFence parameter has been added to the setPlanDesignMode
command. This parameter enables planDesign to internally treat guide constraints as fences.
Thus, their boundaries are strictly honored. Now macros are packed on the guide boundary which
helps to achieve a better grouping of macros.
To have guide constraints, you can set the createFence constraint while using the
planDesign capability. In seed constraint creation:
BEGIN SEED
name = xxx [createFence = TRUE]
END SEED
When createFence constraint is not set, the seed will be treated as a guide. Also, auto seed
generation feature will group unconstrained macros into guides. When the –virtualFence
option is specified in setPlanDesignMode, the guide constraints will have their boundaries
honored.
New Command to Generate Partition Fences Around Flexmodels

In earlier releases, after floorplanning, you had to manually draw a partition fence boundary in
order to enclose all its children flexModel guides. This had to be done for each partition and was
quite tedious.
In this release, a new generate_fence command has been introduced using which partition
fences, which enclose all their children flexModel guides, can be drawn automatically. This
capability improves the usability of the prototyping flow.
The following is the syntax of the generate_fence command:
generate_fence

Floorplanning
[-help]
[-min_gap float]
[-target_util float]
[ [-hInst {hInst(s)}] | [-module {module(s)}] | [-inst_group
{instGroup(s)}] ]
Support for Bus Guides in Relative Floorplan

In this release, bus guide support has been added to the relative floorplan capability. This
enhancement avoids having to re-design bus guides after small floorplan refinements, like, little
movements of macros and partitions or stretches of partitions. Now, when the master object is
moved, the bus guide segments which had been constrained will be moved and will maintain
connectivity.
You can now use the autoGenRelativeFPlan -busGuide command to generate bus guide
segments connection.
Also, use the relativeFPlan command to generate a constraint, bind one bus guide
segment to one reference object. The following parameters have been added to the
relativeFPlan command:
relativeFPlan
[--masterSlave {-masterType masterType -masterName masterName -slaveType slaveType -
slaveName slaveName}]
Blackblob Capability made Obsolete

In this release the Blackblob capability has been made obsolete. The flexModel is a super set of
blackblob capabilities. With the support of flexModels, it removes the need for using blackblobs.
The flexModels should be used for prototyping instead.
The following commands have been removed from the software:

elaborateBlackBlob

Floorplanning
specifyBlackBlob
unplaceBlackBlob
unspecifyBlackBlob

Structured Data Path
13
readSdpFile Command Enhanced To Support More Than 10 skipSpace Variables
Support Added for Reusing SDP Instantiations
New Buttons in the SDP Browser

readSdpFile Command Enhanced To Support More Than 10
skipSpace Variables
The readSdpFile command reads in a relative placement file (in .sdp format) and then calls
placeSdpGroup to place all the structured data path (SDP) elements defined in the file. In previous
releases, you could specify only up to 10 variables for skipSpace in the .sdp file. In this release,
this restriction has been removed so that you can define as many skipSpace variables as
required.
Support Added for Reusing SDP Instantiations

In traditional structured data path design, a low-level data path corresponding to a hierarchical
module in a netlist may need to be reused many times in other data paths. With the SDP syntax
supported in previous releases, you had to re-specify this low-level data path each time it had to
be instantiated in other data paths. This made the SDP file bigger and difficult to use.
To improve usability, the SDP file format in this release has been enhanced to support reuse
capability. The data path macro definition can be specified with the new define keyword. Once
specified, this macro definition can be instantiated or and then used multiple times in a data path
specification by using the use keyword.
The SDP reader has been enhanced to handle the new SDP syntax, including nested macro
definitions. The SDP reader can also handle SDP macro definitions that are in a separate SDP file
than the data path that references them.
New Buttons in the SDP Browser

The following buttons have been added to the SDP Browser to make it easier to use:
clear : Use the clear button to clear any existing text string in the Find text input field.
Top : Use the new Top button in the SDP Browser to return to the top of the structured

data path quickly. In previous releases, you had to click the Previous button several times
or restart the browser to return to the top view of the SDP browser.

Multiple Supply Voltage (MSV)
14
Multiple Supply Voltage (MSV)
New Options for optPowerSwitch
New Options for reportPowerDomain
New Option for replacePowerSwitch

New Options for optPowerSwitch
The command optPowerSwitch has the following new variables:
-setDontUseCells that prevents the specified library cells from being used during
power switch ECO function.
-idsatmargin that scales the power switch instance current according to the margin
value specified. This scaled power switch instance current value is then used for
computation in resize mode operation.
-reportOnly that reports the power switch instance currents, the downsize and upsize
information to the file fileName.rpt without performing any power switch optimization.
-area enables power switch ECO to optimize the power switch instances within area
defined by this parameter.
New Options for reportPowerDomain

The command reportPowerDoman has the following new variables:
-pin: Lists the pins and the option is of type string Pin1, Pin2 .... This option is
optional.
-verbose: Prints out the detail information and is optional.
New Option for replacePowerSwitch

The command replacePowerSwitch has a new variable -xyRangeFromCenterInst that
selects the power switch instances whose lower left corner is in the range from lower left corner of
the specified instance (-insts) for replacement with switch cell (-cell).

NanoRoute Router
15
NanoRoute Router

NanoRoute Support for LEF Properties Enhanced
getNanoRouteMode and setNanoRouteMode Commands Modified
Enhanced Violation Marker Support

NanoRoute Support for LEF Properties Enhanced
In this release, the NanoRoute router has been enhanced to support PARALLEL for cut to metal
CONCAVECORNER LEF property.
For more information, see the “LEF Syntax” chapter of the LEF/DEF Reference.
getNanoRouteMode and setNanoRouteMode Commands Modified

In this release, the following parameters of the getNanoRouteMode and setNanoRouteMode
commands have been made obsolete:
-dbCheckRule
-dbReportWireExtraction
-dbReportWireExtractionEcoOnly
-drouteAutoCreateShield
-drouteCheckMinstepOnTopLevelPin
-drouteElapsedTimeLimit
-routeAutoGgrid
-routeDeleteAntennaReroute
-routeInsertAntennaInVerticalRow
-routeMergeSpecialWire
-routeSiEffort
-routeTdrEffort
-routeUseBlockageForAutoGgrid

NanoRoute Router
-routeWithSiPostRouteFix
-timingEngine
Note: The obsolete command parameters have been removed in this release and have not been
replaced. Update your scripts to avoid warnings and to ensure compatibility with future releases.
Enhanced Violation Marker Support

In the previous release, the violation markers only indicated the location of the violation. They did
not guide you to the nature of the violation. With enhancements in this release, the marking box
provides full information about the violation including error type, layer name, net object, location,
and a description in the violation browser.
The Nanoroute DRC markers are edge based markers which are in design view and Violation
Browser.

TrialRoute Router
16
TrialRoute Router

TrialRoute Support for get_metric APIs

TrialRoute Support for get_metric APIs
The trialRoute now supports get_metric APIs and enables you to query existing routing
metrics at command line.
To enable this capability, routeDesign just calls the 'get_metrics' API after generating the
routing metrics.
For more information, see the Design Metrics chapter of the EDI System Text Command
Reference .

Timing Budgeting
17
Timing Budgeting
Power Pin Support in Budgeted Timing Models for Low Power Designs
Justify Budget Enhanced

Power Pin Support in Budgeted Timing Models for Low Power
Designs
In a variation of the CPF-based flow, the CPF file contains only power domain information and
assigns timing libraries to them. Since voltages are not defined in the CPF file, the voltage
information comes from these timing libraries through constructs like voltage_map, pg_pin,
related_power_pin and related_ground_pin. Previously, these constructs were not
supported in the timing models generated by budgeting. It is important to have this voltage
information in budgeted timing models to ensure that the top-level flow is able to use the budgeted
.lib containing the power and ground pin information for an accurate CPF-based flow.
Timing Budgeting has been enhanced to support PG pins in budgeting timing models. Therefore, if
a full-chip design has libraries defined with PG pins, timing libraries generated for each
instance/block will have voltage information. To support this enhancement, the budgeting timing
library now imports the following constructs from the full-chip library:
Voltage Maps - are written for all the voltages that are coming inside a partition/instance
for which the timing model is being written.
voltage_map( vdd, 0.903 );
This information is at the library level. Every voltage has a name given and a value is
associated with it.
Cell Level PG Pin Information - For each voltage map, a related pg pin is defined for the
cell. It will have a pin name and the voltage name it is to be connected to.
pg_pin ( vdd ) {
voltage_name : vdd;
pg_type : primary_power;
direction : input;
physical_connection : device_layer;
}

Timing Budgeting
This information is at the cell level. The pins described in this definition are global in the library
scope. All the pins in the library are considered to be connected to one of these pins.
Pin Level PG Information - At each port of the partition/instance, there will be a related
pg_pin construct that specifies from which power/ground pin is the port being driven.
pin (q) {
related_power_pin : vdd;
related_ground_pin : vss;
.....
Justify Budget Enhanced

In earlier releases, when you changed the budgets on a port using the modifyBudget
command, the justify budget report would still show the original budget instead of the modified
budget. The justify budget report has now been enhanced to display the modified budget and the
justification for that (user applied or derived from user applied), thereby ensuring accuracy.
For manual budgeting, the budget of the port can change in the following scenarios:
When you directly apply a constraint on the port, the justify report shows the location of the
file from which the constraint has been taken, the applied constraint, and the port on which
it was applied.
Partition: block
Port: sub_in
Budgeted constraint type: set_input_delay(setup rise)
Virtual Clock: clk1_setuphold
Budget Applied by modify budget statement (/../../modify.tcl:3) :
set_input_delay 1.9 -clock [get_clocks {clk1_setuphold}] -
max -rise [get_ports {sub_in}] -add_delay
Applied constraint = 1.900
Start clock: clk1 clock edge: rise
End clock: clk1 clock edge: rise
When you apply a constraint on a connected port, the budget of that port also changes.
The output port will be impacted due to modification at the input port as it is one continuous
path. Budgets are modified at the output port by adjusting the required time of the port with
the extra delta delay given to (or taken away from) the connected port. Therefore, the
modifications at the input port is reflected in the justify report for both the input port and the
output port, wherein, the budgets are being recalculated for the output port based on the
modification.
The justify report has information about the port, the delta and how that delta affected the
constraint value at the given port.
Budget Impacted by modify budget statement (location of the file in which the
applied constraint is specified) :

Timing Budgeting
set_input_delay 1.9 -clock [get_clocks {clk1_setuphold}] -

max -rise [get_ports {sub_in}] -add_delay
Impact of modify budget(modDelta) = 0.911
Available budget after adjustment(AvailTime)=(10.000 - 2.982) - (0.911) = 6.107

RC Extraction
18
RC Extraction
RCDB Reading Enhanced to Fix Errors
New Command for Providing Information about the Contents of the RCDB
Obsolete Command Parameters - Removed from the Software
TQRC/IQRC Enhanced to Complete Broken RC Networks
TQRC/IQRC Enhanced to Perform Incremental Extraction After defIn and Metal Fill
Commands
Accuracy of PreRoute Extraction Enhanced for Signal Nets
Reduction in Peak Memory Consumption by spefIn in Sequential Mode

RCDB Reading Enhanced to Fix Errors
Earlier, the RCDB flow was disrupted if there was any inconsistency between the design netlist
and the RCDB. For example, if the design was modified before loading the corresponding RCDB,
the software gave an error message.
This behavior is unlike that of the SPEF file-based flows that continue even if there is a
design/RCDB mismatch. In this release, the EDI System is enhanced so that the QRC-RCDB flow
also continues to run in such situations. For this, the command, read_parasitics, is
enhanced to do error checking and fixing during RCDB reading. This command fixes the data
when a single flat RCDB is read by using the -force parameter of this command.
Impact on Other Commands, Parameters, and Globals:None
New Command for Providing Information about the Contents of

the RCDB
In this release, the EDI System is enhanced to provide you a mechanism to check the basic
contents of the RCDB being read so that they can debug the issues related to RCDB reading, if
required. For this, a new command, report_rcdb is provided that displays the contents of the
RCDB being read. This command can be used to report all the information about the RCDB
contents such as the RCDB version, the OS bit (64bit/32bit), whether the RCDB contains node
locations or not, coupled or decoupled data, statistical data, number of corners, RCDB source
(QRC or Encounter), and so on.

RC Extraction
The command has the following syntax:
report_rcdb
-help
<rcdb_dir_name>
Obsolete Command Parameters - Removed from the Software

The following command parameters have been removed from the software:
setExtractRCMode
-ipdb <dirname>
This parameter used the interconnect parasitic database (ipdb), which allowed faster direct
access instead of the RCDB. This feature is now ON by default.
setExtractRCMode
-noReduce {true | false}
This parameter was used to specify that the software should NOT perform RC reduction. It
is no longer required because the software does not perform RC reduction by default.
setExtractRCMode
-rcdb {filename}
This parameter was used to specify the RCDB output filename. It is no longer required
because the software generates the RCDB in the current working directory by default
unless you have specified an alternative location, using either the FE_TMPDIR or the
TMPDIR variable.
setExtractRCMode
-scOpTemp
This parameter was used to specify the derating value to be used in single-corner analysis
mode. This parameter is obsolete because it is not supported in the MMMC mode. Use
the -T parameter of the MMMC commands, create_rc_corner and
update_rc_corner instead.
setExtractRCMode
-useNDRForClockNets {true | false}
This parameter was used to specify the non-default rules from LEF to calculate the
approximate shielding and spacing values, instead of using the density values. This feature
is ON by default.
spefIn
-dumpMissedNet mnFileName
This parameter was used to provide a detailed listing of all the missing nets to the
file, mnFileName . It is no longer required because the software prints the missing nets in

RC Extraction
the file, rc_corner_name.missing_nets.rpt by default.
TQRC/IQRC Enhanced to Complete Broken RC Networks

Earlier, if the routing of a net was incomplete or broken, TQRC/IQRC skipped the extraction for
these nets. On analysis, it was found that this resulted in slowing down the delay calculation.
In this release, TQRC/IQRC is enhanced to complete the RC networks of broken nets by adding
low value resistors. The timing value for such nets may not be as accurate as that for other nets
but it is better than when the extraction of broken nets was skipped entirely.
TQRC/IQRC Enhanced to Perform Incremental Extraction After

defIn and Metal Fill Commands
For 65nm and lower geometry nodes, TQRC and IQRC extraction engines are recommended for
postRoute flow and ECO steps, respectively. These extraction engines have better correlation with
signoff extraction engines such as QRC. However, along with better accuracy these extraction
engines also have a higher runtime when compared to detail extraction.
Although this runtime can be reduced by using the multiCPU mode, a much larger runtime
improvement comes from performing incremental extraction where extraction is either skipped or
performed on fewer nets depending on the design/route changes in flow runs.
Currently, incremental extraction capability of TQRC/IQRC is not available after running defIn and
metal fill commands. Therefore, TQRC/IQRC is forced to perform fullchip extraction after running
defIn and metal fill commands.
In this release, TQRC/IQRC incremental extraction support is extended to all types of gray data
changes (defIn) and metal fill changes. The performance, accuracy, and memory will remain the
same as that of the rest of the commands currently supported by incremental extraction.
Accuracy of PreRoute Extraction Enhanced for Signal Nets

Earlier, a significant scale factor variation was seen both across different corners of the same
design and across the same corner of different designs, especially for lower nodes. It was also
seen that even a minor netlist change resulted in a large variations in scale factors in some cases.
In this release, the accuracy of preRoute extraction for signal nets is enhanced so that these large
scale factor variations are controlled and remain close to the signoff extraction results for
most designs.
Reduction in Peak Memory Consumption by spefIn in Sequential

RC Extraction
Mode
Earlier, the peak memory consumption during sequential spefIn was almost double that
consumed during multiple-CPU spefIn .
In this release, the software is enhanced so that the peak memory consumption during
sequential s pefIn is as low as that during multiple-CPU spefIn .

Timing
19
Timing

Constraint Handling Enhancements
Ability to Override Local Clock Latency Value
Reporting Enhancements
Added New Global Variable to Track Reported Paths Limit
Ability to Report on AOCV Stage Counts
Timing Report Enhanced to Show Markers for Pins
Added New Command to Report AOCV Derating Factors
Added New Parameters for Statistical Derating
Ability to Perform Arc-Based AOCV Weight Analysis
Added New Global to Improve Reporting of Clock Objects
Added New Property Attribute
Added New Property to Report Constants
Added New Library Properties
Report_timing Command Enhanced
Timing Modeling
Ability to Perform AOCV-Based ETM Extraction
do_extract_model Command Enhancements
Other Enhancements
Ability to Perform AOCV Analysis on Data Paths
Added New Property to Report Macros
Added New Global to Control Clock Reconvergence

Constraint Handling Enhancements
Ability to Override Local Clock Latency Value
The set_clock_latency -clock_gate parameter has been added to allow setting the local clock
latency value on pin or port objects. This setting overwrites the existing latency value of clock
gating cells and is used when performing timing checks against the specified pins or ports.
Reporting Enhancements
Added New Global Variable to Track Reported Paths Limit

Timing
You can use the timing_report_enable_max_path_limit_crossed variable to determine if the

number of reported paths for a particular clock group equals the specified maximum paths limit.
When this global is set to true, the software will issue a warning message in case the number of
reported paths for a clock group is equal to the given maximum paths limit. This applies to both
graph- and path-based reporting modes.
Impact on Other Commands, Parameters, and Globals: This variable is supported in clock
group-based non-statistical reporting flows only. The clock group-based reporting mode can be
enabled by setting timing_path_groups_for_clocks variable to true.
Ability to Report on AOCV Stage Counts

You can query on graph-based AOCV stage counts for timing arcs. The following new properties
have been added to get_property and report_property commands:
Data Path:
aocv_stage_count_data_early: Returns AOCV stage count values for a timing arc
on an early data path.
aocv_stage_count_date_late: Returns AOCV stage count values for a timing arc
on a late data path.
Launch Clock Path:

aocv_stage_count_launch_clock_early: Returns AOCV stage count values in
AOCV mode for a given timing arc that is a part of early launch clock paths.
aocv_stage_count_launch_clock_late: Returns AOCV stage count values in
AOCV mode for a given timing arc that is a part of late launch clock paths.
Capture Clock Path:

aocv_stage_count_capture_clock_early: Returns graph based AOCV stage
count values in AOCV mode for a given timing arc that is a part of early capture clock
paths.
aocv_stage_count_capture_clock_late: Returns graph based AOCV stage
count values in AOCV mode for a given timing arc that is a part of late capture clock paths.
You can specify report_timing -format stage_count option to view “Aocv Stage Count”
column in the report output.
Impact on Other Commands, Parameters, and Globals: This enhancement impacts the following
property query commands:
get_property [get_arcs –from * -to *] propertyName
list_property –type timing_arc
report_property [get_arcs –from * -to *]

Timing
Timing Report Enhanced to Show Markers for Pins

The report_timing command output has been enhanced to display markers that identify the pins
specified using the –from, -to, or -through parameters. This feature provides better
readability. The markers, displayed as ‘->’, show up in the ‘timing point’ or ‘ hpin’ column (if the
‘timing point’ column is not available) of the timing report.
To enable this feature, you can set the timing_report_enable_markers global variable to true. By
default, this global is set to false.
Added New Command to Report AOCV Derating Factors

The following command has been added to report AOCV derate factors in path based AOCV
analysis mode:
report_pba_aocv_derate
The report contains details of all the cells and the worst derating applied on each cell for all the
reported paths. This command is supported in AOCV mode only.
Impact on Other Commands, Parameters, and Globals: Using this command might result in
increased runtime.
Added New Parameters for Statistical Derating

The following parameters have been added to the set_timing_derate command to allow derating
factors for statistical data:
-corner: Applies derating on cells or nets that are modeled as corner data elements. The
specified derating factor is applied to both the mean and sensitivities of the delays (corner
objects can have propagated sensitivities).
A cell with no timing arc data in a library that has any sensitivity information with respect to any
parameter defined in SPDF are considered as a corner object. All cells that do not qualify this
are considered to be statistical objects.
A net with parasitic data that has no sensitivity information with respect to any parameter
defined in SPDF is considered as a corner object. All nets that do not qualify this are
considered to be statistical objects.
-statistical: Applies derating on cells or nets that are modeled as statistical data
elements. The specified derating factor is applied to both the mean and sigma of delays.
If both set_timing_derate –corner and –statistical options are not specified,

the derating factor is equally applied on variation and corner objects. This is equivalent to
issuing two separate set_timing_derate commands, one with –statistical option
and another with –corner option.

Timing
Ability to Perform Arc-Based AOCV Weight Analysis

The following enhancements have been made:
The define_property/set_property command allows you to perform arc-based AOCV
weight analysis. You can use the following library property:
aocv_weight
For example,
define_property -type float -object_type lib_arc aocv_weight

set_property [get_lib_arcs -of_objects slow/INVX1] aocv_weight 8
The software uses this property during analysis for computing the stage count.
To display AOCV weight values in the timing report, you can specify report_timing –
format aocv_weight option. This enables reporting of column named “Aocv Weight” in
the timing report, which shows the respective AOCV weights on path elements.You can
also use the get_property command to return AOCV weight values.
Added New Global to Improve Reporting of Clock Objects

Earlier, the software identified some of the pins as clock network pins instead of data pins. This
following new global variable has been added to improve reporting of pins:
timing_property_clock_used_as_data_unconstrained_clock_source_paths
: When set to true, the is_clock_used_as_data timing property returns true
irrespective of whether the clock source path is constrained or unconstrained.
Added New Property Attribute

The get_property command now supports the timing_model_type property for cells and
instances. This property indicates the model type for a given cell or instance. The supported
values are abstracted, extracted, and qtm.
Added New Property to Report Constants

The get_property/report_property command has been enhanced to report constants on pins or
ports. The following new property has been added:
user_constant_value: Returns constant values from netlists or constraints.
Added New Library Properties

The get_property/report_property commands support the following library attributes:

Timing
slew_lower_threshold_pct_fall: Returns the value of lower threshold point used

in modeling the delay of a pin falling from 1 to 0.
slew_upper_threshold_pct_fall: Returns the value of upper threshold point used
to model the delay of a pin falling from 1 to 0.
slew_lower_threshold_pct_rise: Returns the value of lower threshold point used
to model the delay of a pin rising from 0 to 1.
slew_upper_threshold_pct_rise: Returns the value of upper threshold point used
to model the delay of a pin rising from 0 to 1.
slew_derate_from_library: Specifies how the transition times found in the library
need to be derated to match the transition times between the characterization trip points.
input_threshold_pct_fall: Returns the value of threshold point on an input pin
signal falling from 1 to 0, which is used in modeling the delay of a signal transmitting from
an input pin to an output pin.
input_threshold_pct_rise: Returns the value of threshold point on an input pin
signal rising from 0 to 1, which is used in modeling the delay of a signal transmitting from an
input pin to an output pin.
output_threshold_pct_fall: Returns the value of threshold point on an output
signal falling from 1 to 0, which is used in modeling the delay of a signal transmitting from
an input pin to an output pin.
output_threshold_pct_rise: Returns the value of threshold point on an output
signal rising from 0 to 1, which is used in the modeling of a signal transmitting from an input
pin to an output pin.
Report_timing Command Enhanced

Earlier, the report_timing command reported all the paths for clocks generated on specified pins or
ports. Now, the command filters out wrong paths, and displays only the valid paths.
For example, if a generated clock apll1/CLKI is created on pin apll1/CLKI, then the
following command will only display the valid paths:
report_timing -clock_from apll1/CLKI -to [ get_pins apll1/CLKI]
Timing Modeling
Ability to Perform AOCV-Based ETM Extraction
The following global variable has been added to allow specification of AOCV derating mode:
timing_extract_model_aocv_mode
The valid values are:

graph_based: Specifies that the delays in the timing model are derated using the

Timing
graph-based stage counts.

path_based: Specifies that the delays in the timing model are derated using the
total path stage count of worst path between those pin pairs.
none: Specifies that the delays in the timing model are underated base delays.
By default, this variable is set to none.
do_extract_model Command Enhancements

The following new parameter has been added to the do_extract_model command:
–pg: Allows power or ground related pin information to be extracted inside the extracted
model.
Other Enhancements
Ability to Perform AOCV Analysis on Data Paths
The timing_aocv_analysis_mode global variable has been enhanced to support the
capability of counting the number of stages of launch/capture clock and data paths separately in
the AOCV flow. The following new option has been added to support this feature:
separate_data_clock: Calculates the AOCV stage count for clock paths and data
paths separately. Both clock and data paths have related AOCV derating factors.
Added New Property to Report Macros

You can use the following new get_property/report_property option to query on timing
library cells:
is_interface_timing: Returns a value of true if a library cell has interface timing
specified for that cell.
Added New Global to Control Clock Reconvergence

The following new global allows you to specify the branch point to use for computing clock path
pessimism removal (CPPR) adjustment when there is reconvergence in the clock tree:
timing_cppr_skip_clock_reconvergence
When set to false, the software uses the branch point closest to the register clock pins where
the clocks reconverge. When set to true, the software uses the farthest branch point from the
register clock pins (that is, the branch point closest to the clock root pin where the clocks diverge).
By default, this global is set to false.

Timing Debug
20
Timing Debug
New Options for load_timing_debug_report
The command load_timing_debug_report has the following new options:
-additonal_slack_past_wns: Reports all the paths with slack worse than WNS and
the additional specified slack value.
-num_path: Specifies the number of paths to be reported in the detailed path violations.
-proto: Creates flex model categories and displays the top path of the top 8 (by default)
categories. This option can be used for design that has flexModels.

Verification
21
Verification
New Command To Support 20nm and Lower DRC Rules
Verify Geometry Enhancements
Option -minPinArea Now Obsolete
Option -warning Now Obsolete
Violation Browser Enhancements
Auto Zoom Enhanced To Display Only Active Layers for Violations
Option Added for Limiting Number of Errors Displayed Per Type
Support Added for Complex Logical Expressions for Filtering Violations
New Forms Added for Loading and Saving DRC Markers

New Command To Support 20nm and Lower DRC Rules
EDI System now supports DRC check of 20nm and lower designs. As verifyGeometry does not
support 20nm DRC rules, this release introduces a new command, verify_drc, for 20nm and lower
DRC rules check. Using verify_drc, you can check for DRC violations in a specified area or
layer range in a 20nm design. You can also choose to check only special wires or cells.
verify_drc can also be used for 28nm and above rules. However, you need a 20nm license to
use verify_drc. Therefore, you can continue to use verifyGeometry for DRC check of
28nm and above designs.
Impact on Other Commands, Parameters, and Globals: If you use verifyGeometry for a
20nm design, EDI System displays the following warning:
The verifyGeometry command does not support 20nm and below advanced rules. Use verify_drc instead.
Verify Geometry Enhancements

Option -minPinArea Now Obsolete
Option -minPinArea of the verifyGeometry command is now obsolete. Use the -
sameCellViol option instead to report the minimum area violations for pin shapes in the cell,
along with other cell violations. Although the obsolete option still works in this release, update your
script to use -sameCellViol instead to ensure compatibility with future releases.
Impact on Other Commands, Parameters, and Globals: getVerifyGeometryMode -

minPinArea and setVerifyGeometryMode -minPinArea are also now obsolete.
Option -warning Now Obsolete

From this release, option -warning of the verifyGeometry command is obsolete. This
option is being removed as Verify Geometry does not issue warning markers.
Impact on Other Commands, Parameters, and Globals: getVerifyGeometryMode -

warning and setVerifyGeometryMode -warning are also now obsolete.
Violation Browser Enhancements

Auto Zoom Enhanced To Display Only Active Layers for Violations
The Layer field in the Violation Browser displays the layer on which each violation occurs. When
you select a violation in the browser, the Auto Zoom feature automatically zooms into the violation
in the main window display. However, in previous releases, you then need to manually turn off
display of other layers so that you can focus on the layer in which the violation occurs. In this
release, the Auto Zoom feature in Violation Browser has been enhanced to display only the active

Verification
layers related to the selected violation marker. The active layers for a violation includes the layer
on which the violation occurs and the adjacent layers. This enhancment makes it easier for you to
review a violation.
Option Added for Limiting Number of Errors Displayed Per Type

When loading a large DRC file with millions of violations, the EDI System database can become
very slow. In this release, you can use the new -max_error_per_type option of the
violationBrowser command to specify a limit for the number of violations parsed for each violation
type. The Violation Browser then parses only the specified number of violations from the DRC file
for each type of violation. For example, if you set violationBrowser -
max_error_per_type 500, the Violation Browser parses only 500 markers per error type.
This enhancement prevents the database from becoming very slow while loading large DRC files
and makes it easier for you to review violation markers in the browser.
You can also specify the maximum number for each error type from the GUI by using the Error
Per Type option in the Violation Browser Settings form.

Verification
By default, the Violation Browser displays all markers.
Support Added for Complex Logical Expressions for Filtering Violations

In previous releases, you could use only one of the AND, OR, and NOT conditions for filtering
violations. Now, you can use complex expressions with multiple logical operators to filter violations.
For example, if you want to view only the violations occuring on Metal4 or Metal5 layers and
want to exclude short violations, you can use the following filter string with the new -
filter_query option of the violationBrowser command:
!Short*(M4+M5)
Here:
! refers to the NOT condition.
x specifies the AND condition.
+ specifies the OR condition.
New Forms Added for Loading and Saving DRC Markers

You can now load and save database DRC markers directly from the Violation Browser using the
highlighted optons in the Violation Browser.

Verification
Click Save to save the DRC file. This opens a form that allows you to specify the path and name
for saving the DRC file. This is equivalent to using the saveDRC command.
Click Load to load an existing database DRC file. This opens a form in which you can browse and
select the DRC file to be loaded. This is equivalent to using the loadDrc -incremental
command.

Power Calculation
22
Power Calculation
read_activity_file Parameters Consolidated
Multi-Threading Support for Dynamic Vector-Based Power Analysis Flow
Power Analysis Reporting Enhanced
Clock-Gating Efficiency Reports Improved
Variation in Switching Power Numbers when Running Power Analysis from EDI

read_activity_file Parameters Consolidated
In this release, nine parameters of the read_activity_file have been made obsolete, and
have been consolidated into three new parameters to simplify and streamline the use model. The
following table lists the obsolete parameters, and the command parameters that replace them:
Obsolete Parameters Replaced with
-scale_tcf_duration scalefactor -scale_duration scalefactor

-scale_fsdb_duration scalefactor
-scale_vcd_duration scalefactor
-fsdb_block fsdb_block_name -block block_name

-tcf_block tcf_block_name
-vcd_block vcd_block_name
-fsdb_scope fsdb_scope_name -scope scope_name

-tcf_scope tcf_scope_name
-vcd_scope vcd_scope_name
The enhanced read_activity_file command provides the needed functionality for the
obsolete parameters. The obsolete parameters still work in this release but a warning message
will be displayed stating that these parameters will not be supported in a future release.
Multi-Threading Support for Dynamic Vector-Based Power

Analysis Flow

Power Calculation
The Power Analysis engine has been enhanced to support multi-threading in the dynamic vector-
based flow. In the multi-threading mode, a job is divided into several threads, and multiple
processors in a single machine process them concurrently. The multi-threaded processing mode
can be specified using the following existing commands:
set_distribute_host –local
set_multi_cpu_usage -localCpu 4
These commands are used to control the number of CPUs to be used on a local machine for
multi-threading. Multi-threading provides better runtime for both the VCD/FSDB based dynamic
vector-based flows as compared to previous releases.
Power Analysis Reporting Enhanced

Previously, the following reports were generated by Power Analysis in the working directory:
powerAnalysis.cmdlog
powerAnalysis.summary.log
powerAnalysis.log
The following enhancements have been made in this release:

powerAnalysis.cmdlog and powerAnalysis.summary.log reports have been
removed.
powerAnalysis.log file has been moved to the output directory where all the power
analysis results are written out.
improved error message logging in the log file eps.log and the verbose log file
eps.logv. The eps.log file will contain limited number of WARNING/ERROR messages
and the eps.logv file will contain detailed and meaningful information.
The enhanced log files contain detailed analysis information that can be used for debugging
purpose.
Clock-Gating Efficiency Reports Improved

The Clock Gate Efficiency (CGE) and Register Gating Efficiency (RGE) reporting have been
improved to include toggles savings for each integrated clock gate (ICG). These reports now
highlight toggle savings due to clock gating in the design, hierarchical view of toggle savings, and
register gating opportunities.
When you generate a CGE report using the command report_power –

clock_gating_efficiency –outfile cge.rpt, the following information will be
displayed:

Power Calculation
Clock-gating Efficiency Report - for each clock domain, it includes the toggle rate,
number of registers, number of clock gates, average clock toggle at registers, average
toggle savings at registers, and average toggle savings histogram.
Hierarchical View of Average Toggle Savings - number of clock gates and average
toggle savings for each hierarchical module in the design
When you generate an RGE report using the command report_power –

register_gating_efficiency –outfile rge.rpt, the following information will be
displayed:
Register-gating Efficiency Report - for each clock domain, it includes the toggle rate,
number of registers, number of clock gates, average clock toggle at registers, average
toggle savings at registers, and average toggle savings histogram.
Register Gating Opportunities Report - this report is sorted based on the Q/CLK toggle
ratio. When a register's Q/CLK ratio is greater than .25 (25%), Q toggles every other clock
cycle. However, when it is less than 25%, there is a gating opportunity to reduce power.
The –cluster_gating_efficiency parameter has been added to the report_power

command to generate the cluster efficiency report in the RGE report. This report gives the
CGE/RGE metrics for the registers at the fanout of each clock gate instance in the design.
Variation in Switching Power Numbers when Running Power

Analysis from EDI
In this release, there has been a default change in pre-route extraction in EDI that results in
change in switching power numbers as compared to previous releases.

Rail Analysis
23
Rail Analysis
Simplification of Auto-Fetch DC Sources Commands
Body Bias Analysis Supported
On-Chip Voltage Regulator Analysis Supported
Support for Region-Based Snapping
Edit Pad Location Form Enhanced
view_esd_violation Enhanced to View Bumps Within a Resistor Range
Ability to Control Layer Processing
Rail Analysis Reporting Improved
Support for Non Zero Capacitance Filler Cells for Decap Optimization Flow
Sub_Via Support Added
Change in Extraction Results for Designs with Dangling Resistors
Via Clustering Enhanced
New Parameters to Ignore Filler and Decap Cells

Simplification of Auto-Fetch DC Sources Commands
In this release, seven voltage source generation commands are made obsolete, and are
consolidated into the new command create_power_pads . The create_power_pads
command has been added to simplify voltage source generation, and provide the needed
functionality for the obsolete commands. The obsolete commands still work in this release but a
warning message will be displayed stating that these commands will not be supported in a future
release.
The following table lists the obsolete commands, and the new command parameters that replace
the obsolete commands:
Obsolete Command Replaced With

auto_fetch_dc_sources Use one of the following three methods to fetch voltage
sources into the database:
fetch all voltage sources
create_power_pads –net net_name –

Rail Analysis
auto_fetch
fetch the voltage sources within the specified region of the

specified layer controlled by the specified xpitch/ypitch
create_power_pads -net net_name -region {x1 y1 x2
y2} –region_pitch {xpitch ypitch} –layer {LEF} -format xy -
vsrc_file filename
fetch voltage source for the specified cell/cell
pin/instance/instance pin
create_power_pads -net net_name -cell cellname -
format xy
create_power_pads -net net_name -cell_pin {cellname
pinname} -vsrc_file filename
add_pad_location This command has not been replaced.

clear_pad_loc_display Use the following command to clear the voltage source
displayed in the GUI and the fetched voltage sources in the
database:
create_power_pads -clear
delete_pad_location This command has not been replaced.
display_pad_loc and Use the following command to fetch, save, and display the
load_pad_location voltage sources:
create_power_pads -net net_name –auto_fetch -
vsrc_file filename -display
Use the following command to display voltage sources on
GUI by loading a saved voltage source file:
create_power_pads -vsrc_file filename -
display
save_pad_location Use the following command to save the fetched voltage

sources to a voltage source file:
create_power_pads -vsrc_file filename
Use the following command to append the fetched voltage
sources to an existing voltage source file:
create_power_pads -vsrc_file filename -
append_to_vsrc_file
As part of this enhancement, the following changes have been made to auto-fetch DC sources'

Rail Analysis
behavior:
Automatically fetch voltage sources on all layer shapes. Previously,
the auto_fetch_dc_sources command would only fetch the voltage sources on the
top connected metal layer.
Fetch multiple voltage sources for large shapes based on multiple connections. Previously,
the auto_fetch_dc_sources command would only fetch one voltage source for large
shapes with multiple connections.
Body Bias Analysis Supported

EDI System has been enhanced to support body bias designs, in which body bias nets (BVDD,
BVSS) are connected to body bias pins (NWELLPIN, PWELLPIN) of the cell. The main purpose of
body bias analysis is to prevent latch-up in the circuit, reduce leakage current, and optimize
performance. The following diagram illustrates body bias connectivity:
To support this enhancement, the following changes have been made:

Library Characterization - the body bias pins are defined by the WELL layer in the LEF
macro. The pins are connected via the tap cell (M1-CONT-DIFF/WELL) for top-level body
bias power routing. The WELL layer is mapped to the DIFF layer in the lefdef layer map,
therefore, current sinks will be attached to the DIFF layer. You can use the new parameter
–create_diff_layer_ports of the characterize_power_library command
to create the DIFF layer ports of body bias pins in PGV.
Power Analysis -The bias pin definitions are read from the liberty (dotlibs) libraries. With

Rail Analysis
body bias pin definitions in liberty, the power and ground pins with type PWELL and NWELL
will be regarded as body bias pins. You can use the new parameter –bulk_pins of the
set_power_analysis_mode command when library cells have bulk pins defined in
LEF but the liberty file does not contain power associated with these pins. If a liberty file
does not have body bias definition, power analysis does not distribute power to the body
bias domain.
Rail Analysis - the -process_bulk_pins_for_body_bias parameter has been
added to the set_rail_analysis_mode command. When set to true, rail analysis
will process current sinks on the cell's bulk pin connections. This parameter is used during
body bias analysis, where a body bias net is connected to bulk pins of the cell.
The bulk pins for a cell is defined in the cell library using the
set_power_library_mode -generic_bulk_power_names -
generic_bulk_ground_names command parameter. If bulk pins are
defined using set_power_library_mode -generic_power_names
-generic_ground_names, then the -
process_bulk_pins_for_body_bias parameter must not be used.
For more information, refer to the "Body Bias Analysis" chapter in the Encounter Power
System User Guide.
On-Chip Voltage Regulator Analysis Supported

EDI System now supports analysis of on-chip voltage regulators (Vreg) in System-on-a-chip
(SoC) to stabilize voltage supplies and to handle Dynamic Voltage and Frequency Scaling (DVFS).
This analysis has been included in the IR Drop analysis flow to understand how Vreg affects the
on-chip voltage drop, chip package co-design, and how it interacts with the IC/package/board
system. This feature allows you to accurately model Vreg modules for rail analysis.
During Vreg analysis, the tool captures the noise at the output of Vreg caused due to loading
current and RC effects, and uses this voltage waveform for rail analysis. In the following diagram,
the chip configuration has a Vreg that is connected to an input and output domain along with a
common ground. When you perform Vreg analysis, a reduced grid is created for both input and
output, and reduced ground resulting in a much concise RC netlist to do simulations of vectors
with these loadings. The noise at the output of Vreg is captured and used for rail analysis.
To analyze voltage regulator effects, the set_voltage_regulator_module command has

been introduced. For more information, refer to the "Dynamic Rail Analysis for On-Chip Voltage
Regulators "section in the Dynamic Power and IRDrop Analysis chapter of the Encounter Power
System User Guide.

Rail Analysis
Support for Region-Based Snapping

In this release, region-based auto fetch has been enhanced to support snapping. For region-
based auto fetch, if the voltage source points that were fetched according to the start point and the
specified region pitch (xPitch/yPitch) are not on the stripe, these points will be ignored during
analysis. Therefore, you can now use the -snap_distance parameter of the
create_power_pads command to snap the voltage sources to a stripe within +/- snap
distance/2. If no such stripe is found, this point will not be saved into the pad location file. As a
result, the voltage sources are generated only on the stripes and these points will be saved to the
pad location file.
Edit Pad Location Form Enhanced

The Edit Pad Location form has been enhanced by rearranging the form layout to improve
usability.

Rail Analysis
In addition, the following changes have been made:

Removed the RLC Update section
Removed the Fetch All Layer Shapes and Snap Constraint options
Added the TSV and Append to Existing File options
view_esd_violation Enhanced to View Bumps Within a Resistor

Rail Analysis
Range
Previously, the view_esd_violation command reported only those bumps with effective
resistance greater than the specified threshold value. Now, you can use the new -limit
parameter to report bumps that have a resistor value in the specified range, that is, between
value1 and value2. The -limit parameter must be used in conjunction with the -threshold
parameter. The -threshold parameter specifies value1 or the lower limit of the resistance
value, and the -limit parameter specifies value2 or the upper limit of the resistance value.
Resistance values must be specified in Ohm.
Ability to Control Layer Processing

In this release, the -process_layer_off parameter has been added to the
view_analysis_results command to select the user-defined layers to be used for
processing during the next analysis. This parameter allows you to turn on/off certain layers so that
you can view specific layer-based IRdrop plots with data distribution.
view_analysis_results -process_layer_off {all | none | layer1

layer2..layerN}
GUI Enhancement
The Process column has been added to the Power & Rail Results - Advanced form to control the
processing of individual layers interactively.
Rail Analysis Reporting Improved

In this release, Rail Analysis has been improved to generate a single consolidated report
containing all power-grid integrity data. This report lists all power-grid integrity related problems,
such as instances without voltage-source connectivity in PGDB, disconnected PGVs in PGDB,
missing cells, physically disconnected cells, and so on.
Previously, the following reports were generated by Rail Analysis for each net inside the state
directory (../state_dir/Reports):
net_name.disconnected_inst.asc
net_name .disconnected_pgv.asc
net_name .missing_pgv.asc
net_name .pwr_annotation.asc
net_name .reff_infiniti.asc
net_name .unconnected_sections.asc

Rail Analysis
With the current implementation, these fragmented reports have been consolidated to generate
the net_name.pg_integrity.asc and .html files for each net in the state directory
(../state_dir/<net>/Reports). The consolidated report will now also have information on
weakly connected power segments, for example, stripes not connected to top level layer.
Support for Non Zero Capacitance Filler Cells for Decap

Optimization Flow
The set_rail_analysis_mode -filler_cell_list command parameter now supports
non-zero capacitance filler cells during feasibility or timing aware decap optimization. Previously,
this parameter would only honor the filler cells with zero capacitance.
Sub_Via Support Added

In this release, the software has been enhanced to apply the EM rules defined for a via object to
its sub_via objects. For example, via odtap has 2 sub_vias, odtap_n and odtap_p . The EM
model defined for odtap will be automatically applied to all the resistors belonging to odtap_n
and odtap_p .
Change in Extraction Results for Designs with Dangling

Resistors
In this release, the extractor embedded in Encounter Power System will remove dangling resistors
on power-grid during extraction. These dangling resistors do not contribute towards any accuracy
loss during rail analysis. The dangling resistors occur on shapes with open current path. However,
it preserves dangling resistors for EM analysis if the process EM rules depends on current
direction and the longest path length.

From release 12.0 onwards, rail analysis considers the connectivity of the block-level power nets
to the top-level DEF, if the connectivity is defined by the wildcard character (*). Previously, wildcard
pin connectivity definition was not supported.
Via Clustering Enhanced

Rail Analysis has been enhanced to support clustering of VIA1 ports placed on follow-pin routing.
Designs with follow-pin routing on M1 and M2 layers have standard cells library LEF with M1, M2,
and VIA1 ports. You can now specify the set_rail_analysis_mode –
cluster_via1_ports true parameter to cluster VIA1 ports for such cells in order to improve
overall extraction and rail analysis performance.

Rail Analysis
In addition, the following parameter has been introduced to support layer-based custom via
clustering:
set_rail_analysis_mode –cluster_via_rule { {via_layer
number_of_equidistant_vias}… } - Controls the number of vias to cluster on a
layer basis. The VIA clustering rule specified using this parameter will override the default
clustering rule for a given accuracy mode.
The following command will cluster 100 equidistant VIA1 cuts, 200 equidistant VIA2 cuts, and 300
equidistant VIA7 cuts:
set_rail_analysis_mode –cluster_via_rule { {VIA1 100}} {VIA2
200} {VIA7 300}}
The rest of the VIAs will be clustered using the default clustering rule depending upon the rail
analysis accuracy mode.
New Parameters to Ignore Filler and Decap Cells

In this release, the following parameters have been added to the set_rail_analysis_mode
command to ignore filler and decap cells:
–ignore_fillers {true | false} - Ignores filler cells during power-grid view
library generation or specified as fillers using the set_rail_analysis_mode –
filler_cell_list command parameter. During dynamic analysis, ignore library cells
that are tagged as FILLER cells and have no capacitance associated with the interface
nodes.
Default: false
Note: Due to follow-pin routing in DEF, connectivity will not be impacted by ignoring these
cells. If a design has M1-M2 follow-pin routing, filler cells may provide additional parallel
paths for current and ignoring them may cause slight change in IRdrop results, but at a
much higher cost of performance.
–ignore_decaps {true | false} - Ignores decap cells during static analysis. It ignores
cells that are tagged as DECAP cells during library characterization or set as decap cells
using the set_rail_analysis_mode –decap_cell_list command parameter.
Ignoring decaps during dynamic analysis is not recommended.
Default: false

Early Rail Analysis
24
Early Rail Analysis
New Parameter to Support Fast Mode Extraction
Power Gate Analysis Behavior Enhanced

New Parameter to Support Fast Mode Extraction
In this release, the -turbo parameter has been added to the analyze_early_rail
command to enable fast mode ERA extraction. This parameter improves extraction performance
by reducing turnaround time and memory footprint. This can result in extraction performance gains
of up to 2X, compared to the 11 release.
Note: The -turbo parameter requires the EPS-L license.
Power Gate Analysis Behavior Enhanced

In the power gate file based flow, the following enhancements were made to the power gate
analysis behavior:
The methodology to add Ron resistor to a power gate cell has been improved to minimize
the behavior difference between the power gate file flow and the power-grid view flow.
The methodology to add leakage current to a power gate cell has been modified. When
power switch instances have the ON status, the leakage current in the power gate file is
not added for rail analysis. While in the OFF status, leakage current in the power gate file is
added. Earlier, leakage current was added for rail analysis even if power switch instances
have the ON status.
A new parameter -off_rails has been added to the analyze_early_rail
command to specify a list of switched nets in the OFF state that are to be excluded from rail
analysis. Previously, it was assumed that power switch instances always have the ON
status.
Generates a report file including the Ron/Idsat/Ileakage information of power switch
instances:
CELL ATERM STERM RON(Ohm) IDSAT(A) ILEAK(A)
HDRSID0 TVDD VDD 12.1046 0.0368639 1.28907e-08

Early Rail Analysis

Mixed Signal Interoperability
25
run_vsr GUI Updated
setIntegRouteConstraint Command Enhanced
Integration Constraints Editor GUI Updated
Floating Shields Supported

run_vsr GUI Updated
In this release, the run_vsr GUI (Tools Menu) supports bus constraints.
setIntegRouteConstraint Command Enhanced

In this release, setIntegRouteConstraint constraint command contains:
the new bus constraint type.
the updated syntax for layerGap, shieldWidth, shieldGap, tandemWidth and
groupToOutsideSpacing
Following is the updated syntax of this command:

setIntegRouteConstraint
[-help]
-type {diffPair | matchLength | routeNet | bus}

-net {Net1 Net2}
-rule <non-default-rule-name>
[-shieldNet name |
-groupToOutsideSpacing {layer1Spacing layer2Spacing ...}]
[-layerGap {layer1 gap1 layer2[:layerN] gap2...}]
[-shieldGap {layer1 gap1 layer2[:layerN] gap2 ...}]
[-shieldWidth {layer1 width1 layer2[:layerN] width2...}]
[-tandemWidth {layer1 width1 layer2[:layerN] width2...}]

[-shieldType shieldType]
[-tandemWidth {layer1width layer2width ...}]
[-hierarchicalScope {local local_above local_below local_above_below}]
[-tolerance tolerance]
[-matchStyle style]
[-topLayer layerNumber]
[-bottomLayer layerNumber]
[-connectSupply value}]

[-layerMatch layerMatch]
Integration Constraints Editor GUI Updated

In this release, the Integration Constraints Editor has been updated to support bus constraints
using the new BUS tab.
Using the new Pull Block Constraint tab, you can pull the routing constraints stored on the
interface nets of blocks in a design, to their corresponding top-level nets.
Floating Shields Supported

In this release, the Integration Constraints Editor has been enhanced to support floating shields.
The Connect Supply option now can support float as one of the value in addition to the default
value anyPoint.

Clock Concurrent Optimization
26
Clock Concurrent Optimization
setCCOptMode Command Enhanced to Set the Minimum Fanout Number for Top
Nets

setCCOptMode Command Enhanced to Set the Minimum Fanout
Number for Top Nets
The -top_net_min_fanout parameter of the setCCOptMode command is used to set the
minimum number of transitive fanouts in the clock tree for a net to be considered a "top" net.
All nets in a clock tree can be classified as "leaf" nets, "trunk" nets, or "top" nets. Leaf nets connect
directly to sinks. Top nets are nets that have a transitive fanout higher than the configured
threshold, and trunk nets are those nets that are not directly connected to sinks. Depending on the
total number of fanouts in a tree, you may not have any top nets at all – just leaf and trunk nets.
Top nets, trunk nets, and leaf nets can all use different routing rules. So if a net is determined to be
a top net because its transitive fanout is greater than the threshold set by the
top_net_min_fanout parameter then it will use the top net routing rules. If it is leaf net or a
trunk net then it will use leaf routing rules or trunk routing rules.
Changing the value of this parameter will change the nets that are considered as top nets.
The default value of this parameter is 0.

Clock Tree Synthesis
27
AssumeShielding Option in the Clock Specification File is Obsolete
clockDesign Parameters not Supported with CCOpt Engine
reportClockTree Command Enhanced to Write Out Information for Cell Types

AssumeShielding Option in the Clock Specification File is
Obsolete
The AssumeShielding option in the section of the clock tree specification file, which deals with
attributes that clock tree synthesis (CTS) passes to NanoRoute Ultra, is now obsolete. This option
was used to instruct CTS to assume that unshielded wires were shielded when CTS estimated
wire loading. The default value of this option was NO.
However, this option is no longer needed because of the following reasons:

1. The users can estimate the shielding effect during the preRoute stage by specifying
"Shielding YES" in the specification file.
2. Specifying both options - "AssumeShielding YES" and "Shielding NO" (default) -
in the spec file can lead to a conflict.
If specified, this option will be ignored by the software.
clockDesign Parameters not Supported with CCOpt Engine

The setCTSMode -engine {ck | ccopt} command is used to specify whether
clockDesign will use the EDI-CTS commands (ckSynthesis / ckECO ) or the CCOpt
engine to perform CTS.
When setCTSMode -engine is set to -ccopt, the EDI clock specification file is automatically
mapped to the Azuro clock specification. However, when you use the CCOpt engine, many
parameters of the clockDesign command are not supported. These parameters are only
supported when the engine specified is ck. You can use other EDI commands and options
instead.
For details of commands and parameters that can be used instead of the clockDesign
parameters that are not supported with the CCOpt engine, refer to the clockDesign command

in the EDI System Text Command Reference document.
reportClockTree Command Enhanced to Write Out Information

for Cell Types
The reportClockTree command is enhanced to write out information about the cell type,
instance count, and area both for leaf components (such as flip flops and latches) and non-leaf
components (such as buffers, inverters, and clock gates) for all clocks specified in the specification
file.Use the -area parameter of this command to write out this information.

OpenAccess
28
OpenAccess
New Command to Access the 5.x Library Structure
New Parameter to Add Voltage Information to the Nets

New Command to Access the 5.x Library Structure
In earlier releases, there was no way for the user to find out where on disk OpenAccess data is
stored. In this release, you can use the new dd_get command to access the 5.x library structure.
This command has the following syntax:

dd_get
{-all_lib} |{–dd dd_objHandle | -lib libName | -cell {lib cell} | -cellview {lib cell view} }
[-children | -file | -path | -type |-name]}
New Parameter to Add Voltage Information to the Nets

In this release, you can use the new setOaxMode -saveNetVoltage {true | false} parameter to
save the maximum net voltage across all loaded timing views to every net. This is useful for
Virtuoso to understand the maximum net voltage without looking at a CPF, or .lib files.

TSV
29
TSV
Embedded Bump Flow Supported in Hierarchical Designs
New Parameter Added to Output Selected Bumps

Embedded Bump Flow Supported in Hierarchical Designs
EDI System has been enhanced to support embedded bumps in the hierarchical flow for 3D IC
designs. At the block level, all the bumps in the LEF file were previously output as PIN which is
same as normal pins. Therefore, it was difficult to distinguish bumps from normal pins. With the
current implementation, the tool can identify the PIN as a normal bump, which is defined as an
embedded bump in the top-level.
The block-level LEF file with the embedded bump information is passed to the top-level design,
and the embedded bumps are treated as normal bumps in the top-level design. The embedded
bump information can also be exchanged between adjacent dies. As a result, a chip of the current
design could create and assign bumps according to embedded bumps in the adjacent die.
All the 3D IC commands have been enhanced to support embedded bumps, therefore, the output
files generated by these commands for the downstream tools also support embedded bumps.
New Parameter Added to Output Selected Bumps

In this release, the -selected parameter has been added to the writeBumpLocation
command to output information related to selected bumps to the bump file. With the current
implementation, you can select the required bumps in the GUI, and specify the
writeBumpLocation -selected command to output the bump information. You can use
this parameter when you want to output bump information that is related to a specific block in
hierarchical designs.

Timing Optimization
30
Timing Optimization
New Command Introduced
timeDesign Command Updated
reclaimArea Command Updated
setOptMode Command Updated
New Parameters Added
GigaOpt as the Default Optimization Engine
Obsolete Parameters

New Command Introduced
In this release, you can use the reportLengthViolation command to run timing analysis and report
nets that exceed the maximum length constraint set by the setOptMode –maxLength parameter.
timeDesign Command Updated

In this release, the timeDesign -signOff command uses AAE as the default engine.
reclaimArea Command Updated

In this release, you can use the new reclaimArea -maintainHold parameter to run the hold-aware
area reclaim while running with AAE engine.
setOptMode Command Updated

New Parameters Added
In this release, the following new parameters have been added to the setOptMode command:

Timing Optimization
-timeDesignNumPaths number
Allows you to select the number of paths that should be reported per path group during
timeDesign or optDesign final summary reports.
Default : 50
-timeDesignExpandedView {true | false}
When set to true, it will force timeDesign or optDesign to print summary timing reports
as per the view in the log file.
Default : false
-timeDesignReportNet {true | false}
When set to true, this will force timeDesign or optDesign to print timing reports with the
net section.
Default : false
-postRouteAreaReclaim {none | setupAware | holdAndSetupAware}

This parameter can be used after routing to reclaim area during optDesign -postRoute. It
safely reclaims area while not impacting the timing and DRV violations.
GigaOpt as the Default Optimization Engine

In this release, GigaOpt is the new default optimization engine for post-route optimization. This
new engine is multi-threaded, scalable and deterministic so it is recommended to use
setMultiCpuUsage where possible to reduce TAT.
Using this engine, you need not run optDesign –si but rest of the use model is unchanged. The
reason for this is that GigaOpt post-route optimization will by default fix both the base timing and SI
timing at the same time.
Obsolete Parameters
In this release, the following parameters of setOptMode command are obsolete.
-congOpt {true | false}
-considerNonActivePathGroup {true | false}
-critPathCellYield {true | false}
-postRouteAllowOverlap {true | false}
-yieldEffort {none | low | high}

Placement
31
Placement
Release 12 Enhancements
New Commands
New Options for setPlaceMode
New Option for addFillerGap
Release 12 Enhancements
New Commands
The new commands added to EDI System are:
place_connected: Places the specified standard cells close to the specified attractor with
legal location. The attractor can be IOs or hard macros. The recommended flow is to run
this command before placeDesign.
get_well_tap_mode: Returns the information about set_well_tap_mode parameters in the

EDI System log file and in the EDI System console.
set_well_tap_mode: Controls the behavior of addWellTap command. The mode setting is

persistent and saved along with the database by the saveDesign command.
New Options for setPlaceMode

The command setPlaceMode has a new option -fillerGapRadius that specifies the
searching radius when solving the minimum filler gap.
The command setprerouteAsObs has been replaced with the option -prerouteAsObs.
The option's function remains the same, it returns the routing layers.
A new option congRepairEffort is added which controls the effort level of

congRepair iterations. The high effort mode is recommended for highly congested designs
because itruns additional congRepair iterations at cost of extra runtime. The same option has also
been added to getPlaceMode.
New Option for addFillerGap

The command addFillerGap has a new option -radius which specifies the searching radius

Placement
when solving the minimum filler gap.

Yield Analysis
32
Yield Analysis
Yield Analysis Discontinued

Yield Analysis Discontinued
Yield analysis is being discontinued from this release. The following yield analysis commands and
standalone executables are now obsolete:
loadYieldTechFile
reportYield
tsmc2yld
umc2yld
The associated GUI forms and documentation have also been discontinued from this release.

Delay Calculation
33
Delay Calculation
Vectorized Delay Calculation Support in MMMC with AAE

Vectorized Delay Calculation Support in MMMC with AAE
In this release, the EDI System 12 is enhanced to support vectorized delay calculation when the
software is in the MMMC mode and the delay calculation engine used is the Advanced Analysis
Engine (AAE). With this enhancement the user can specify options for combining delay calculation
runs for early and late simulations into a single simulation. The enhancement provides the user
control for improving the runtime of AAE for all analysis types. Use the combine_mmmc {none
| early_late} parameter of the setDelayCalMode command to specify the combination of
your choice for the delay calculation runs.
When none is specified, the software does not combine any delay calculation runs. When
early_late is selected, the software combines early and late simulations of a single corner into
one delay calculation simulation.

Netlist-to-Netlist
34
Netlist-to-Netlist
runN2NOpt -optimizeYield Parameter Now Obsolete

runN2NOpt -optimizeYield Parameter Now Obsolete
The -optimizeYield parameter of runN2NOpt is now obsolete as EDI does not support the
Yield Analysis feature any longer.

Prototyping Foundation Flow
35
New Command to Control Initial Floorplan
New Command to Generate Floorplan for Prototyping
set_proto_mode Command Updated
set_proto_model Command Updated
load_timing_debug_report Command Updated

New Command to Control Initial Floorplan
In this release, you can use the new set_proto_design_mode command to control certain aspects
of how the proto_design command generates an initial floorplan.
New Command to Generate Floorplan for Prototyping

In this release, you can use the new proto_design command to generate an initial floorplan for
prototyping that can be used as a start point for making the final floorplan. This command internally
calls planDesign to place flexModels, power domains, and/or user-specified module seeds.
It is a super command and internally calls planDesign, placeDesign, and timeDesign -proto
commands.
set_proto_mode Command Updated

In this release, the following new parameters have been added to the set_proto_mode command:
Specifies an estimate of the average percentage of routing tracks which would be used by
the standard cells represented by flexFillers.
-create_characterize_percent_rt_blockage
Specifies the percentage of models being generated that will be used for characterizing the

default percentage of routing tracks that will be used by the standard cells represented by
flexFiller cells.
-identify_partition_min_inst and -identify_partition_max_inst
Specifies the minimum and maximum instance count per partition that will be used by
identify_flexmodel to identify flexModels.
set_proto_model Command Updated

In this release, the following new parameter have been added to the set_proto_model command:
Specifies an estimate of the percentage of routing tracks which would be used by the
standard cells represented by flexFillers of a specific flexModel.
-create_gate_area
Specifies total area of standard cell gates. This value does not include macro area.
-create_gate_count
Specifies number of gates per area. This value will be multiplied with the value of -
create_gate_area to come up the total area of standard cells for a specific module.
load_timing_debug_report Command Updated

In this release, the new load_timing_debug_report -proto [-additional_slack_past_wns number] [-
num_path number] parameter creates flex model categories and displays the top path of the top
eight (by default) categories. This option can be used for design that has flexModels. Use –
additional_slack_past_wns to report all paths with slack worst than (WNS and additional specified
slack value). Use –num_path to control the number of violation paths.

Signal Integrity Analysis
36
setSIMode Command Enhanced
In this release, following new parameters have been added to the setSIMode command:
-accumulated_small_attacker_mode {cap | current}
-accumulated_small_attacker_threshold value
-individual_attacker_threshold <value>
-separate_delta_delay_on_data {true | false}
-delta_delay_annotation_mode {lumpedOnNet | arc}
-switch_prob value

-receiver_peak_limit value
-input_glitch_thresh value

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December 2012 3 Product Version 12.0

New Pin Shapes Option in Layer Control Bar 34

December 2012 4 Product Version 12.0

Flip Chip Flightline Enhancements 50

December 2012 5 Product Version 12.0

Support for Virtual fence Option to Handle User-specified Seeds 69

December 2012 6 Product Version 12.0

December 2012 7 Product Version 12.0

Multi-Threading Support for Dynamic Vector-Based Power Analysis Flow 97

December 2012 8 Product Version 12.0

December 2012 9 Product Version 12.0

New Command to Control Initial Floorplan 127

December 2012 10 Product Version 12.0

How This Document Is Organized

EDI System Product Documentation

December 2012 11 Product Version 12.0

EDI System Known Problems and Solutions

EDI System User Guide

EDI System Text Command Reference

EDI System Menu Reference

EDI System Database Access Command Reference

EDI System Foundation Flows User Guide

Mixed Signal Interoperability Guide

December 2012 12 Product Version 12.0

Release 12.0 Overview

New Commands and Globals Chapter

create_power_pads Rail Analysis

December 2012 13 Product Version 12.0

set_voltage_regulator_module Rail Analysis

December 2012 14 Product Version 12.0

New Command Parameters

New Parameters Chapter

add_ndr Floorplan Commands and Global

addFillerGap Placement Commands and Global

December 2012 15 Product Version 12.0

assignBump Flip Chip Commands and Global

do_extract_model Timing Modeling Commands

December 2012 16 Product Version 12.0

optPowerSwitch Low Power Commands

getPlanDesignMode Floorplan Commands and Global

reportClockTree Clock Tree Synthesis Commands

reportPowerDomain Low Power Commands

report_power Power Calculation Commands

December 2012 17 Product Version 12.0

setEdit Wire Edit Commands

setPinConstraint Partition Commands and Global

setPlaceMode Placement Commands and Global

December 2012 18 Product Version 12.0

setPlanDesignMode Floorplan Commands and Global

set_proto_model Prototyping Foundation Flow

set_rail_analysis_mode Rail Analysis Commands

December 2012 19 Product Version 12.0

setSpecialRouteOption Wire Edit Commands

set_timing_derate Timing Analysis Commands

December 2012 20 Product Version 12.0

setCCOptMode Clock Concurrent Optimization

viewBumpConnection Flip Chip Commands and Global

view_analysis_results Rail Analysis Commands

Obsolete Text Commands and Global Variables

Supported in this Release