COMP2611: Computer Organization

The Processor:
Datapath & Control

COMP2611 CSE HKUST

Major Goals 2

 Present the design of MIPS processor

 A simplified version: single-cycle implementation
 A more realistic pipelined version: pipelined single-cycle
implementation

 Illustrate the datapath & control in processor

 Focus on implementing of a subset of the core MIPS instruction set

 Memory-reference instructions: lw, sw
 Arithmetic-logical instructions: add, sub, and, or, slt
 Branch and jump instructions: beq, j

COMP2611 CSE HKUST The Processor: Datapath & Control

 3

1. Building a Single-cycle Datapath

COMP2611 CSE HKUST The Processor: Datapath & Control

Big Picture 4

 First, understand how an instruction is executed before the design

 Then, split the execution of an instruction into multiple steps common

to all instructions

 Next, implement each part separately

 Finally, put all these parts back together

COMP2611 CSE HKUST The Processor: Datapath & Control

How is an Instruction Executed? 5

1. Fetch the instruction from memory location indicated by program

counter (PC)

2. Decode the instruction – to find out what to perform

Meanwhile, read source registers specified in the instruction fields
 lw instruction require reading only one register
 most other instructions require reading two registers

3. Perform the operation required by the instruction using the ALU

 Arithmetic & logical instructions: execute
 Memory-reference instructions: use ALU for address calculation
 Conditional branch instructions: use ALU for comparison

4. Memory access: lw and sw instructions

5. Write back the result to the destination register

Increment PC by 4 or change PC to branch target address to find
next instruction to be executed
COMP2611 CSE HKUST The Processor: Datapath & Control
MIPS Processor Overview 6

add

add n
4
Data

Reg. #
PC

Addr. Instr. Addr.

Reg. #
Data
Instruction Reg. #
ALU Data
Memory
j Registers
l
Memory

k m

COMP2611 CSE HKUST The Processor: Datapath & Control

Anatomy of a Computer: Inside the Processor 7

 AMD Barcelona: 4 processor cores

COMP2611 CSE HKUST The Processor: Datapath & Control

Building a Datapath 8

 Datapath
 Elements that process data and addresses in the CPU
• Registers, ALUs, multiplexors, memories, …
 We will build a MIPS datapath incrementally
 Refining the overview design

COMP2611 CSE HKUST The Processor: Datapath & Control

Basic Building Blocks 9

 Instruction memory:
 A memory unit that stores the instructions of a program
 Supplies an instruction given its address
 Program counter:
 A register storing the address of the instruction being executed
 Adder:
 A unit that increments PC to form the address of next instruction

Instruction
address

PC
Instruction Add Sum
Instruction
memory

a. Instruction memory b. Program counter c. Adder

COMP2611 CSE HKUST The Processor: Datapath & Control

Instruction Fetch 10

1. Fetch the current instruction from memory using PC

2. Prepare for the next instruction
 By incrementing PC by 4 to point to next instruction (base case)
 Will worry about the branches later

Add

Read
PC
address Increment by
4 for next
Instruction
32-bit instruction
Instruction
register memory

COMP2611 CSE HKUST The Processor: Datapath & Control

Operations for Different Types of Instructions 11

 R-format arithmetic/logic instructions

 Read two register operands
 ALU performs arithmetic/logical operation
 Write register result
 I-format load/store instructions
 Read base register operand
 ALU adds base address with 16-bit sign-extend offset
 Load: Read memory and update register
 Store: Write register value to memory
 I-format branch instructions
 Read register operands
 ALU compares operands by subtracting and checking Zero output
 Use ALU, subtract and check Zero output
 Calculate branch target address with PC-relative addressing

COMP2611 CSE HKUST The Processor: Datapath & Control

 Datapath for Arithmetic/Logical (R-Type) Instr. 12

 E.g.: add $t0, $s1, $s2

Register Value
0 17 18 8 0 32 s1 100
000000 10001 10010 01000 00000 100000 s2 200
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

k l
ALU
instr[25-21] 17 Read operation
Add 3
register 1 100
4 Read
instr[20-16] 18 data 1
PC Read Read
address
register 2 Zero
Register
Instruction
File ALU 300
Instruction
memory
instr. 8 Write result
register 200
instr[15-11] Read
data 2
Write
data

j n RegWrite

COMP2611 CSE HKUST The Processor: Datapath & Control

 Datapath for Load/Store (I-Format) Instr. 13

Register Value
 E.g.: lw $t0, 1000($s1)
t0 200
35 17 (s1) 8 (t0) 1000 (immediate) s1 100
100011 10001 01000 0000 0011 1110 1000 Memory[1100]
6 bits 5 bits 5 bits 16 bits 50

instr[25-21] 17 3 ALU operation 0

Read

instr[20-16]
register 1
Read 100 m MemWrite
8 Read
data 1
Instruction register 2 Zero
ALU ALU
8 Write
Registers
Read 50
instr[20-16] result Address
register 1100 data
Read
Write data 2
Data
data
k RegWrite
200
(not used)
Write
data
memory

16 32
1000 Sign MemRead
instr[15-0]
(Offset) extend l
n
Note: For load word instruction, MemWrite has to be de-asserted so that the memory will not be modified by
incoming write data.
COMP2611 CSE HKUST The Processor: Datapath & Control
Datapath for Branch (I-Format) Instr. 14

 E.g.: beq $t0, $t1, 2

1000: beq $t0, $t1, L1

1004: . 2 instructions PC+4 from 1004
1008: . are skipped Instruction datapath
1012: L1: add $t0, $t1, $t2 Add Sum Branch target

2 Shift 8 1012
Register Value left 2
t0 200
instr[25-21] ALU operation
8 Read 3
t1 200
Instruction register 1
Read 200
PC 1000 9 Read
data 1
instr[20-16] register 2
Register ALU Zero To branch
Write File control logic
register
Read 200
data 2
Write
data
RegWrite

2 16
Sign
32
instr[15-0]
extend

COMP2611 CSE HKUST The Processor: Datapath & Control

A Simple Single-Cycle Implementation 15

 We have already built a datapath for each instruction separately

 Now, we need to combine them into a single datapath

 Key to combine

Share some of the resources (e.g., ALU)

among different instructions

Note:
 This simple implementation is based on the (unrealistic) assumption
 i.e. all instructions take just one clock cycle each to complete
 Implication:
 No datapath resource can be used more than once per instruction
 Any element needed more than once must be duplicated
 Instructions and data have to be stored in separate memories
 Use multiplexers where alternate data sources are used for
different instructions
COMP2611 CSE HKUST The Processor: Datapath & Control
R-Type/Load/Store Datapath 16

 Use ALUSrc to decide which source will be sent to the ALU

 Use MemtoReg to choose the source of output back to dest. register

Add

4 k l m
R eg isters
Read ALU operatio n
register 1 3 MemW rite
PC Re ad
Read
address Read MemtoReg
register 2 data 1
ALUSrc Zero
Instruction
W rite Read AL U A LU R ea d
Address
register data 2 result data
M M
Instruction u u
W rite x Data
m emory x
data mem ory
W rite
RegW rite data
j 16 Sig n 32 Mem R ead
extend

n
COMP2611 CSE HKUST The Processor: Datapath & Control
Combined Datapath for Different Instr. Classes 17

PCSrc

M
Add u
x
4 Add A LU
result
Shift
left 2

Select the next PC:

k l 
Either PC+4 or branch
Read
R eg isters target
ALU operatio n address
register 1 3 MemW rite
PC Read
Read
address Read MemtoReg
register 2 data 1 ALUSrc Zero
Instruction
W rite Read AL U A LU R ead
Address
register data 2 result data
M M
Instructio n u u
W rite x Data
m emory x
data mem ory
W rite
RegW rite data
j 16 Sig n 32 Mem R ead
e xtend

n
COMP2611 CSE HKUST The Processor: Datapath & Control
 Full Datapath: Muxing Two Possible Destination Registers 18

PCSrc

M
Add u
x
4 Add A LU
result
Shift
left 2

R eg isters
Read ALU operatio n
register 1 3 MemW rite
PC Read
Read
address Read MemtoReg
register 2 data 1 ALUSrc Zero
Instruction
M W rite Read AL U A LU R ead
Address
u register data 2 result data
x M M
Instructio n u u
W rite x Data
m emory x
data mem ory
W rite
RegW rite data

16 Sig n 32
Destination register: e xtend
Mem R ead

For R-format: it is rd field (bits 15-11)

For lw: it is rt field (bits 20-16)

COMP2611 CSE HKUST The Processor: Datapath & Control

 19

2. Single-cycle Control

COMP2611 CSE HKUST The Processor: Datapath & Control

Overview: Datapath with Control 20

0
M
u
x
ALU
Add 1
result
Add
Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21] Read

Read register 1
PC Read
address
Instruction [20 16] data 1
Read
register 2 Zero
Instruction
0 Registers Read ALU ALU
[31– 0] 0 Read
M W rite data 2 result Address 1
Instruction u register M data
u M
memory x u
Instruction [15 11] W rite x
1 Data x
data 1 memory 0
Write
data
16 32
Instruction [15 0] Sign
extend ALU
control

Instruction [5 0]

Topic we are going to discuss next

COMP2611 CSE HKUST The Processor: Datapath & Control

Control Unit 21

 Control unit controls the whole operation of the datapath

through control signals, e.g.

 read/write signals for state elements: RegWrite,

MemWrite, MemRead
 selector inputs for multiplexors: ALUSrc, MemtoReg,
PCSrc, RegDst
 ALU control inputs (4 bits) for different ALU operations

COMP2611 CSE HKUST The Processor: Datapath & Control

First: ALU Control Unit 22

 ALU is used for

 Load/Store: F = add
 Branch: F = subtract
 R-type: F depends on funct field

ALU Control Input Function

0000 and
0001 or
0010 add
0110 subtract
0111 set on less than
1100 NOR

COMP2611 CSE HKUST The Processor: Datapath & Control

Generation of ALU Control Input Bits 23

0
M
u
x
ALU
Add 1
result
Add
Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21] Read

Read register 1
PC Read
address
Instruction [20 16] data 1
Read
register 2 Zero
Instruction
0 Registers Read ALU ALU
[31– 0] 0 Read
M W rite data 2 result Address 1
Instruction u register M data
u M
memory x u
Instruction [15 11] W rite x
1 Data x
data 1 memory 0
Write
data
16 32
Instruction [15 0] Sign
extend ALU
control
Instruction [5 0]
4-bit ALU
6-bit Control
function 2-bit
code ALUOp

COMP2611 CSE HKUST The Processor: Datapath & Control

Generation of ALU Control Input Bits (cont.) 24

 Two common implementation techniques:

 1-level decoding
― more input bits
 2-level decoding
 less input bits, less complicated => potentially faster logic

k j
Opcode ALU Op Opcode
6 bit 2 bit 6 bit
ALU Control
Function 4 bit Function
code code
6 bit 6 bit

2 levels of decoding: only 8 inputs are 1 level only, a logic circuit with
used to generate 3 outputs in 2nd level 12 inputs is needed

COMP2611 CSE HKUST The Processor: Datapath & Control

Implementing ALU Control Block 25

 Assume 2-bit ALUOp derived from opcode

 Combinational logic derives ALU control

opcode ALUOp Operation funct ALU function ALU control

lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111
input input output

COMP2611 CSE HKUST The Processor: Datapath & Control

Implementing ALU Control Block (cont.) 26

 Start from truth table

 Smart design converts many entries in the table to don't-care terms,
leading to a simplified hardware implementation

ALUOp Function code

Operation
ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0
0 0 X X X X X X 0010 lw, sw
X 1 X X X X X X 0110 beq
1 X X X 0 0 0 0 0010
1 X X X 0 0 1 0 0110
R-type
1 X X X 0 1 0 0 0000 Instr.
1 X X X 0 1 0 1 0001
1 X X X 1 0 1 0 0111

 Why we can come up with some many don’t care?

COMP2611 CSE HKUST The Processor: Datapath & Control

Hardware Implementation of ALU Control Block 27

ALUOp
ALU control block
ALUOp0
ALUOp1

Operation2
F3
Operation
F2 Operation1
F (5– 0)
F1
Operation0
F0

COMP2611 CSE HKUST The Processor: Datapath & Control

Next: the Main Control Unit 28

 Different instructions desire different operations in datapath

 Proper control signals in datapath make this happen
 Control signals are derived from instruction

R-type 0 rs rt rd shamt funct

31:26 25:21 20:16 15:11 10:6 5:0

Load/ 35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for R- sign-extend

read except type and and add
for load load

COMP2611 CSE HKUST The Processor: Datapath & Control

Control Signals in Single-cycle Implementation 29

Signal name Effect when deasserted Effect when asserted

The register destination number for The register destination number for the
RegDst the Write register comes from rt field Write register comes from rd field (bits
(bits 20-16) 15-11)
Enable data write to the register
RegWrite None specified by the register destination
number
The second ALU operand comes from The second ALU operand is the sign-
ALUSrc the second register file output (Read extended, lower 16 bits of the
data port 2). instruction
The next PC picks up the output of The next PC picks up the output of the
PCSrc
the adder that computes PC+4 adder that computes the branch target
Enable read from memory. Memory
MemRead None contents designated by the address are
put on the Read data output
Enable write to memory. Overwrite the
memory contents designated by the
MemWrite None
address with the value on the Write
data input
Feed the Write data input of the Feed the Write data input of the
MemtoReg
register file with output from ALU register file with output from memory

COMP2611 CSE HKUST The Processor: Datapath & Control

Setting of Control Signals 30

 The 9 control signals (7 from previous table + 2 from ALUOp) can be

set based entirely on the 6-bit opcode, with the exception of PCSrc

 PCSrc control line is set if both conditions hold simultaneously:

a. Instruction is a branch, e.g. beq
b. Zero output of ALU is true (i.e., two source operands are equal)

COMP2611 CSE HKUST The Processor: Datapath & Control

R-Type Instr. with Control 31

0
M
u
x
ALU
Add 1
result
Add
RegDst
Shift
left 2
PCSrc 0
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control ALUOp
MemWrite


ALUSrc

1
RegWrite

0
Instruction [25 21] Read
Read register 1
PC Read

0
address
data 1
0
Instruction [20 16] Read
register 2 Zero
Instruction
0 Registers Read ALU ALU
[31– 0] 0 Read
M W rite data 2 result Address 1
Instruction u register M data
u M
memory x u
Instruction [15 11] W rite x
1 Data x
data 1 memory 0
Write

1
data

j Instruction [15 0]
16
Sign
32


extend

0
ALU

Instruction [5 0]
control

10

COMP2611 CSE HKUST The Processor: Datapath & Control

Load Instr. with Control 32

0
M
u
x
ALU
Add 1
result
Add
RegDst
Shift
left 2
PCSrc 0
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control ALUOp
MemWrite

 ALUSrc
RegWrite
1
0
Instruction [25 21] Read
Read register 1
PC Read

1
address


data 1
1
Instruction [20 16] Read
register 2 Zero
Instruction
0 Registers Read ALU ALU
[31– 0] 0 Read
M W rite data 2 result Address 1
Instruction u register M data
u M
memory x u
Instruction [15 11] W rite x
1 Data x
data 1 memory 0
Write

0 data

j Instruction [15 0]
16
Sign
extend
32

1
ALU

Instruction [5 0]
control

00

COMP2611 CSE HKUST The Processor: Datapath & Control

Branch-on-Equal Instr. with Control 33

0
M
u
x Checking
ALU
Add
result
1
condition
Add
RegDst
Shift
left 2
PCSrc 1 for PCSrc
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control ALUOp
MemWrite
ALUSrc

0
RegWrite

0
Instruction [25 21] Read
Read register 1
PC Read
address
data 1
0 X
Instruction [20 16] Read
register 2 Zero
Instruction
0 Registers Read ALU ALU
[31– 0] 0 Read
M W rite data 2 result Address 1
Instruction u register M data
u M
memory x u
Instruction [15 11] W rite x
1 Data x
data 1 memory 0
Write

X data

j Instruction [15 0]
16
Sign
extend
32

0
ALU

Instruction [5 0]
control

01

COMP2611 CSE HKUST The Processor: Datapath & Control

Setting of Control Signals (Cont’d) 34

 Setting of control lines (output of control unit):

Reg- ALU- Mem- Reg- Mem- Mem-
Instruction Branch ALUOp1 ALUOp0
Dst Src toReg Write Read Write
R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1
sw & beq will not modify any register, it is ensured by making RegWrite to 0
So, we don’t care what write register & write data are

 Input to control unit (i.e. opcode determines setting of control lines):

Opcode Opcode in binary
Instruction in
decimal Op5 Op4 Op3 Op2 Op1 Op0
R-format 0 0 0 0 0 0 0
lw 35 1 0 0 0 1 1
sw 43 1 0 1 0 1 1
beq 4 0 0 0 1 0 0

COMP2611 CSE HKUST The Processor: Datapath & Control

Implementing Datapath Control Unit 35

 Start with truth table

Input or output Signal name R-format lw sw beq
Op5 0 1 1 0
Op4 0 0 0 0
Op3 0 0 1 0
Inputs
Op2 0 0 0 1
Op1 0 1 1 0
Op0 0 1 1 0
RegDst 1 0 X X
ALUSrc 0 1 1 0
MemtoReg 0 1 X X
RegWrite 1 1 0 0
Outputs MemRead 0 1 0 0
MemWrite 0 0 1 0
Branch 0 0 0 1
ALUOp1 1 0 0 0
ALUOp0 0 0 0 1

COMP2611 CSE HKUST The Processor: Datapath & Control

Hardware Implementation of Datapath Control Unit 36
Inputs
Op5
Op4
Op3
Op2
Op1
Op0

Outputs
R-format Iw sw beq
RegDst

ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite

Branch
ALUOp1

ALUOpO

COMP2611 CSE HKUST The Processor: Datapath & Control

Implementing Jumps 37

Jump 2 address
31:26 25:0

 Jump uses word address

 Update PC with concatenation of
 Top 4 bits of old PC
 26-bit jump address
 00
 Need an extra control signal decoded from opcode

COMP2611 CSE HKUST The Processor: Datapath & Control

Extend Datapath & Control to Handle Jump Instr. 38

Instruction [25– 0] Shift

jump addr
[31-0]
left 2
26 28 0 1

PC+4 [31– 28] M M

u u
x x
ALU
Add 1 0
result
Add
Shift
Jmp
RegDst
left 2
4 Branch
MemRead
Instruction [31– 26]
Control MemtoReg
ALUOp
MemW rite
ALUSrc
RegWrite

Instruction [25– 21] Read

Read register 1
PC Read
address
Instruction [20– 16] data 1
Read
register 2 Zero
Instruction
0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction register M data
u M
memory x u
Instruction [15– 11] u
Write x
1 Data x
data 1 memory 0
Write
data

16 32
Instruction [15– 0] Sign
extend ALU
control

Instruction [5– 0]

COMP2611 CSE HKUST The Processor: Datapath & Control

Performance Issues 39

Single-cycle implementation can’t run very fast

 Longest delay determines clock period

 Critical path: load instruction
 Instruction memory  register file  ALU  data memory 
register file
 Not feasible to vary period for different instructions
 Violates design principle
 Making the common case fast
 We will improve performance by pipelining

COMP2611 CSE HKUST The Processor: Datapath & Control