A B C D E

1 1

2 Compal Confidential 2

Schematic Document
Crestline_GM/PM+NB8M-GS & ICH8M
2008 / 3 / 17 Rev:1.0
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Tuesday, March 18, 2008 Sheet 1 of 51
A B C D E

GRATIS - FOR FREE

hexainf@hotmail.com
 A B C D E

Compal Confidential
Project Code: ANRJAL3000 (JAL30)
JAL30 UMA/Discrete
File Name : LA-4121P
ZZZ1
Thermal Sensor Mobile Merom
1 1
ADM1032ARMZ CK505 TSSOP-64

PCB uFCPGA-478 CPU Clock Generator

P4
CRT & HDMI ICS 9LPRS365
P15 , P39 P4, 5, 6 P16

Fan conn P4 H_A#(3..35)

FSB
H_D#(0..63) 667/800MHz 1.05V
LVDS Panel Interface
P15

DDR2 667MHz 1.8V DDR2-SO-DIMM X2

nVidia Intel Crestline MCH BANK 0, 1, 2, 3 P13, 14

NB8M-GS
VRAM x 4 FCBGA 1299 Dual Channel
P37 , 38 P33 ~ 36
P7, 8, 9, 10, 11, 12
USB0
2 P30 2
USB conn x 1
CardBus Controller PCI DMI X4 C-Link
OZ129TN
P25
USB2.0

Express Card Intel ICH8M USB2,3

USB Conn x 2
P26 Azalia
PCIE2 On IO/B P30
Media Card 1394
PCI-E BUS mBGA-676 SATA0
PATA Slave
P17, 18, 19, 20
PCIE5 PCIE4 PCIE1

USB5
10/100/1000 LAN Mini Card-1 Mini Card-2 Express Card
P26
REALTEK (WLAN) (Robson)
RTL8111C-GR P27 P27 USB6

3
P22 Finger Printer 3
P30
Option
USB7
LPC BUS TPM1.2 BT
RJ45 CONN P28
P27
P22
USB8
Camera
P30

USB9
Felica Conn
ENE KB926C0 P30
P28
Audio CKT AMP & Audio Jack
ALC268 P23 P24
Touch Pad CONN. Int.KBD BIOS(System/EC)
Power On/Off CKT.
P29 P29 P28
P29 SATA HDD Connector
P21
4 4

DC/DC Interface CKT. RTC CKT. CDROM Conn.

P31 P18 P21

Security Classification Compal Secret Data Compal Electronics, Inc.

2007/1/15 2008/1/15 Title
Power Circuit DC/DC Power OK CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P40~47 P29 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 2 of 51
A B C D E
 A B C D E

O MEANS ON X MEANS OFF

Voltage Rails SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+5VS
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+3VS
Power +1.8VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
plane +1.5VS
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+1.25VS
+B +5VALW +1.8V CLOCK
1
+1.2VS S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+3VALW
State +0.9VS
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_CORE
+VGA_CORE
+VCCP
Board ID Table for AD channel
Vcc 3.3V +/- 5%
S0 O O O O O Ra / Rc 100K +/- 5%
Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
S3 O O O O 0 0 0 V 0 V 0 V
X
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
S5 S4/AC O O O 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
X X
3 33K +/- 5% 0.712 V 0.819 V 0.875 V
S5 S4/ Battery only O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
X X X X
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
S5 S4/AC & Battery 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
don't exist X X X X X
7 NC 2.500 V 3.300 V 3.300 V
2 2

BOARD ID Table BTO Option Table

O MEANS ON S3 : STR
X MEANS OFF
Board ID PCB Revision BTO Item BOM Structure
S4 : STD 0 0.1
S5 : SOFT OFF 1 0.2
External PCI Devices 2 0.3
Device IDSEL# REQ#/GNT# Interrupts
3
CardBus AD21 0 PIRQE/PIRQF/PIRQG
4
5
6
7

3 EC SM Bus1 address EC SM Bus2 address 3

Device Address Device Address

Smart Battery 0001 011X b? ADM1032 4D
EEPROM(24C16/02) 1010 000X b?
(24C04) 1011 000Xb?

ICH7 SM Bus address

Device Address

Clock Generator 1101 001Xb?

(ICS ICS9LPR310)
DDRII DIMM0 1001 000Xb?
DDRII DIMM2 1001 010Xb?

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 3 of 51
A B C D E

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

XDP Reserve
7 H_A#[3..16]
JP1A
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# 7 +VCCP

ADDR GROUP 0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# 7
H_A#6 K5
H_A#7 A[6]# H_DEFER# XDP_TDI R439 1 150_0402_1%
M3 H5 H_DEFER# 7 2
H_A#8 A[7]# DEFER# H_DRDY#
N2 F21 H_DRDY# 7
H_A#9 A[8]# DRDY# H_DBSY# XDP_TMS R443 1 39_0402_1%
J1 E1 H_DBSY# 7 2
H_A#10 A[9]# DBSY#
N3
H_A#11 A[10]# H_BR0# R78
P5 F1 H_BR0# 7
D H_A#12 A[11]# BR0# 56_0402_5% D
P2
A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# 2 1 XDP_BPM#5 R445 1 2 54.9_0402_1%
H_A#14 A[13]# IERR# H_INIT# +VCCP
P4 B3 H_INIT# 18 @
H_A#15 A[14]# INIT#
P1
H_A#16 A[15]# H_LOCK#
R1 H4 H_LOCK# 7
H_ADSTB#0 A[16]# LOCK#
7 H_ADSTB#0 M1
ADSTB[0]# H_RESET# XDP_TRST# R440 1 560_0402_5%
C1 H_RESET# 7 2
H_REQ#0 RESET# H_RS#0
7 H_REQ#0 K3 F3 H_RS#0 7
H_REQ#1 REQ[0]# RS[0]# H_RS#1 XDP_TCK R444 1 27_0402_5%
7 H_REQ#1 H2 F4 H_RS#1 7 2
H_REQ#2 REQ[1]# RS[1]# H_RS#2
7 H_REQ#2 K2 G3 H_RS#2 7
H_REQ#3 REQ[2]# RS[2]# H_TRDY#
7 H_REQ#3 J3 G2 H_TRDY# 7
H_REQ#4 REQ[3]# TRDY#
7 H_REQ#4 L1
REQ[4]# H_HIT#
7 H_A#[17..35] G6 H_HIT# 7
H_A#17 HIT# H_HITM#
Y2 E4 H_HITM# 7
H_A#18 A[17]# HITM#
U5
H_A#19 A[18]#
R3 AD4
A[19]# BPM[0]#

ADDR GROUP 1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#

XDP/ITP SIGNALS
U4 AD1
H_A#22 A[21]# BPM[2]#
Y5 AC4
H_A#23 A[22]# BPM[3]#
U1 AC2
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 AC1
H_A#25 A[24]# PREQ# XDP_TCK
T5 AC5
H_A#26 A[25]# TCK XDP_TDI
T3 AA6
H_A#27 A[26]# TDI XDP_TDO
W2 AB3 TP6
H_A#28 A[27]# TDO XDP_TMS
W5 AB5
H_A#29 A[28]# TMS XDP_TRST#
Y4 AB6
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 C20 XDP_DBRESET# 19
H_A#31 A[30]# DBR#
V4
H_A#32 A[31]#
W3
A[32]#
PROCHOT# is not used ---> 56 ohms pull-up
H_A#33 AA4 THERMAL
H_A#34 A[33]# H_PROCHOT#
CRB uses 1K ohms pull-up resistor to fix
AB2 1 2
H_A#35 A[34]# R79 56_0402_1% +VCCP PROCHOT# failure when driven by a thermal sensor.
AA3 D21
C H_ADSTB#1 A[35]# PROCHOT# H_THERMDA C
7 H_ADSTB#1 V1 A24
ADSTB[1]# THERMDA H_THERMDC
B25
H_A20M# THERMDC
18 H_A20M# A6
A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP#
18
18
H_FERR#
H_IGNNE#
H_IGNNE# C4
FERR#
IGNNE#
THERMTRIP# H_THERMTRIP# 7,18 FAN1 Control and Tachometer
H_STPCLK# D5
18 H_STPCLK# STPCLK#
H_INTR C6 H CLK
18 H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK
18 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 16
H_SMI# A3 A21 CLK_CPU_BCLK#
18 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 16
M4
RSVD[01]
N5
RSVD[02] H_THERMDA, H_THERMDC routing together,
T2
RSVD[03] Trace width / Spacing = 10 / 10 mil
V3
RSVD[04]
RESERVED

B2 C439
RSVD[05] 10U_0805_10V4Z~N
C3
RSVD[06]
D2 2 1
RSVD[07] +5VS
D22
RSVD[08] H_THRMTRIP# should connect C86
D3
RSVD[09] to ICH8 and GMCH without 1000P_0402_50V7K~N
F6 1 2
RSVD[10] C442 10U_1206_16V4Z~N
T-ing (No stub) 2 1
+VCCP
U1
Merom Ball-out Rev 1a 1 8
conn@ VEN GND
2 7
VIN GND
1

FAN1_POWER 3 6
R76 EN_DFAN1 VO GND
28 EN_DFAN1 4 5
VSET GND
@ 56_0402_5% +3VS APL5605KI-TRL SOP 8P
+VCCP
2 2

1
JFAN1
40mil
B

B @ R130 R378 1 B
54.9_0402_1% 10K_0402_5% 1
2
2
E

H_PROCHOT# 3 1 OCP# 1 2 H_RESET# 3

OCP# 19 3
C

@ Q11

2
MMBT3904_SOT23 4
28 FAN_SPEED1 GND
2 5
GND
C440 ACES_85205-03001
0.01U_0402_16V7K conn@
1
FAN1

Thermal Sensor EMC1402-2-ACZL-TR

+3VS
1
C88
1

0.1U_0402_10V6K R67
2 @ 10K_0402_5%
U2
1 8 EC_SMB_CK2
2

VDD SCLK
H_THERMDA 2 7 EC_SMB_DA2
C104 D+ SDATA
1 2 H_THERMDC 3 6 THERM_SCI# 2 1
D- ALERT# EC_THERM# 19,28
@ R68
2200P_0402_50V7K~N THERM# 4 5 0_0402_5%
THERM# GND
A R75 A

+3VS 1 2 EMC1402-2-ACZL-TR MSOP 8P

10K_0402_5% Address:100_1100

EC_SMB_CK2
28,29,34 EC_SMB_CK2
28,29,34 EC_SMB_DA2
EC_SMB_DA2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(1/3)-AGTL+/XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 4 of 51
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
7 H_D#[0..15] H_D#[32..47] 7
JP1B JP1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 AB24 A9 AB7
H_D#2 D[1]# D[33]# H_D#34 VCC[002] VCC[069]
E26 V24 A10 AC7
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
G22 V26 A12 AC9
D[3]# D[35]# VCC[004] VCC[071]

DATA GRP 0
D H_D#4 F23 V23 H_D#36 A13 AC12 D
H_D#5 D[4]# D[36]# H_D#37 VCC[005] VCC[072]
G25 T22 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 U25 A17 AC15
H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
E23 U23 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18

DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 W22 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 Y23 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 W24 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 W25 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 AA23 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 AA24 B15 AD15
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
H23 AB25 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
7 H_DSTBN#0 J26 Y26 H_DSTBN#2 7 B18 AD18
H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 VCC[017] VCC[084]
7 H_DSTBP#0 H26 AA26 H_DSTBP#2 7 B20 AE9
H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2 VCC[018] VCC[085]
7 H_DINV#0 H25 U22 H_DINV#2 7 C9 AE10
DINV[0]# DINV[2]# VCC[019] VCC[086]
7 H_D#[16..31] H_D#[48..63] 7 C10 AE12
VCC[020] VCC[087]
C12 AE13
H_D#16 H_D#48 VCC[021] VCC[088]
N22 AE24 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 AD24 C15 AE17
H_D#18 D[17]# D[49]# H_D#50 VCC[023] VCC[090]
P26 AA21 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 AB22 C18 AE20
H_D#20 D[19]# D[51]# H_D#52 VCC[025] VCC[092]
L23 AB21 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 AD20 D12 AF12
H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
M23 AE22 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 AF23 D15 AF15
H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
P23 AC25 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 AE21 D18 AF18

DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 AD21 E7 AF20
H_D#28 D[27]# D[59]# H_D#60 VCC[033] VCC[100]
R24 AC22 E9
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 AD23 E10 G21
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01]
T25 AF22 E12 V6
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] C
N25 AC23 E13 J6
H_DSTBN#1 D[31]# D[63]# H_DSTBN#3 VCC[037] VCCP[03]
7 H_DSTBN#1 L26 AE25 H_DSTBN#3 7 E15 K6 1
H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 VCC[038] VCCP[04]
7 H_DSTBP#1 M26 AF24 H_DSTBP#3 7 E17 M6
H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 VCC[039] VCCP[05] C87 +
7 H_DINV#1 N24 AC20 H_DINV#3 7 E18 J21
DINV[1]# DINV[3]# VCC[040] VCCP[06]
E20 K21
V_CPU_GTLREF COMP0 VCC[041] VCCP[07] 330U_V_2.5VM
AD26 R26 F7 M21
R82 TEST1 GTLREF COMP[0] COMP1 VCC[042] VCCP[08] 2
1 2 @ 1K_0402_5% C23 MISC U26 F9 N21 @
R83 TEST2 TEST1 COMP[1] COMP2 VCC[043] VCCP[09]
1 2 @ 1K_0402_5% D25 AA1 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
TP7 C24 Y1 F12 R21
TEST4 TEST3 COMP[3] VCC[045] VCCP[11]
TP8 AF26 F14 R6
TEST5 TEST4 H_DPRSTP# VCC[046] VCCP[12]
TP9 AF1 E5 H_DPRSTP# 7,18,46 F15 T21
TEST5 DPRSTP# VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TP10 TEST6 A26 B5 H_DPSLP# F17 T6
TEST6 DPSLP# H_DPSLP# 18 VCC[048] VCCP[14]

1
D24 H_DPWR# F18 V21
DPWR# H_DPWR# 7 VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
16 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 18 VCC[050] VCCP[16]

R441

R442

R80

R81
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
16 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 7 VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
16 CPU_BSEL2 BSEL[2] PSI# H_PSI# 46 VCC[052] VCCA[01] +1.5VS

0.01U_0402_16V7K~N
AA10 C26

2
Merom Ball-out Rev 1a VCC[053] VCCA[02]

10U_0805_10V4Z~N
AA12
conn@ VCC[054]
AA13 AD6 CPU_VID0 46
VCC[055] VID[0]
AA15 AF5 CPU_VID1 46 1 1
VCC[056] VID[1]
AA17 AE5 CPU_VID2 46
VCC[057] VID[2]

C92

C101
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs Resistor placed within AA18
VCC[058] VID[3]
AF4 CPU_VID3 46
AA20 AE3
0.5" of CPU pin.Trace AB9
VCC[059] VID[4]
AF3
CPU_VID4 46 2 2
VCC[060] VID[5] CPU_VID5 46
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 should be at least 25 AC10
VCC[061] VID[6]
AE2 CPU_VID6 46
AB10
mils away from any other AB12
VCC[062]
VCC[063]
toggling signal. AB14
VCC[064] VCCSENSE
AF7 VCCSENSE VCCSENSE 46
166 0 1 1 COMP[0,2] trace width is AB15
VCC[065] Near pin B26
AB17
18 mils. COMP[1,3] trace VCC[066] VSSSENSE
AB18 AE7 VSSSENSE 46
VCC[067] VSSSENSE
B
width is 4 mils. B
200 0 1 0 Merom Ball-out Rev 1a
conn@ .
Length match within 25 mils.
The trace width/space/other is
+VCCP
20/7/25.
1

R84
1K_0402_1%
+CPU_CORE
2

V_CPU_GTLREF R135
100_0402_1%
1 2 VCCSENSE
1

R136
R77 100_0402_1%
2K_0402_1% 1 2 VSSSENSE
2

Close to CPU pin AD26

within 500mils. Close to CPU pin
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(2/3)-AGTL+/PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 5 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

High Frequence Decoupling

10uF 0805 X5R -> 85 degree.
D D

JP1D +CPU_CORE Place these caps inside

A4
VSS[001] VSS[082]
P6 the CPU socket.
A8
VSS[002] VSS[083]
P21 Place these caps inside
A11
VSS[003] VSS[084]
P24 1 1 1 1 1 1 1 1 1 1 ( Left side on Top ).
A14
VSS[004] VSS[085]
R2 the CPU socket cavity. C201 C528 C529 C232 C255 C505 C504 C254 C253 C211
A16 R5
VSS[005] VSS[086] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A19
VSS[006] VSS[087]
R22 ( Left side on Top ). 2 2 2 2 2 2 2 2 2 2
A23 R25
VSS[007] VSS[088]
AF2 T1
VSS[008] VSS[089]
B6 T4
VSS[009] VSS[090]
B8 T23
VSS[010] VSS[091]
B11 T26
VSS[011] VSS[092]
B13 U3
VSS[012] VSS[093]
B16 U6
VSS[013] VSS[094]
B19
B21
VSS[014] VSS[095]
U21
U24
+CPU_CORE Place these caps inside
VSS[015] VSS[096]
B24
VSS[016] VSS[097]
V2 the CPU socket.
C5
VSS[017] VSS[098]
V5 Place these caps inside
C8
VSS[018] VSS[099]
V22 1 1 1 1 1 1 1 1 1 1 ( Right side on Top ).
C11
VSS[019] VSS[100]
V25 the CPU socket cavity. C154 C181 C252 C164 C150 C188 C155 C197 C208 C226
C14 W1
VSS[020] VSS[101] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
C16
VSS[021] VSS[102]
W4 ( Right side on Top side). 2 2 2 2 2 2 2 2 2 2
C19 W23
VSS[022] VSS[103]
C2 W26
VSS[023] VSS[104]
C22 Y3
VSS[024] VSS[105]
C25 Y6
VSS[025] VSS[106]
D1 Y21
VSS[026] VSS[107]
D4 Y24
VSS[027] VSS[108]
D8 AA2
VSS[028] VSS[109] +CPU_CORE
D11 AA5
C VSS[029] VSS[110] C
D13 AA8
VSS[030] VSS[111]
D16 AA11
VSS[031] VSS[112]
D19
D23
VSS[032] VSS[113]
AA14
AA16
Place these caps inside 1 1 1 1 1 1
VSS[033] VSS[114]
D26
VSS[034] VSS[115]
AA19 the CPU socket cavity. C498
10U_0805_6.3V6M
C508
10U_0805_6.3V6M
C514
10U_0805_6.3V6M
C519
10U_0805_6.3V6M
C522
10U_0805_6.3V6M
C533
10U_0805_6.3V6M
E3 AA22
VSS[035] VSS[116] 2 2 2 2 2 2
E6
VSS[036] VSS[117]
AA25 ( Left side on Bottom ).
E8 AB1
VSS[037] VSS[118]
E11 AB4
VSS[038] VSS[119]
E14 AB8
VSS[039] VSS[120]
E16 AB11
VSS[040] VSS[121]
E19 AB13
VSS[041] VSS[122]
E21 AB16
VSS[042] VSS[123]
E24 AB19
VSS[043] VSS[124] +CPU_CORE
F5 AB23
VSS[044] VSS[125]
F8 AB26
VSS[045] VSS[126]
F11 AC3
VSS[046] VSS[127]
F13
F16
VSS[047] VSS[128]
AC6
AC8
Place these caps inside 1 1 1 1 1 1
VSS[048] VSS[129]
F19
VSS[049] VSS[130]
AC11 the CPU socket cavity. C500
10U_0805_6.3V6M
C510
10U_0805_6.3V6M
C515
10U_0805_6.3V6M
C520
10U_0805_6.3V6M
C526
10U_0805_6.3V6M
C532
10U_0805_6.3V6M
F2 AC14
VSS[050] VSS[131] 2 2 2 2 2 2
F22
VSS[051] VSS[132]
AC16 ( Right side on Bottom ).
F25 AC19
VSS[052] VSS[133]
G4 AC21
VSS[053] VSS[134]
G1 AC24
VSS[054] VSS[135]
G23 AD2
VSS[055] VSS[136]
G26 AD5
VSS[056] VSS[137]
H3 AD8
VSS[057] VSS[138]
H6 AD11
VSS[058] VSS[139]
H21 AD13
VSS[059] VSS[140] +CPU_CORE
H24 AD16
VSS[060] VSS[141]
J2 AD19
B VSS[061] VSS[142] B
J5 AD22
VSS[062] VSS[143]
J22 AD25
VSS[063] VSS[144]
ESR <= 1.5m ohm
330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

J25
K1
VSS[064] VSS[145]
AE1
AE4
Place these caps inside Place these caps inside
VSS[065] VSS[146] 1 1 1
K4
VSS[066] VSS[147]
AE8 the CPU socket. the CPU socket.
C170

C186

C237

K23 AE11 + + +
K26
L3
VSS[067]
VSS[068]
VSS[148]
VSS[149]
AE14
AE16
( Left side on Top ). ( Right side on Top side). Capacitor > 880 uF
VSS[069] VSS[150] 2 2 2
L6 AE19
VSS[070] VSS[151]
L21 AE23
VSS[071] VSS[152]
L24 AE26
VSS[072] VSS[153]
M2 A2
VSS[073] VSS[154]
M5 AF6
VSS[074] VSS[155]
M22 AF8
VSS[075] VSS[156]
M25 AF11 Place these outside of
VSS[076] VSS[157]
N1 AF13 socket cavity on L8
VSS[077] VSS[158]
N4 AF16 (North side Secondary)
VSS[078] VSS[159]
N23 AF19
VSS[079] VSS[160]
N26 AF21
VSS[080] VSS[161] +VCCP
P3 A25
VSS[081] VSS[162]
AF25
VSS[163]
Merom Ball-out Rev 1a 1
. 1 1 1 1 1 1
C588 + C100 C98 C97 C579 C578 C99

220U 4V Y D2 ESR15M 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(3/3)-GND&Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 6 of 51
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] 4 U3B For Crestline: 20ohm

5 H_D#[0..63] U3A For Calero: 80.6ohm
J13 H_A#3 P36
H_D#0 H_A#_3 H_A#4 RSVD1 M_CLK_DDR0
E2 B11 P37 AV29 M_CLK_DDR0 13
H_D#1 H_D#_0 H_A#_4 H_A#5 RSVD2 SM_CK_0 M_CLK_DDR1
G2 C11 R35 BB23 M_CLK_DDR1 13
H_D#2 H_D#_1 H_A#_5 H_A#6 RSVD3 SM_CK_1 M_CLK_DDR2
G7 M11 N35 BA25 M_CLK_DDR2 14
H_D#_2 H_A#_6 +1.8V RSVD4 SM_CK_3

0.01U_0402_25V7K~N
H_D#3 H_A#7 M_CLK_DDR3

2.2U_0603_106K
M6 C15 AR12 AV23 M_CLK_DDR3 14
H_D#4 H_D#_3 H_A#_7 H_A#8 RSVD5 SM_CK_4
H7 F16 AR13
H_D#5 H_D#_4 H_A#_8 H_A#9 RSVD6 M_CLK_DDR#0
H3 L13 2 2 AM12 AW30 M_CLK_DDR#0 13
H_D#_5 H_A#_9 RSVD7 SM_CK#_0

1
H_D#6 G4 G17 H_A#10 AN13 BA23 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SM_CK#_1 M_CLK_DDR#1 13
H_D#7 F3 C14 H_A#11 R383 J12 AW25 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SM_CK#_3 M_CLK_DDR#2 14

C463

RSVD
C444
H_D#8 N8 K16 H_A#12 AR37 AW23 M_CLK_DDR#3
H_D#_8 H_A#_12 1 1 RSVD10 SM_CK#_4 M_CLK_DDR#3 14
H_D#9 H2 B13 H_A#13 1K_0402_1% AM36
H_D#10 H_D#_9 H_A#_13 H_A#14 RSVD11 DDR_CKE0_DIMMA
M10 L16 AL36 BE29 DDR_CKE0_DIMMA 13

2
H_D#11 H_D#_10 H_A#_14 H_A#15 SMRCOMP_VOH RSVD12 SM_CKE_0 DDR_CKE1_DIMMA
N12 J17 AM37 AY32 DDR_CKE1_DIMMA 13
D H_D#12 H_D#_11 H_A#_15 H_A#16 RSVD13 SM_CKE_1 DDR_CKE2_DIMMB D
N9 B14 D20 BD39 DDR_CKE2_DIMMB 14
H_D#_12 H_A#_16 RSVD14 SM_CKE_3

1
H_D#13 H5 K19 H_A#17 BG37 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SM_CKE_4 DDR_CKE3_DIMMB 14
H_D#14 P13 P15 H_A#18 R381
H_D#15 H_D#_14 H_A#_18 H_A#19 3.01K_0402_1% DDR_CS0_DIMMA#
K9 R17 BG20 DDR_CS0_DIMMA# 13
H_D#16 H_D#_15 H_A#_19 H_A#20 NA lead free SM_CS#_0 DDR_CS1_DIMMA#
M2 B16 BK16 DDR_CS1_DIMMA# 13
H_D#17 H_D#_16 H_A#_20 H_A#21 SM_CS#_1 DDR_CS2_DIMMB#
W10 H20 BG16 DDR_CS2_DIMMB# 14

2
H_D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL SM_CS#_2 DDR_CS3_DIMMB#
Y8 L19 H10 BE13 DDR_CS3_DIMMB# 14
H_D#19 H_D#_18 H_A#_22 H_A#23 RSVD20 SM_CS#_3
V4 D17 B51

MUXING
H_D#_19 H_A#_23 RSVD21

1
2.2U_0603_106K
H_D#20 H_A#24 M_ODT0

0.01U_0402_25V7K~N
M3 M17 BJ20 BH18 M_ODT0 13
H_D#21 H_D#_20 H_A#_24 H_A#25 R384 RSVD22 SM_ODT_0 M_ODT1
J1 N16 1 1 BK22 BJ15 M_ODT1 13
H_D#22 H_D#_21 H_A#_25 H_A#26 RSVD23 SM_ODT_1 M_ODT2 +1.8V
N5 J19 BF19 BJ14 M_ODT2 14
H_D#23 H_D#_22 H_A#_26 H_A#27 1K_0402_1% RSVD24 SM_ODT_2 M_ODT3
N3 B18 BH20 BE16 M_ODT3 14
H_D#_23 H_A#_27 RSVD25 SM_ODT_3

C445

C464
H_D#24 W6 E19 H_A#28 BK18

2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RSVD26 SMRCOMP R385
W9 B17 BJ18 BL15 2 1 20_0402_1%
H_D#26 H_D#_25 H_A#_29 H_A#30 RSVD27 SM_RCOMP SMRCOMP#
N2 B15 BF23 BK14 2 1
H_D#27 H_D#_26 H_A#_30 H_A#31 RSVD28 SM_RCOMP# R386 20_0402_1%
Y7 E17 BG23
H_D#28 H_D#_27 H_A#_31 H_A#32 RSVD29 SMRCOMP_VOH
Y9 C18 BC23 BK31
H_D#29 H_D#_28 H_A#_32 H_A#33 RSVD30 SM_RCOMP_VOH SMRCOMP_VOL
P4 A19 BD24 BL31

DDR
H_D#30 H_D#_29 H_A#_33 H_A#34 RSVD31 SM_RCOMP_VOL
W3 B19 13 DDR_A_MA14 BJ29
H_D#31 H_D#_30 H_A#_34 H_A#35 RSVD32
N1 N19 14 DDR_B_MA14 BE24 AR49
H_D#32 H_D#_31 H_A#_35 RSVD33 SM_VREF_0 +DDR_MCH_REF
AD12 BH39 AW4
H_D#33 H_D#_32 H_ADS# RSVD34 SM_VREF_1
AE3 G12 H_ADS# 4 AW20
H_D#34 H_D#_33 H_ADS# H_ADSTB#0 +3VS RSVD35
AD9 HOST H17 H_ADSTB#0 4 BK20
H_D#35 H_D#_34 H_ADSTB#_0 H_ADSTB#1 R115 RSVD36
AC9 G20 H_ADSTB#1 4 C48
H_D#36 H_D#_35 H_ADSTB#_1 H_BNR# PM_EXTTS#0 RSVD37 CLK_MCH_DREFCLK
AC7 C8 H_BNR# 4 2 1 D47 B42 CLK_MCH_DREFCLK 16
H_D#37 H_D#_36 H_BNR# H_BPRI# RSVD38 DPLL_REF_CLK CLK_MCH_DREFCLK#
AC14 E8 H_BPRI# 4 B44 C42 CLK_MCH_DREFCLK# 16
H_D#38 H_D#_37 H_BPRI# H_BR0# 10K_0402_5% RSVD39 DPLL_REF_CLK# MCH_SSCDREFCLK
AD11 F12 H_BR0# 4 C44 H48 MCH_SSCDREFCLK 16
H_D#39 H_D#_38 H_BREQ# H_DEFER# RSVD40 DPLL_REF_SSCLK MCH_SSCDREFCLK#
AC11 D6 H_DEFER# 4 A35 H47 MCH_SSCDREFCLK# 16
H_D#40 H_D#_39 H_DEFER# H_DBSY# R128 RSVD41 DPLL_REF_SSCLK#
AB2 C10 H_DBSY# 4 B37
H_D#41 H_D#_40 H_DBSY# CLK_MCH_BCLK PM_EXTTS#1 RSVD42 CLK_MCH_3GPLL
AD7 AM5 CLK_MCH_BCLK 16 2 1 B36 K44 CLK_MCH_3GPLL 16
H_D#_41 HPLL_CLK RSVD43 PEG_CLK

CLK
H_D#42 AB1 AM7 CLK_MCH_BCLK# B34 K45 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 16 RSVD44 PEG_CLK# CLK_MCH_3GPLL# 16
H_D#43 Y3 H8 H_DPWR# 10K_0402_5% C34
C H_D#_43 H_DPWR# H_DPWR# 5 RSVD45 C
H_D#44 AC6 K7 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AE2 E4 H_HIT#
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AC5 C6 H_HITM# AN47 DMI_TXN0
H_D#_46 H_HITM# H_HITM# 4 DMI_RXN_0 DMI_TXN0 19
H_D#47 AG3 G10 H_LOCK# AJ38 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# 4 DMI_RXN_1 DMI_TXN1 19
H_D#48 AJ9 B7 H_TRDY# AN42 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# 4 DMI_RXN_2 DMI_TXN2 19
H_D#49 AH8 AN46 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 19
H_D#50 AJ14
H_D#51 H_D#_50 DMI_TXP0
AE9 AM47 DMI_TXP0 19
H_D#52 H_D#_51 MCH_CLKSEL0 DMI_RXP_0 DMI_TXP1
AE11 16 MCH_CLKSEL0 P27 AJ39 DMI_TXP1 19
+VCCP H_D#53 H_D#_52 H_DINV#0 MCH_CLKSEL1 CFG_0 DMI_RXP_1 DMI_TXP2
AH12 K5 H_DINV#0 5 16 MCH_CLKSEL1 N27 AN41 DMI_TXP2 19
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 MCH_CLKSEL2 CFG_1 DMI_RXP_2 DMI_TXP3
AJ5 L2 H_DINV#1 5 16 MCH_CLKSEL2 N24 AN45 DMI_TXP3 19
H_D#55 H_D#_54 H_DINV#_1 H_DINV#2 CFG_2 DMI_RXP_3
AH5 AD13 H_DINV#2 5 PAD TP11 C21
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 CFG_3 DMI_RXN0
AJ6 AE13 H_DINV#3 5 PAD TP12 C23 AJ46 DMI_RXN0 19
H_D#_56 H_DINV#_3 CFG_4 DMI_TXN_0
54.9_0402_1%

54.9_0402_1%

H_D#57 AE7 CFG5 F23 AJ41 DMI_RXN1

H_D#_57 9 CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 19
1

H_D#58 AJ7 M7 H_DSTBN#0 PAD TP43 N23 AM40 DMI_RXN2

H_D#_58 H_DSTBN#_0 H_DSTBN#0 5 CFG_6 DMI_TXN_2 DMI_RXN2 19
H_D#59 AJ2 K3 H_DSTBN#1 CFG7 G23 AM44 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 5 9 CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 19
R98

R97

H_D#60 AE5 AD2 H_DSTBN#2 J20

DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5 9 CFG8 CFG_8

CFG
H_D#61 AJ3 AH11 H_DSTBN#3 CFG9 C20 AJ47 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5 9 CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 19
H_D#62 AH2 PAD TP44 R24 AJ42 DMI_RXP1
DMI_RXP1 19
2

H_D#63 H_D#_62 H_DSTBP#0 CFG_10 DMI_TXP_1 DMI_RXP2

AH13 L7 H_DSTBP#0 5 PAD TP45 L23 AM39 DMI_RXP2 19
H_D#_63 H_DSTBP#_0 H_DSTBP#1 CFG12 CFG_11 DMI_TXP_2 DMI_RXP3
K2 H_DSTBP#1 5 9 CFG12 J23 AM43 DMI_RXP3 19
H_DSTBP#_1 H_DSTBP#2 CFG13 CFG_12 DMI_TXP_3
AC2 H_DSTBP#2 5 9 CFG13 E23
H_SWNG H_DSTBP#_2 H_DSTBP#3 CFG_13
B3 AJ10 H_DSTBP#3 5 PAD TP13 E20
H_RCOMP H_SWING H_DSTBP#_3 CFG_14 R596 0_0402_5% VGA@
C2 PAD TP14 K23
H_RCOMP H_REQ#0 CFG16 CFG_15 CLK_MCH_DREFCLK 2
M14 H_REQ#0 4 9 CFG16 M20 1
H_SCOMP H_REQ#_0 H_REQ#1 CFG_16 R599 0_0402_5% VGA@
W1 E13 H_REQ#1 4 PAD TP15 M24
H_SCOMP H_REQ#_1 CFG_17

GRAPHICS VID
H_SCOMP# W2 A11 H_REQ#2 PAD TP42 L32 CLK_MCH_DREFCLK# 2 1
H_SCOMP# H_REQ#_2 H_REQ#2 4 CFG_18
H13 H_REQ#3 CFG19 N33 R267 0_0402_5% VGA@
H_REQ#_3 H_REQ#3 4 9 CFG19 CFG_19
H_RESET# B6 B12 H_REQ#4 CFG20 L35 MCH_SSCDREFCLK 2 1
4 H_RESET# H_CPURST# H_REQ#_4 H_REQ#4 4 9 CFG20 CFG_20
5 H_CPUSLP# H_CPUSLP# E5 R268 0_0402_5% VGA@
H_CPUSLP# H_RS#0 MCH_SSCDREFCLK# 2
E12 H_RS#0 4 1
H_RS#_0 H_RS#1
D7 H_RS#1 4 E35 TP16 PAD
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_0 B
D8 H_RS#2 4 19 PM_BMBUSY# G41 A39 TP17 PAD
H_RS#_2 H_DPRSTP# PM_BM_BUSY# GFX_VID_1
B9 5,18,46 H_DPRSTP# L39 C38 TP18 PAD
H_VREF H_AVREF PM_EXTTS#0 PM_DPRSTP# GFX_VID_2
A9 13 PM_EXTTS#0 L36 B39 TP19 PAD
H_DVREF PM_EXT_TS#_0 GFX_VID_3

PM
PM_EXTTS#1 J36 E36
14 PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN TP20 PAD
CRESTLINE_1p0 UMA@ PM_POK_R AW49
PLT_RST#_R PWROK +1.25VM_AXD
layout note: R116 0_0402_5% AV20
RSTIN#
4,18 H_THERMTRIP# 2 1 THERMTRIP# N20
DPRSLPVR THERMTRIP#
19,46 DPRSLPVR G36
DPRSLPVR

1
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
AM49 CL_CLK0 R396
CL_CLK CL_CLK0 19
AK50 CL_DATA0
CL_DATA CL_DATA0 19
Layout Note: BJ51
NC_1 CL_PWROK
AT43 M_PWROK
M_PWROK 19
1K_0402_1%
Layout Note: CL_RST#

ME
+DDR_MCH_REF BK51 AN49 CL_RST# 19

2
+1.8V NC_2 CL_RST# CL_VREF CL_VREF
BK50 AM50
H_RCOMP / H_VREF / H_SWNG trace width and BL50
NC_3 CL_VREF
NC_4

1
trace width and spacing is 10/20 spacing is 20/20. BL49
NC_5 1
1

BL3 C501 R395

R91 NC_6 0.1U_0402_16V4Z~N 392_0402_1%
BL2
NC_7

NC
1K_0402_1% BK1 12 mil
NC_8 2
BJ1 H35

2
+VCCP NC_9 SDVO_CTRL_CLK
E1 K36

MISC
2

+VCCP +DDR_MCH_REF NC_10 SDVO_CTRL_DATA CLKMCHREQ#

A5 G39 CLKMCHREQ# 16
NC_11 CLK_REQ# MCH_ICH_SYNC#
0.1U_0402_16V4Z~N

C51 G40 MCH_ICH_SYNC# 19

NC_12 ICH_SYNC#
1
1K_0402_1%

221_0402_1%

B50
NC_13
1

1 R90 A50
NC_14
R448

1K_0402_1% A49 A37

NC_15 TEST_1
R434

C157

BK2 R32
NC_16 TEST_2
2

1
0.1U_0402_16V4Z~N 2 CRESTLINE_1p0 UMA@
2

H_VREF H_RCOMP H_SWNG R106 R429

24.9_0402_1%

close to NB 20K_0402_5% 0_0402_5%

0.1U_0402_16V4Z~N
1

1
2K_0402_1%

100_0402_1%

A 2 1 PM_POK_R A
1 1 19,28 PM_PWROK

2
R87 0_0402_5%
R433

C571

R435

R437

C564

PLT_RST# 1 2 PLT_RST#_R
2 2 17,19,22,26,27,28,33 PLT_RST#
R89 100_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

within 100 mils from NB Near B3 pin Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(1/6)-AGTL+/DMI/DDR2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 7 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

D D

13 DDR_A_D[0..63] 14 DDR_B_D[0..63]
U3D U3E
DDR_A_D0 AR43 BB19 DDR_A_BS#0 DDR_B_D0 AP49 AY17 DDR_B_BS#0
SA_DQ_0 SA_BS_0 DDR_A_BS#0 13 SB_DQ_0 SB_BS_0 DDR_B_BS#0 14
DDR_A_D1 AW44 BK19 DDR_A_BS#1 DDR_B_D1 AR51 BG18 DDR_B_BS#1
SA_DQ_1 SA_BS_1 DDR_A_BS#1 13 SB_DQ_1 SB_BS_1 DDR_B_BS#1 14
DDR_A_D2 BA45 BF29 DDR_A_BS#2 DDR_B_D2 AW50 BG36 DDR_B_BS#2
SA_DQ_2 SA_BS_2 DDR_A_BS#2 13 SB_DQ_2 SB_BS_2 DDR_B_BS#2 14
DDR_A_D3 AY46 DDR_B_D3 AW51
DDR_A_D4 SA_DQ_3 DDR_A_CAS# DDR_B_D4 SB_DQ_3 DDR_B_CAS#
AR41 BL17 DDR_A_CAS# 13 AN51 BE17 DDR_B_CAS# 14
DDR_A_D5 SA_DQ_4 SA_CAS# DDR_B_D5 SB_DQ_4 SB_CAS#
AR45 DDR_A_DM[0..7] 13 AN50 DDR_B_DM[0..7] 14
DDR_A_D6 SA_DQ_5 DDR_A_DM0 DDR_B_D6 SB_DQ_5 DDR_B_DM0
AT42 AT45 AV50 AR50
DDR_A_D7 SA_DQ_6 SA_DM_0 DDR_A_DM1 DDR_B_D7 SB_DQ_6 SB_DM_0 DDR_B_DM1
AW47 BD44 AV49 BD49
DDR_A_D8 SA_DQ_7 SA_DM_1 DDR_A_DM2 DDR_B_D8 SB_DQ_7 SB_DM_1 DDR_B_DM2
BB45 BD42 BA50 BK45
DDR_A_D9 SA_DQ_8 SA_DM_2 DDR_A_DM3 DDR_B_D9 SB_DQ_8 SB_DM_2 DDR_B_DM3
BF48 AW38 BB50 BL39
DDR_A_D10 SA_DQ_9 SA_DM_3 DDR_A_DM4 DDR_B_D10 SB_DQ_9 SB_DM_3 DDR_B_DM4
BG47 AW13 BA49 BH12
DDR_A_D11 SA_DQ_10 SA_DM_4 DDR_A_DM5 DDR_B_D11 SB_DQ_10 SB_DM_4 DDR_B_DM5
BJ45 BG8 BE50 BJ7
DDR_A_D12 SA_DQ_11 SA_DM_5 DDR_A_DM6 DDR_B_D12 SB_DQ_11 SB_DM_5 DDR_B_DM6
BB47 AY5 BA51 BF3
DDR_A_D13 SA_DQ_12 SA_DM_6 DDR_A_DM7 DDR_B_D13 SB_DQ_12 SB_DM_6 DDR_B_DM7
BG50 AN6 AY49 AW2
DDR_A_D14 SA_DQ_13 SA_DM_7 DDR_B_D14 SB_DQ_13 SB_DM_7
BH49 DDR_A_DQS[0..7] 13 BF50 DDR_B_DQS[0..7] 14
DDR_A_D15 SA_DQ_14 DDR_A_DQS0 DDR_B_D15 SB_DQ_14 DDR_B_DQS0
BE45 AT46 BF49 AT50

B
DDR_A_D16 SA_DQ_15 SA_DQS_0 DDR_A_DQS1 DDR_B_D16 SB_DQ_15 SB_DQS_0 DDR_B_DQS1
AW43 BE48 BJ50 BD50
DDR_A_D17 SA_DQ_16 SA_DQS_1 DDR_A_DQS2 DDR_B_D17 SB_DQ_16 SB_DQS_1 DDR_B_DQS2
BE44 BB43 BJ44 BK46
DDR_A_D18 SA_DQ_17 SA_DQS_2 DDR_A_DQS3 DDR_B_D18 SB_DQ_17 SB_DQS_2 DDR_B_DQS3
BG42 BC37 BJ43 BK39
DDR_A_D19 SA_DQ_18 SA_DQS_3 DDR_A_DQS4 DDR_B_D19 SB_DQ_18 SB_DQS_3 DDR_B_DQS4
BE40 BB16 BL43 BJ12
DDR_A_D20 SA_DQ_19 SA_DQS_4 DDR_A_DQS5 DDR_B_D20 SB_DQ_19 SB_DQS_4 DDR_B_DQS5

MEMORY
BF44 BH6 BK47 BL7

MEMORY
DDR_A_D21 SA_DQ_20 SA_DQS_5 DDR_A_DQS6 DDR_B_D21 SB_DQ_20 SB_DQS_5 DDR_B_DQS6
BH45 BB2 BK49 BE2
DDR_A_D22 SA_DQ_21 SA_DQS_6 DDR_A_DQS7 DDR_B_D22 SB_DQ_21 SB_DQS_6 DDR_B_DQS7
BG40 AP3 DDR_A_DQS#[0..7] 13 BK43 AV2 DDR_B_DQS#[0..7] 14
DDR_A_D23 SA_DQ_22 SA_DQS_7 DDR_A_DQS#0 DDR_B_D23 SB_DQ_22 SB_DQS_7 DDR_B_DQS#0
BF40 AT47 BK42 AU50
DDR_A_D24 SA_DQ_23 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D24 SB_DQ_23 SB_DQS#_0 DDR_B_DQS#1
AR40 BD47 BJ41 BC50
DDR_A_D25 SA_DQ_24 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D25 SB_DQ_24 SB_DQS#_1 DDR_B_DQS#2
AW40 BC41 BL41 BL45
DDR_A_D26 SA_DQ_25 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D26 SB_DQ_25 SB_DQS#_2 DDR_B_DQS#3
AT39 BA37 BJ37 BK38
DDR_A_D27 SA_DQ_26 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D27 SB_DQ_26 SB_DQS#_3 DDR_B_DQS#4
AW36 BA16 BJ36 BK12
DDR_A_D28 SA_DQ_27 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D28 SB_DQ_27 SB_DQS#_4 DDR_B_DQS#5
AW41 BH7 BK41 BK7
C DDR_A_D29 SA_DQ_28 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D29 SB_DQ_28 SB_DQS#_5 DDR_B_DQS#6 C
AY41 BC1 BJ40 BF2
DDR_A_D30 SA_DQ_29 SA_DQS#_6 DDR_A_DQS#7 DDR_B_D30 SB_DQ_29 SB_DQS#_6 DDR_B_DQS#7
AV38 AP2 DDR_A_MA[0..13] 13 BL35 AV3
DDR_A_D31 SA_DQ_30 SA_DQS#_7 DDR_B_D31 SB_DQ_30 SB_DQS#_7
AT38 BK37 DDR_B_MA[0..13] 14
DDR_A_D32 SA_DQ_31 DDR_A_MA0 DDR_B_D32 SB_DQ_31 DDR_B_MA0
AV13 BJ19 BK13 BC18
SA_DQ_32 SA_MA_0 SB_DQ_32 SB_MA_0
SYSTEM

DDR_A_D33 AT13 BD20 DDR_A_MA1 DDR_B_D33 BE11 BG28 DDR_B_MA1

SYSTEM
DDR_A_D34 SA_DQ_33 SA_MA_1 DDR_A_MA2 DDR_B_D34 SB_DQ_33 SB_MA_1 DDR_B_MA2
AW11 BK27 BK11 BG25
DDR_A_D35 SA_DQ_34 SA_MA_2 DDR_A_MA3 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
AV11 BH28 BC11 AW17
DDR_A_D36 SA_DQ_35 SA_MA_3 DDR_A_MA4 DDR_B_D36 SB_DQ_35 SB_MA_3 DDR_B_MA4
AU15 BL24 BC13 BF25
DDR_A_D37 SA_DQ_36 SA_MA_4 DDR_A_MA5 DDR_B_D37 SB_DQ_36 SB_MA_4 DDR_B_MA5
AT11 BK28 BE12 BE25
DDR_A_D38 SA_DQ_37 SA_MA_5 DDR_A_MA6 DDR_B_D38 SB_DQ_37 SB_MA_5 DDR_B_MA6
BA13 BJ27 BC12 BA29
DDR_A_D39 SA_DQ_38 SA_MA_6 DDR_A_MA7 DDR_B_D39 SB_DQ_38 SB_MA_6 DDR_B_MA7
BA11 BJ25 BG12 BC28
DDR_A_D40 SA_DQ_39 SA_MA_7 DDR_A_MA8 DDR_B_D40 SB_DQ_39 SB_MA_7 DDR_B_MA8
BE10 BL28 BJ10 AY28
DDR_A_D41 SA_DQ_40 SA_MA_8 DDR_A_MA9 DDR_B_D41 SB_DQ_40 SB_MA_8 DDR_B_MA9
BD10 BA28 BL9 BD37
DDR_A_D42 SA_DQ_41 SA_MA_9 DDR_A_MA10 DDR_B_D42 SB_DQ_41 SB_MA_9 DDR_B_MA10
BD8 BC19 BK5 BG17
DDR_A_D43 SA_DQ_42 SA_MA_10 DDR_A_MA11 DDR_B_D43 SB_DQ_42 SB_MA_10 DDR_B_MA11
AY9 BE28 BL5 BE37
DDR_A_D44 SA_DQ_43 SA_MA_11 DDR_A_MA12 DDR_B_D44 SB_DQ_43 SB_MA_11 DDR_B_MA12
BG10 BG30 BK9 BA39
DDR_A_D45 SA_DQ_44 SA_MA_12 DDR_A_MA13 DDR_B_D45 SB_DQ_44 SB_MA_12 DDR_B_MA13
AW9 BJ16 BK10 BG13
SA_DQ_45 SA_MA_13 SB_DQ_45 SB_MA_13
DDR

DDR_A_D46 BD7 DDR_B_D46 BJ8

DDR
DDR_A_D47 SA_DQ_46 DDR_B_D47 SB_DQ_46 DDR_B_RAS#
BB9 BJ6 AV16 DDR_B_RAS# 14
DDR_A_D48 SA_DQ_47 DDR_A_RAS# DDR_B_D48 SB_DQ_47 SB_RAS# SB_RCVEN#
BB5 BE18 DDR_A_RAS# 13 BF4 AY18
DDR_A_D49 SA_DQ_48 SA_RAS# SA_RCVEN# DDR_B_D49 SB_DQ_48 SB_RCVEN# TP21
AY7 AY20 BH5
DDR_A_D50 SA_DQ_49 SA_RCVEN# TP22 DDR_B_D50 SB_DQ_49 DDR_B_WE#
AT5 BG1 BC17 DDR_B_WE# 14
DDR_A_D51 SA_DQ_50 DDR_A_WE# DDR_B_D51 SB_DQ_50 SB_WE#
AT7 BA19 DDR_A_WE# 13 BC2
DDR_A_D52 SA_DQ_51 SA_WE# DDR_B_D52 SB_DQ_51
AY6 BK3
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52
BB7 BE4
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AR5 BD3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AR8 BJ2
DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
AR9 BA3
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AN3 BB3
DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
AM8 AR1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AN10 AT3
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AT9 AY2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AN9 AY3
DDR_A_D62 SA_DQ_61 DDR_B_D62 SB_DQ_61
AM9 AU2
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AN11 AT2
SA_DQ_63 SB_DQ_63
CRESTLINE_1p0 UMA@ CRESTLINE_1p0 UMA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 8 of 51
5 4 3 2 1
 5 4 3 2 1

For Crestline:2.4kohm
For Calero: 1.5Kohm
U3C
PEGCOMP trace width

BIA_PWM
R123
+VCCP
and spacing is 20/25 mils. Strap Pin Table
15 BIA_PWM J40 24.9_0402_1%
GMCH_ENBKL L_BKLT_CTRL PEGCOMP
28 GMCH_ENBKL H39 N43 1 2
R446 1 CTRL_CLK L_BKLT_EN PEG_COMPI
+3VS 210K_0402_5% UMA@ E39 M43 010 = FSB 800MHz
R463 1 CTRL_DATA L_CTRL_CLK PEG_COMPO
210K_0402_5% UMA@ E40 PEG_NRX_GTX_N[0..15] 33
GMCH_EDID_CLK_LCD L_CTRL_DATA
15 GMCH_EDID_CLK_LCD C37
L_DDC_CLK CFG[2:0] FSB Freq select 011 = FSB 667MHz
GMCH_EDID_DAT_LCD D35 J51 PEG_NRX_GTX_N0
15 GMCH_EDID_DAT_LCD L_DDC_DATA PEG_RX#_0
15,28 GMCH_LVDDEN GMCH_LVDDEN K40 L51 PEG_NRX_GTX_N1 Others = Reserved
L_VDD_EN PEG_RX#_1 PEG_NRX_GTX_N2
N47
PEG_RX#_2 PEG_NRX_GTX_N3
2 1 L41 T45
R122 2.4K_0402_1% LVDS_IBG PEG_RX#_3 PEG_NRX_GTX_N4
L43
LVDS_VBG PEG_RX#_4
T50 0 = DMI x 2
D N41 U40 PEG_NRX_GTX_N5 CFG5 (DMI select) D
LVDS_VREFH PEG_RX#_5 PEG_NRX_GTX_N6
N40 Y44 1 = DMI x 4
15 GMCH_LVDSAC-
15 GMCH_LVDSAC+
GMCH_LVDSAC-
GMCH_LVDSAC+
D46
C45
LVDS_VREFL
LVDSA_CLK#
PEG_RX#_6
PEG_RX#_7
Y40
AB51
PEG_NRX_GTX_N7
PEG_NRX_GTX_N8
*
GMCH_LVDSBC- LVDSA_CLK PEG_RX#_8 PEG_NRX_GTX_N9
15 GMCH_LVDSBC- D44
LVDSB_CLK# PEG_RX#_9
W49 CFG6 Reserved
15 GMCH_LVDSBC+ GMCH_LVDSBC+ E42 AD44 PEG_NRX_GTX_N10
LVDSB_CLK PEG_RX#_10

LVDS
AD40 PEG_NRX_GTX_N11
GMCH_LVDSA0- PEG_RX#_11 PEG_NRX_GTX_N12
15 GMCH_LVDSA0- G51
LVDSA_DATA#_0 PEG_RX#_12
AG46 CFG7 (CPU Strap) 0 = Reserved
15 GMCH_LVDSA1- GMCH_LVDSA1- E51 AH49 PEG_NRX_GTX_N13
GMCH_LVDSA2- LVDSA_DATA#_1 PEG_RX#_13 PEG_NRX_GTX_N14
F49 AG45 1 = Mobile CPU
15 GMCH_LVDSA2- LVDSA_DATA#_2 PEG_RX#_14
PEG_RX#_15
AG41 PEG_NRX_GTX_N15
PEG_NRX_GTX_P[0..15] 33 *

GRAPHICS
15 GMCH_LVDSA0+ GMCH_LVDSA0+ G50 J50 PEG_NRX_GTX_P0 0 = Normal mode
GMCH_LVDSA1+ LVDSA_DATA_0 PEG_RX_0 PEG_NRX_GTX_P1
15 GMCH_LVDSA1+ E50
LVDSA_DATA_1 PEG_RX_1
L50 CFG8 (Low power PCIE)
GMCH_LVDSA2+ F48 M47 PEG_NRX_GTX_P2 1 = Low Power mode
15 GMCH_LVDSA2+ LVDSA_DATA_2 PEG_RX_2
PEG_RX_3
U44
T49
PEG_NRX_GTX_P3
PEG_NRX_GTX_P4
*
GMCH_LVDSB0- PEG_RX_4 PEG_NRX_GTX_P5
15 GMCH_LVDSB0- G44
LVDSB_DATA#_0 PEG_RX_5
T41 CFG9 0 = Reverse Lane
15 GMCH_LVDSB1- GMCH_LVDSB1- B47 W45 PEG_NRX_GTX_P6
GMCH_LVDSB2- LVDSB_DATA#_1 PEG_RX_6 PEG_NRX_GTX_P7
B45 W41 (PCIE Graphics Lane Reversal) 1 = Normal Operation
15 GMCH_LVDSB2- LVDSB_DATA#_2 PEG_RX_7
PEG_RX_8
AB50
Y48
PEG_NRX_GTX_P8
PEG_NRX_GTX_P9
*
GMCH_LVDSB0+ PEG_RX_9 PEG_NRX_GTX_P10
15 GMCH_LVDSB0+ E44 AC45
GMCH_LVDSB1+ LVDSB_DATA_0 PEG_RX_10 PEG_NRX_GTX_P11
15 GMCH_LVDSB1+ A47
LVDSB_DATA_1 PEG_RX_11
AC41 CFG[11:10] Reserved
15 GMCH_LVDSB2+ GMCH_LVDSB2+ A45 AH47 PEG_NRX_GTX_P12
LVDSB_DATA_2 PEG_RX_12 PEG_NRX_GTX_P13

PCI-EXPRESS
AG49
PEG_RX_13
AH45 PEG_NRX_GTX_P14 00 = Reserved
PEG_RX_14 PEG_NTX_GRX_N[0..15] 33
AG42 PEG_NRX_GTX_P15 CFG[13:12] (XOR/ALLZ) 01 = XOR Mode Enabled
PEG_RX_15
10 = All Z Mode Enabled
1 2 E27 N45 PEG_TXN0 C447 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N0 11 = Normal Operation (Default)
75_0402_1%1
75_0402_1%1
2 R455
2 R450
G27
K27
TVA_DAC
TVB_DAC
PEG_TX#_0
PEG_TX#_1
U39
U47
PEG_TXN1
PEG_TXN2
C465
C482
1
1
2
2
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
PEG_NTX_GRX_N1
PEG_NTX_GRX_N2
*
TVC_DAC PEG_TX#_2

TV
C 75_0402_1% R126 PEG_TXN3 C461 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N3 C
PEG_TX#_3
N51 1 2 CFG[15:14] Reserved
F27 R50 PEG_TXN4 C477 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N4
TVA_RTN PEG_TX#_4 PEG_TXN5 C459 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N5
J27 T42 1 2
TVB_RTN PEG_TX#_5 PEG_TXN6 C475 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N6
L27
TVC_RTN PEG_TX#_6
Y43 1 2 CFG16 (FSB Dynamic ODT) 0 = Disabled
W46 PEG_TXN7 C457 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N7
PEG_TX#_7 PEG_TXN8 C473 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N8
M35 W38 1 2 1 = Enabled
P33
TV_DCONSEL_0
TV_DCONSEL_1
PEG_TX#_8
PEG_TX#_9
AD39
AC46
PEG_TXN9
PEG_TXN10
C455
C471
1
1
2
2
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
PEG_NTX_GRX_N9
PEG_NTX_GRX_N10
*
PEG_TX#_10 PEG_TXN11 C453 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N11
PEG_TX#_11
AC49 1 2 CFG[18:17] Reserved
CRT_B AC42 PEG_TXN12 C469 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N12
15 CRT_B PEG_TX#_12
CRT_G AH39 PEG_TXN13 C451 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N13
15 CRT_G PEG_TX#_13
CRT_R AE49 PEG_TXN14 C467 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N14 0 = No SDVO Device Present
15 CRT_R PEG_TX#_14
PEG_TX#_15
AH44 PEG_TXN15 C449 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_N15
PEG_NTX_GRX_P[0..15] 33
SDVO_CTRLDATA *
2

2
150_0402_1%

150_0402_1%

150_0402_1%

1 = SDVO Device Present

H32 M45 PEG_TXP0 C448 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P0
CRT_BLUE PEG_TX_0
R124

R117

R121

G32 T38 PEG_TXP1 C466 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P1

CRT_BLUE# PEG_TX_1
UMA@

K29 T46 PEG_TXP2 C484 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P2 0 = Normal Operation

UMA@

UMA@

J29
CRT_GREEN PEG_TX_2
N50 PEG_TXP3 C462 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P3 CFG19 (DMI Lane Reversal) (Lane number in Order) *
1

CRT_GREEN# PEG_TX_3 PEG_TXP4 C478 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P4

F29 R51 1 2
CRT_RED PEG_TX_4
VGA

E29 U43 PEG_TXP5 C460 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P5 1 = Reverse Lane

CRT_RED# PEG_TX_5 PEG_TXP6 C476 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P6
W42 1 2
PEG_TX_6 PEG_TXP7 C458 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P7
Y47 1 2
3VDDCCL PEG_TX_7 PEG_TXP8 C474 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P8
K33 Y39 1 2 0 = Only PCIE or SDVO is operational.
15 3VDDCCL
15 3VDDCDA
15 CRT_HSYNC
3VDDCDA
CRT_HSYNC
G35
F33
CRT_DDC_CLK
CRT_DDC_DATA
PEG_TX_8
PEG_TX_9
AC38
AD47
PEG_TXP9
PEG_TXP10
C456
C472
1
1
2
2
VGA@ 0.1U_0402_16V7K
VGA@ 0.1U_0402_16V7K
PEG_NTX_GRX_P9
PEG_NTX_GRX_P10
CFG20 (PCIE/SDVO concurrent)
1 = PCIE/SDVO are operating simu.
*
CRT_HSYNC PEG_TX_10 PEG_TXP11 C454 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P11
C32 AC50 1 2
CRT_VSYNC CRT_TVO_IREF PEG_TX_11 PEG_TXP12 C470 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P12
15 CRT_VSYNC E33 AD43 1 2
CRT_VSYNC PEG_TX_12 PEG_TXP13 C452 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P13
AG39 1 2
PEG_TX_13
1

AE50 PEG_TXP14 C468 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P14 R431 1 2 @ 4.02K_0402_1%

PEG_TX_14 7 CFG5
2

1.3K_0402_1%

AH43 PEG_TXP15 C450 1 2 VGA@ 0.1U_0402_16V7K PEG_NTX_GRX_P15

R457 PEG_TX_15
0_0402_5% 0_0402_5% R452 1
7 CFG7 2 @ 4.02K_0402_1%
B R382 R380 CRESTLINE_1p0 B
2

VGA@ VGA@
1

UMA@ R432 1 2 @ 4.02K_0402_1%

7 CFG8

R430 1 2 @ 4.02K_0402_1%
7 CFG9
For Crestline:1.3kohm
For Calero: 255ohm
R449 1 2 @ 4.02K_0402_1%
7 CFG12

R451 1 2 @ 4.02K_0402_1%
+3VS 7 CFG13
R124 R117 R121
R113 1 2 @ 4.02K_0402_1%
7 CFG16
R39 UMA@
1 2 GMCH_EDID_CLK_LCD CTRL_CLK

2.2K_0402_5% CFG[17:3] have internal pull up

CTRL_DATA 0_0402_5% 0_0402_5% 0_0402_5%
R38 UMA@ VGA@ VGA@ VGA@ CFG[19:18] have internal pull down
1 2 GMCH_EDID_DAT_LCD
2

2.2K_0402_5% +3VS
2

0_0402_5% 0_0402_5%
0_0402_5% 0_0402_5% R464 R456 R112
7 CFG19 1 2 @ 4.02K_0402_1%
R37 R40 VGA@ VGA@
1

VGA@ VGA@
1

R127 1 2 @ 4.02K_0402_1%
7 CFG20

A A

Note: CRT / TV-out should route to JP30 first then to the JP1 & JP2 on system side.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 9 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

+3VS VCCSYNC
+3VS_DAC_BG +3VS R109UMA@
2 1
2 1 0_0603_5% 1
UMA@

UMA@

UMA@
+1.25VS_DPLLB +1.25VS
0.022U_0402_16V7K~N

0.1U_0402_16V4Z~N

4.7U_ 0603_6.3V
L35 C248UMA@ +V1.25VS_AXF
10_0603_5%~D 0.1U_0402_16V4Z~N +VCCP UMA@
1 1 1 2
UMA@ 1 2 +1.25VS 1 2
C560

C574

C589

0.1U_0402_16V4Z~N

10U_0805_10V4Z~N
U3H L30

22U_0805_6.3VAM

1U_0603_10V4Z
10U_FLC-453232-100K_0.25A_10% R461
2 2 2 J32 U13 330U_V_2.5VM 0_0603_5%
VCCSYNC VTT_1 1 1 1 1

4.7U_ 0603_6.3V

C598

C570
U12 C546
VTT_2 C548
+3VS_DAC_CRT A33 U11 1 1
VCCA_CRT_DAC_1 VTT_3 UMA@
B33 U9
VCCA_CRT_DAC_2 VTT_4 + 2 2 UMA@ 2 2

C249
U8 C502
VTT_5

CRT
U7
VTT_6 2
D
+3VS_DAC_CRT +3VS_DAC_BG A30 U5 D
+3VS VCCA_DAC_BG VTT_7 2
U3
BLM18PG181SN1D_0603 VTT_8
B32 U2
VSSA_DAC_BG VTT_9
2 1 U1
VTT_10
0.022U_0402_16V7K~N

UMA@

UMA@

L33 UMA@ T13

VTT_11 +1.25VS_DMI +1.8V_SM_CK
0.1U_0402_16V4Z~N

VTT
+1.25VS_DPLLA B49 T11 +1.25VS +1.8V
VCCA_DPLLA VTT_12

0.47U_0603_10V7K

4.7U_ 0603_6.3V

2.2U_0805_16V4Z
1 1 T10 R379
VTT_13
+1.25VS_DPLLB H49 T9 1 1 1 1 2 1 2
VCCA_DPLLB VTT_14
C569

C568

C89 22U_0805_6.3V4Z

10U_0805_10V4Z
0_0805_5%

0.1U_0402_16V4Z~N
T7
VTT_15

0.1U_0402_16V4Z~N
PLL

C214

C259

C544
+1.25VM_HPLL AL2 T6 R397 1 1
2 2 VCCA_HPLL VTT_16 0_0603_5%
T5 1
+1.8V_TXLVDS VTT_17 2 2 2

C446

C443
+1.25VM_MPLL AM2 T3 1
VCCA_MPLL VTT_18

C512
T2
VTT_19 2 2
R3
VTT_20 2

A LVDS
A41 R2
VCCA_LVDS VTT_21 2
R1
VTT_22 +1.25VM_AXD
B41
VSSA_LVDS R93
+3VS_PEG_BG
AT23 1 2 +1.25VS
R404 VCC_AXD_1 0_0805_5%
AU28
VCC_AXD_2

1U_0603_10V4Z

10U_0805_10V4Z~N
+3VS 1 2 K50 AU24 1 1
VCCA_PEG_BG VCC_AXD_3 +1.25VS_PEGPLL

AXD

C153

C179
0_0805_5% AT29 +1.25VS
VCC_AXD_4 L28 +1.5VS_TVDAC +1.5VS
1 K49 AT25
VSSA_PEG_BG VCC_AXD_5

A PEG
AT30 BLM18PG121SN1D_0603 R96
C540 VCC_AXD_6 2 2 2 1 1 2
0.1U_0402_16V4Z~N 20 mils 0_0805_5%

0.022U_0402_16V7K~N

0.1U_0402_16V4Z~N
+1.25VS_PEGPLL U51 AR29
2 VCCA_PEG_PLL VCC_AXD_NCTF

0.1U_0402_16V4Z~N

10U_0805_10V4Z~N
1 1 1 1

C525

C524
AW18 B23 +V1.25VS_AXF
VCCA_SM_1 VCC_AXF_1

C245

C236
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2

AXF
AU19 A21
VCCA_SM_3 VCC_AXF_3 2 2 2 2
AU18
+1.25VM_A_SM VCCA_SM_4
AU17 AJ50 +1.25VS_DMI
R92 0317 change value VCCA_SM_5 VCC_DMI

A SM
+1.25VS 1 2 AT22
C
0_0805_5% 1 VCCA_SM_7 C
AT21 BK24 +1.8V_SM_CK
VCCA_SM_8 VCC_SM_CK_1
150U_Y_6.3VM

SM CK
1 1 1 AT19 BK23
VCCA_SM_9 VCC_SM_CK_2
C441

+ AT18 BJ24
C167 C156 C142 VCCA_SM_10 VCC_SM_CK_3
AT17 BJ23
22U_0805_6.3V4Z 4.7U_ 0603_6.3V VCCA_SM_11 VCC_SM_CK_4 +1.25VM_HPLL
AR17
2 2 2 2 VCCA_SM_NCTF_1 +1.25VS_DPLLA L4 +1.25VS
AR16 L34
1U_0603_10V4Z VCCA_SM_NCTF_2 UMA@
R88 +1.25VM_A_SM_CK
A43 +1.8V_TXLVDS 1 2 +1.25VS 2 1
VCC_TX_LVDS

A CK
2 1 BC29 MBK2012121YZF_0805

10U_0805_10V4Z~N
VCCA_SM_CK_1 +3VS_HV

220U_D2_4VM
0_0603_5% BB29 10U_FLC-453232-100K_0.25A_10%
22U_0805_6.3V4Z

0.1U_0402_16V4Z~N

1
1U_0402_6.3V4Z

VCCA_SM_CK_2
1U_0603_10V4Z

C40 1 1 1 1
VCC_HV_1
@ C135

@ C145

1 1 1 1 C25 B40 + C612 C565 C158 C171

+3VS_TVDACA VCCA_TVA_DAC_1 VCC_HV_2
C144

C138

HV
B25 UMA@ UMA@ C573
VCCA_TVA_DAC_2

0.1U_0402_16V4Z~N
C27
+3VS_TVDACB 0.1U_0402_16V4Z~N 10U_0603_6.3V~N
VCCA_TVB_DAC_1 2 2 2 2 2
B27 AD51 +VCC_PEG 1 UMA@
2 2 2 2 VCCA_TVB_DAC_2 VCC_PEG_1

C567
TV

+3VS_TVDACC B28 W50

VCCA_TVC_DAC_1 VCC_PEG_2

PEG
A28 W51
VGA@ R138 0_0402_5% VCCA_TVC_DAC_2 VCC_PEG_3 0.1U_0402_16V4Z~N
V49
VCC_PEG_4 2
2 1 V50
VCC_PEG_5
D TV/CRT

2 1 M32
R137 0_0402_5% UMA@ VCCD_CRT
+1.5VS_TVDAC L29
VCCD_TVDAC
AH50 +VCCP
VCC_RXR_DMI_1 +1.25VM_MPLL
DMI

+1.5VS_QDAC N28 AH51

VCCD_QDAC VCC_RXR_DMI_2 +VCC_PEG +1.25VS
20mils L5
+1.25VM_HPLL AN2 R401
VCCD_HPLL
A7 2 1 2 1
VTTLF1
VTTLF

+1.25VS_PEGPLL U48 F2 0_0805_5% MBK2012121YZF_0805

VCCD_PEG_PLL VTTLF2

10U_0805_10V4Z~N
AH1 1
VTTLF3

220U_D2_4VM
J41 1 1 1
VCCD_LVDS_1 0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

C507

C517
LVDS

H42 + C172 C192

+1.8V_LVDS VCCD_LVDS_2
1 1 1
C196

C263

C572
0.1U_0402_16V4Z~N 10U_0603_6.3V~N
2 2 2 2
+3VS_TVDACA +3VS CRESTLINE_1p0 UMA@
B
R460 2 2 2 B
2 1
0.022U_0402_16V7K~N

0_0603_5%
UMA@

UMA@
0.1U_0402_16V4Z~N

UMA@
1 1
C563

C577

+VCCP_D
2 2

D7 R462 R454
+VCCP 2 1 2 1 2 1 +3VS_HV
10_0402_5% 0_0402_5%
CH751H-40PT_SOD323-2
+3VS
+1.5VS_QDAC +1.5VS
+3VS_TVDACB +3VS R108
R459
2 1
1U_0402_6.3V4Z

2 1 100_0603_1%
0.022U_0402_16V7K~N

0.1U_0402_16V4Z~N

0_0603_5% UMA@
+1.8V_TXLVDS
UMA@

UMA@
0.1U_0402_16V4Z~N

UMA@ 1 1 40 mils C546 C560 C577 C575 C615 U3

1 1 R447 UMA@
C246

C231
C562

C576

1000P_0402_50V7K~N 2 1 +1.8V
2 2
UMA@

UMA@

0_0603_5%
2 2 UMA@ 1
220U_D2_4VM

1 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0603_5% CRESTLINE_1p0

C613

C566 + VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

2 UMA@ 2 C565 C569 C576 C231 C566 C248

+3VS_TVDACC +3VS +1.8V_LVDS

A R458 A
R478
2 1
0.022U_0402_16V7K~N

0_0603_5% 2 1 +1.8V 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

UMA@

UMA@
0.1U_0402_16V4Z~N

10U_0805_10V4Z~N

UMA@ 0_0603_5% VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

UMA@ C614

1U_0603_10V4Z
UMA@ C615

1 1 1 1 UMA@
C561

C575

2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(4/6)-PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 10 of 51
5 4 3 2 1
 5 4 3 2 1

+VCCP
U3G +VCCP

AT35
VCC_1 370mil
AT34 T17
VCC_2 VCC_AXG_NCTF_1
AH28 T18
VCC_3 VCC_AXG_NCTF_2 0.1U_0402_16V4Z~N 0.47U_0603_10V7K
AC32 T19
VCC_5 VCC_AXG_NCTF_3 UMA@ UMA@
AC31 T21
VCC_4 VCC_AXG_NCTF_4
AK32 T22 1 1
VCC_6 VCC_AXG_NCTF_5

1
AJ31 T23 C216 C225 C230
+VCCP VCC_7 VCC_AXG_NCTF_6
AJ28 T25
D U3F VCC_8 VCC_AXG_NCTF_7 D
AH32 U15

2
VCC_9 VCC_AXG_NCTF_8 2 2

VCC CORE
AH31 U16
VCC_10 VCC_AXG_NCTF_9
AB33 AH29 U17
VCC_NCTF_1 VCC_11 VCC_AXG_NCTF_10 0.22U_0402_10V4Z~N UMA@
AB36 AF32 U19
VCC_NCTF_2 VCC_12 VCC_AXG_NCTF_11
AB37 U20
VCC_NCTF_3 VCC_AXG_NCTF_12
AC33 T27 U21
VCC_NCTF_4 VSS_NCTF_1 R105 VCC_AXG_NCTF_13
AC35 T37 U23
VCC_NCTF_5 VSS_NCTF_2 VCC_AXG_NCTF_14
AC36 U24 1 2 R30 U26
VCC_NCTF_6 VSS_NCTF_3 0_0603_5% VCC_13 VCC_AXG_NCTF_15
AD35 U28 V16
VCC_NCTF_7 VSS_NCTF_4 VCC_AXG_NCTF_16
AD36 V31 V17
VCC_NCTF_8 VSS_NCTF_5 VCC_AXG_NCTF_17
AF33 V35 V19
VCC_NCTF_9 VSS_NCTF_6 VCC_AXG_NCTF_18
@

AF36 AA19 V20

VCC_NCTF_10 VSS_NCTF_7 VCC_AXG_NCTF_19
22U_0805_6.3V4Z

0.22U_0402_10V4Z~N

0.22U_0402_10V4Z~N

0.1U_0402_16V4Z~N

AH33 AB17 V21

VCC_NCTF_11 VSS_NCTF_8 VCC_AXG_NCTF_20

VSS NCTF
1 AH35 AB35 V23
VCC_NCTF_12 VSS_NCTF_9 VCC_AXG_NCTF_21
220U_D2_4VM

1 1 AH36 AD19 V24

VCC_NCTF_13 VSS_NCTF_10 VCC_AXG_NCTF_22
1

1
C516

C212

C200

C202

C159

+ AH37 AD37 Y15

AJ33
AJ35
VCC_NCTF_14
VCC_NCTF_15
VSS_NCTF_11
VSS_NCTF_12
AF17
AF35 +1.8V POWER VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
Y16
Y17
2

2 2 2 VCC_NCTF_16 VSS_NCTF_13 VCC_AXG_NCTF_25

AK33 AK17 AU32 Y19
VCC_NCTF_17 VSS_NCTF_14 160mil VCC_SM_1 VCC_AXG_NCTF_26
AK35 AM17 AU33 Y20
VCC_NCTF_18 VSS_NCTF_15 VCC_SM_2 VCC_AXG_NCTF_27
AK36 AM24 AU35 Y21
VCC_NCTF_19 VSS_NCTF_16 VCC_SM_3 VCC_AXG_NCTF_28
AK37 AP26 AV33 Y23
VCC_NCTF_20 VSS_NCTF_17 VCC_SM_4 VCC_AXG_NCTF_29

0.01U_0402_16V7K~N
330U_V_2.5VM
AD33 AP28 AW33 Y24
VCC_NCTF_21 VSS_NCTF_18 VCC_SM_5 VCC_AXG_NCTF_30

22U_0805_6.3V4Z

22U_0805_6.3V4Z
AJ36 AR15 1 AW35 Y26
VCC_NCTF_22 VSS_NCTF_19 VCC_SM_6 VCC_AXG_NCTF_31

VCC NCTF
AM35 AR19 1 1 2 AY35 Y28
VCC_NCTF_23 VSS_NCTF_20 VCC_SM_7 VCC_AXG_NCTF_32

C96

C117

C134
AL33 AR28 C74 + BA32 Y29
VCC_NCTF_24 VSS_NCTF_21 VCC_SM_8 VCC_AXG_NCTF_33
AL35 BA33 AA16
VCC_NCTF_25 VCC_SM_9 VCC_AXG_NCTF_34
AA33 BA35 AA17
VCC_NCTF_26 2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_35
AA35 BB33 AB16
VCC_NCTF_27 VCC_SM_11 VCC_AXG_NCTF_36
AA36 BC32 AB19
VCC_NCTF_28 VCC_SM_12 VCC_AXG_NCTF_37
AP35 BC33 AC16
VCC_NCTF_29 VCC_SM_13 VCC_AXG_NCTF_38
AP36 BC35 AC17
VCC_NCTF_30 VCC_SM_14 VCC_AXG_NCTF_39

VCC SM
C AR35 BD32 AC19 C
VCC_NCTF_31 VCC_SM_15 VCC_AXG_NCTF_40
AR36 BD35 AD15
VCC_NCTF_32 VCC_SM_16 VCC_AXG_NCTF_41
Y32 BE32 AD16
VCC_NCTF_33 VCC_SM_17 VCC_AXG_NCTF_42
Y33 BE33 AD17
VCC_NCTF_34
POWER VCC_SM_18 VCC_AXG_NCTF_43

VCC GFX NCTF

Y35 BE35 AF16
VCC_NCTF_35 VCC_SM_19 VCC_AXG_NCTF_44
Y36 BF33 AF19
VCC_NCTF_36 VCC_SM_20 VCC_AXG_NCTF_45
Y37 A3 BF34 AH15
VCC_NCTF_37 VSS_SCB1 VCC_SM_21 VCC_AXG_NCTF_46
T30 B2 BG32 AH16
VCC_NCTF_38 VSS_SCB2 VCC_SM_22 VCC_AXG_NCTF_47
VSS SCB
T34 C1 BG33 AH17
VCC_NCTF_39 VSS_SCB3 VCC_SM_23 VCC_AXG_NCTF_48
T35 BL1 BG35 AH19
VCC_NCTF_40 VSS_SCB4 VCC_SM_24 VCC_AXG_NCTF_49
U29 BL51 BH32 AJ16
VCC_NCTF_41 VSS_SCB5 VCC_SM_25 VCC_AXG_NCTF_50
U31 A51 BH34 AJ17
VCC_NCTF_42 VSS_SCB6 VCC_SM_26 VCC_AXG_NCTF_51
U32 BH35 AJ19
VCC_NCTF_43 VCC_SM_27 VCC_AXG_NCTF_52
U33 BJ32 AK16
VCC_NCTF_44 VCC_SM_28 VCC_AXG_NCTF_53
U35 BJ33 AK19
VCC_NCTF_45 VCC_SM_29 VCC_AXG_NCTF_54
U36 BJ34 AL16
VCC_NCTF_46 VCC_SM_30 VCC_AXG_NCTF_55
V32 BK32 AL17
VCC_NCTF_47 VCC_SM_31 VCC_AXG_NCTF_56
V33 BK33 AL19
VCC_NCTF_48 VCC_SM_32 VCC_AXG_NCTF_57
V36 BK34 AL20
VCC_NCTF_49 VCC_SM_33 VCC_AXG_NCTF_58
V37 BK35 AL21
VCC_NCTF_50 VCC_SM_34 VCC_AXG_NCTF_59
BL33 AL23
VCC_SM_35 VCC_AXG_NCTF_60
AT33 +VCCP AU30 AM15
VCC_AXM_1 VCC_SM_36 VCC_AXG_NCTF_61
AT31 AM16
VCC_AXM_2 VCC_AXG_NCTF_62
VCC AXM

+VCCP AK29 AM19

VCC_AXM_3 +VCCP VCC_AXG_NCTF_63
AK24 AM20
VCC_AXM_4 VCC_AXG_NCTF_64
10U_0805_10V4Z~N

10U_0805_10V4Z~N

AK23 AM21
VCC_AXM_5 VCC_AXG_NCTF_65
1 1 AL24 AJ26 R20 AM23
VCC_AXM_NCTF_1 VCC_AXM_6 VCC_AXG_1 VCC_AXG_NCTF_66
C177

C178

AL26 AJ23 T14 AP15

VCC_AXM_NCTF_2 VCC_AXM_7 VCC_AXG_2 VCC_AXG_NCTF_67
AL28 W13 AP16
VCC_AXM_NCTF_3 VCC_AXG_3 VCC_AXG_NCTF_68
AM26 W14 AP17
2 2 VCC_AXM_NCTF_4 VCC_AXG_4 VCC_AXG_NCTF_69
VCC AXM NCTF

AM28 UMA@ Y12 AP19

VCC_AXM_NCTF_5 10U_0603_6.3V~N 0.1U_0402_16V4Z~N VCC_AXG_5 VCC_AXG_NCTF_70
AM29 AA20 AP20
B VCC_AXM_NCTF_6 UMA@ VCC_AXG_6 VCC_AXG_NCTF_71 B
AM31 AA23 AP21
VCC_AXM_NCTF_7 VCC_AXG_7 VCC_AXG_NCTF_72
AM32 1 AA26 AP23
VCC_AXM_NCTF_8 VCC_AXG_8 VCC_AXG_NCTF_73
AM33 1 1 1 1 AA28 AP24
VCC_AXM_NCTF_9 UMA@ C199 C527 + C247 C213 C209 VCC_AXG_9 VCC_AXG_NCTF_74
AP29 AB21 AR20
VCC_AXM_NCTF_10 VCC_AXG_10 VCC_AXG_NCTF_75
AP31 AB24 AR21
VCC_AXM_NCTF_11 1U_0603_10V4Z VCC_AXG_11 VCC_AXG_NCTF_76
AP32 AB29 AR23
VCC_AXM_NCTF_12 2 2 2 2 2 VCC_AXG_12 VCC_AXG_NCTF_77
AP33 AC20 AR24
VCC_AXM_NCTF_13 VCC_AXG_13 VCC_AXG_NCTF_78

VCC GFX
AL29 AC21 AR26
VCC_AXM_NCTF_14 UMA@ 330U_V_2.5VM UMA@ 10U_0805_10V4Z~N VCC_AXG_14 VCC_AXG_NCTF_79
AL31 AC23 V26
VCC_AXM_NCTF_15 VCC_AXG_15 VCC_AXG_NCTF_80
AL32 AC24 V28
VCC_AXM_NCTF_16 VCC_AXG_16 VCC_AXG_NCTF_81
AR31 AC26 V29
VCC_AXM_NCTF_17 VCC_AXG_17 VCC_AXG_NCTF_82
AR32 AC28 Y31
VCC_AXM_NCTF_18 VCC_AXG_18 VCC_AXG_NCTF_83
0.22U_0402_10V4Z~N

0.22U_0402_10V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

AR33 AC29
VCC_AXM_NCTF_19 VCC_AXG_19
1 1 1 AD20
VCC_AXG_20
1

1
C152

C160

C151

C185

C174

AD23
VCC_AXG_21
AD24 AW45 VCCSM_LF1
VCC_AXG_22 VCC_SM_LF1
AD28 BC39 VCCSM_LF2
2

2 2 2 VCC_AXG_23 VCC_SM_LF2

VCC SM LF
CRESTLINE_1p0 UMA@ AF21 BE39 VCCSM_LF3
VCC_AXG_24 VCC_SM_LF3
AF26 BD17 VCCSM_LF4
VCC_AXG_25 VCC_SM_LF4
AA31 BD4 VCCSM_LF5
VCC_AXG_26 VCC_SM_LF5
AH20 AW8 VCCSM_LF6
VCC_AXG_27 VCC_SM_LF6
AH21 AT6 VCCSM_LF7
VCC_AXG_28 VCC_SM_LF7

C148

C141

C140

C133

C127

C137

C143
AH23 1 1 1 1 1 1 1
VCC_AXG_29
AH24
VCC_AXG_30
AH26
VCC_AXG_31

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N

0.22U_0603_10V7K~N

0.22U_0603_10V7K~N

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
AD31
VCC_AXG_32 2 2 2 2 2 2 2
AJ20
VCC_AXG_33
AN14
VCC_AXG_34

A A

CRESTLINE_1p0 UMA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 11 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

U3I

A13 AW24
VSS_1 VSS_100
A15 AW29
VSS_2 VSS_101
A17 AW32
VSS_3 VSS_102
A24 AW5
VSS_4 VSS_103
AA21 AW7
VSS_5 VSS_104
AA24 AY10
VSS_6 VSS_105
AA29 AY24
VSS_7 VSS_106 U3J
AB20 AY37
D VSS_8 VSS_107 D
AB23 AY42 C46 W11
VSS_9 VSS_108 VSS_199 VSS_287
AB26 AY43 C50 W39
VSS_10 VSS_109 VSS_200 VSS_288
AB28 AY45 C7 W43
VSS_11 VSS_110 VSS_201 VSS_289
AB31 AY47 D13 W47
VSS_12 VSS_111 VSS_202 VSS_290
AC10 AY50 D24 W5
VSS_13 VSS_112 VSS_203 VSS_291
AC13 B10 D3 W7
VSS_14 VSS_113 VSS_204 VSS_292
AC3 B20 D32 Y13
VSS_15 VSS_114 VSS_205 VSS_293
AC39 B24 D39 Y2
VSS_16 VSS_115 VSS_206 VSS_294
AC43 B29 D45 Y41
VSS_17 VSS_116 VSS_207 VSS_295
AC47 B30 D49 Y45
VSS_18 VSS_117 VSS_208 VSS_296
AD1 B35 E10 Y49
VSS_19 VSS_118 VSS_209 VSS_297
AD21 B38 E16 Y5
VSS_20 VSS_119 VSS_210 VSS_298
AD26 B43 E24 Y50
VSS_21 VSS_120 VSS_211 VSS_299
AD29 B46 E28 Y11
VSS_22 VSS_121 VSS_212 VSS_300
AD3 B5 E32 P29
VSS_23 VSS_122 VSS_213 VSS_301
AD41 B8 E47 T29
VSS_24 VSS_123 VSS_214 VSS_302
AD45 BA1 F19 T31
VSS_25 VSS_124 VSS_215 VSS_303
AD49 BA17 F36 T33
VSS_26 VSS_125 VSS_216 VSS_304
AD5 BA18 F4 R28
VSS_27 VSS_126 VSS_217 VSS_305
AD50 BA2 F40
VSS_28 VSS_127 VSS_218
AD8 BA24 F50
VSS_29 VSS_128 VSS_219
AE10 BB12 G1
VSS_30 VSS_129 VSS_220
AE14 BB25 G13 AA32
VSS_31 VSS_130 VSS_221 VSS_306
AE6 BB40 G16 AB32
VSS_32 VSS_131 VSS_222 VSS_307
AF20 BB44 G19 AD32
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
G24
G28
VSS_223
VSS_224
VSS_225
VSS_308
VSS_309
VSS_310
AF28
AF29
AF31 BC16 G29 AT27
VSS_36 VSS_135 VSS_226 VSS_311
AG2 BC24 G33 AV25
VSS_37 VSS_136 VSS_227 VSS_312
AG38 BC25 G42 H50
VSS_38 VSS_137 VSS_228 VSS_313
AG43 BC36 G45
VSS_39 VSS_138 VSS_229
AG47 BC40 G48
C VSS_40 VSS_139 VSS_230 C
AG50 BC51 G8
VSS_41 VSS_140 VSS_231
AH3 BD13 H24
VSS_42 VSS_141 VSS_232
AH40 BD2 H28
VSS_43 VSS_142 VSS_233
AH41 BD28 H4
VSS_44 VSS_143 VSS_234
AH7 BD45 H45
VSS_45 VSS_144 VSS_235
AH9 BD48 J11
VSS_46 VSS_145 VSS_236
AJ11 BD5 J16
VSS_47 VSS_146 VSS_237
AJ13 BE1 J2
VSS_48 VSS_147 VSS_238
AJ21 BE19 J24
VSS_49 VSS_148 VSS_239
AJ24 BE23 J28
VSS_50 VSS_149 VSS_240
AJ29 BE30 J33
AJ32
AJ43
VSS_51
VSS_52
VSS_53
VSS_150
VSS_151
VSS_152
BE42
BE51
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AJ45 BE8
VSS_54 VSS_153
AJ49 BF12 K12
VSS_55 VSS_154 VSS_245
AK20 BF16 K47
VSS_56 VSS_155 VSS_246
AK21 BF36 K8
VSS_57 VSS_156 VSS_247
AK26 BG19 L1
VSS_58 VSS_157 VSS_248
AK28 BG2 L17
VSS_59 VSS_158 VSS_249
AK31 BG24 L20
VSS_60 VSS_159 VSS_250
AK51 BG29 L24
VSS_61 VSS_160 VSS_251
AL1 BG39 L28
VSS_62 VSS_161 VSS_252
AM11 BG48 L3
VSS_63 VSS_162 VSS_253
AM13 BG5 L33
VSS_64 VSS_163 VSS_254
AM3 BG51 L49
VSS_65 VSS_164 VSS_255
AM4 BH17 M28
VSS_66 VSS_165 VSS_256
AM41 BH30 M42
VSS_67 VSS_166 VSS_257
AM45 BH44 M46
VSS_68 VSS_167 VSS_258
AN1 BH46 M49
VSS_69 VSS_168 VSS_259
AN38 BH8 M5
VSS_70 VSS_169 VSS_260
AN39 BJ11 M50
VSS_71 VSS_170 VSS_261
AN43 BJ13 M9
B VSS_72 VSS_171 VSS_262 B
AN5 BJ38 N11
VSS_73 VSS_172 VSS_263
AN7 BJ4 N14
VSS_74 VSS_173 VSS_264
AP4 BJ42 N17
VSS_75 VSS_174 VSS_265
AP48 BJ46 N29
VSS_76 VSS_175 VSS_266
AP50 BK15 N32
VSS_77 VSS_176 VSS_267
AR11 BK17 N36
VSS_78 VSS_177 VSS_268
AR2 BK25 N39
VSS_79 VSS_178 VSS_269
AR39 BK29 N44
VSS_80 VSS_179 VSS_270
AR44 BK36 N49
VSS_81 VSS_180 VSS_271
AR47 BK40 N7
VSS_82 VSS_181 VSS_272
AR7 BK44 P19
VSS_83 VSS_182 VSS_273
AT10 BK6 P2
VSS_84 VSS_183 VSS_274
AT14 BK8 P23
VSS_85 VSS_184 VSS_275
AT41 BL11 P3
VSS_86 VSS_185 VSS_276
AT49 BL13 P50
VSS_87 VSS_186 VSS_277
AU1 BL19 R49
VSS_88 VSS_187 VSS_278
AU23 BL22 T39
VSS_89 VSS_188 VSS_279
AU29 BL37 T43
VSS_90 VSS_189 VSS_280
AU3 BL47 T47
VSS_91 VSS_190 VSS_281
AU36 C12 U41
VSS_92 VSS_191 VSS_282
AU49 C16 U45
VSS_93 VSS_192 VSS_283
AU51 C19 U50
VSS_94 VSS_193 VSS_284
AV39 C28 V2
VSS_95 VSS_194 VSS_285
AV48 C29 V3
VSS_96 VSS_195 VSS_286
AW1 C33
VSS_97 VSS_196
AW12 C36
VSS_98 VSS_197 CRESTLINE_1p0 UMA@
AW16 C41
VSS_99 VSS_198

CRESTLINE_1p0 UMA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 12 of 51
5 4 3 2 1
 5 4 3 2 1

Close to VREF pins of SO-DIMM

+1.8V
+DDR_MCH_REF1
8 DDR_A_DQS#[0..7]
Layout Note:
JDIM1
8 DDR_A_D[0..63] +DDR_MCH_REF +1.8V

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
trace width and 3 4 DDR_A_D6 1 1
8 DDR_A_DM[0..7] VSS DQ4

C72

C67
spacing is 20/20. DDR_A_D4 5 6 DDR_A_D0
DQ0 DQ5

1
DDR_A_D1 7 8
8 DDR_A_DQS[0..7] DQ1 VSS
R58 9 10 DDR_A_DM0
1K_0402_1% DDR_A_DQS#0 VSS DM0 2 2
8 DDR_A_MA[0..13] 11 12
DDR_A_DQS0 DQS0# VSS DDR_A_D5
13 DQS0 DQ6 14
15 16 DDR_A_D7

2
+DDR_MCH_REF1 DDR_A_D2 VSS DQ7
14 +DDR_MCH_REF1 17 18
DDR_A_D3 DQ2 VSS DDR_A_D13

0.1U_0402_16V4Z~N
19 DQ3 DQ12 20

1
D DDR_A_D12 D
21 22
R59 DDR_A_D8 VSS DQ13
1 23 24
1K_0402_1% DDR_A_D14 DQ8 VSS DDR_A_DM1
Layout Note: 25 DQ9 DM1 26

C58
27 28
Place near JDIM1 DDR_A_DQS#1 29
VSS VSS
30 M_CLK_DDR0

2
2 DQS1# CK0 M_CLK_DDR0 7
DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 7
33 34
DDR_A_D9 VSS VSS DDR_A_D11
close to connector 35
DQ10 DQ14
36
DDR_A_D15 37 38 DDR_A_D10
DQ11 DQ15
39 40
VSS VSS

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 44
DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 46
DQ17 DQ21
47 48

330U_D2E_2.5VM_R7
VSS VSS
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_A_DQS#2 49 50
DDR_A_DQS2 DQS2# NC DDR_A_DM2 PM_EXTTS#0 7
1 1 1 1 1 1 1 1 1 51 52
DQS2 DM2
C50

C436

C435

C437

C51

C54

C434

C433

C55

C75
+ 53 54
DDR_A_D18 VSS VSS DDR_A_D23
55 DQ18 DQ22 56
DDR_A_D19 57 58 DDR_A_D22
2 2 2 2 2 2 2 2 2 2 DQ19 DQ23
59 60
DDR_A_D29 VSS VSS DDR_A_D28
61 DQ24 DQ28 62
DDR_A_D24 63 64 DDR_A_D25
DQ25 DQ29
65 66
DDR_A_DM3 VSS VSS DDR_A_DQS#3
67 DM3 DQS3# 68
69 70 DDR_A_DQS3
NC DQS3
71 72
DDR_A_D26 VSS VSS DDR_A_D31
73 DQ26 DQ30 74
DDR_A_D27 75 76 DDR_A_D30
DQ27 DQ31
Layout Note: DDR_CKE0_DIMMA
77
VSS VSS
78
DDR_CKE1_DIMMA
7 DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA 7
C Place one cap close to every 2 pullup 81
CKE0 NC/CKE1
82 C
VDD VDD
resistors terminated to +0.9V DDR_A_BS#2
83
NC NC/A15
84
DDR_A_MA14
8 DDR_A_BS#2 85 BA2 NC/A14 86 DDR_A_MA14 7
87 88
DDR_A_MA12 VDD VDD DDR_A_MA11
89 90
DDR_A_MA9 A12 A11 DDR_A_MA7
91 92
DDR_A_MA8 A9 A7 DDR_A_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 100
DDR_A_MA1 A3 A2 DDR_A_MA0
101 A1 A0 102
103 104
DDR_A_MA10 VDD VDD DDR_A_BS#1
105 106 DDR_A_BS#1 8
DDR_A_BS#0 A10/AP BA1 DDR_A_RAS#
8 DDR_A_BS#0 107 BA0 RAS# 108 DDR_A_RAS# 8
+0.9VS DDR_A_WE# 109 110 DDR_CS0_DIMMA#
8 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
111 112
DDR_A_CAS# VDD VDD M_ODT0
8 DDR_A_CAS# 113 CAS# ODT0 114 M_ODT0 7
DDR_A_V DDR_CS1_DIMMA# 115 116 DDR_A_MA13
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 118
VDD VDD
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

7 M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 122
DDR_A_D37 VSS VSS DDR_A_D32
1 1 1 1 1 1 1 1 1 1 1 1 1 123 124
DDR_A_D36 DQ32 DQ36 DDR_A_D33
125 DQ33 DQ37 126
127 128
DDR_A_DQS#4 VSS VSS DDR_A_DM4
129 130
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C70

C68

C52

C69

C71

C59

C65

C62

C64

C53

C60

C63

C66

133 134 DDR_A_D39

DDR_A_D35 VSS DQ38 DDR_A_D38
135 136
DDR_A_D34 DQ34 DQ39
137 138
DQ35 VSS DDR_A_D45
139 140
DDR_A_D40 VSS DQ44 DDR_A_D43
141 142
DDR_A_D44 DQ40 DQ45
143 144
B DQ41 VSS DDR_A_DQS#5 B
145 146
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 150
DDR_A_D41 VSS VSS DDR_A_D47
151 152
DDR_A_D46 DQ42 DQ46 DDR_A_D42
Layout Note: 153 DQ43 DQ47 154
Place these resistor 155 156
DDR_A_V

DDR_A_D49 VSS VSS DDR_A_D52

157 158
closely JP41,all DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
trace length Max=1.5" 161 162
56_0404_4P2R_5% VSS VSS M_CLK_DDR1
RP26 163 164 M_CLK_DDR1 7
RP27 NC,TEST CK1 M_CLK_DDR#1
165 VSS CK1# 166 M_CLK_DDR#1 7
DDR_A_MA8 3 2 2 3 DDR_CKE0_DIMMA DDR_A_DQS#6 167 168
DDR_A_MA5 DDR_A_MA12 DDR_A_DQS6 DQS6# VSS DDR_A_DM6
4 1 1 4 169 170
DQS6 DM6
171 VSS VSS 172
RP24 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DDR_A_D54 173 174 DDR_A_D51
DDR_A_MA1 DQ50 DQ54
1 4 4 1 DDR_A_MA7 DDR_A_D50 175 176 DDR_A_D55
DDR_A_MA3 DQ51 DQ55
2 3 3 2 DDR_A_MA6 177 VSS VSS 178
DDR_A_D61 179 180 DDR_A_D57
RP16 56_0404_4P2R_5% RP25 56_0404_4P2R_5% DDR_A_D60 DQ56 DQ60 DDR_A_D56
181 182
DDR_A_RAS# DQ57 DQ61
1 4 2 3 DDR_A_BS#2 183 VSS VSS 184
DDR_CS0_DIMMA# 2 3 1 4 DDR_A_MA9 DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 188
RP2356_0404_4P2R_5% RP18 56_0404_4P2R_5% DDR_A_D59 VSS DQS7
189 190
DDR_A_BS#0 DQ58 VSS
3 2 4 1 DDR_A_MA2 DDR_A_D58 191 192 DDR_A_D62
DDR_A_MA10 DQ59 DQ62
4 1 3 2 DDR_A_MA4 193 194 DDR_A_D63
ICH_SM_DA VSS DQ63
14,16,19 ICH_SM_DA 195 196
RP22 56_0404_4P2R_5% RP17 56_0404_4P2R_5% ICH_SM_CLK SDA VSS
14,16,19 ICH_SM_CLK 197 198
DDR_A_CAS# SCL SA0
1 4 4 1 DDR_A_BS#1 +3VS 199 VDDSPD SA1 200
DDR_A_WE# 2 3 3 2 DDR_A_MA0 1

1
10K_0402_5%

10K_0402_5%
1 1
RP21 56_0404_4P2R_5% RP15 56_0404_4P2R_5% C61 C73 FOX_ASOA426-M2RN-7F
R56

R57
DDR_CS1_DIMMA# 4 1 4 1 M_ODT0
A M_ODT1 3 2 3 2 DDR_A_MA13 0.1U_0402_16V4Z
2 2
2.2U_0603_6.3V6K SO-DIMM A A

REVERSE
2

2
56_0404_4P2R_5% RP20 56_0404_4P2R_5%
DDR_CKE1_DIMMA 1 2 4 1 DDR_A_MA11
R55 56_0402_5% 3 2 DDR_A_MA14
Bottom side
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR2 SO-DIMM I
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 13 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

8 DDR_B_DQS#[0..7] Close to VREF pins of SO-DIMM

+1.8V
8 DDR_B_D[0..63]
+DDR_MCH_REF1
+DDR_MCH_REF1 13
8 DDR_B_DM[0..7] JDIM2

2.2U_0805_16V4Z

0.1U_0402_16V4Z
8 DDR_B_DQS[0..7] 1 2
VREF VSS DDR_B_D5
3 4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
8 DDR_B_MA[0..13] 5 6
DQ0 DQ5

C39

C49
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 10
DDR_B_DQS#0 VSS DM0 2 2
11 12
DDR_B_DQS0 DQS0# VSS DDR_B_D6
13 14
DQS0 DQ6 DDR_B_D7
15 16
DDR_B_D2 VSS DQ7
17 18
D DDR_B_D3 DQ2 VSS DDR_B_D12 D
Layout Note: 19
DQ3 DQ12
20
DDR_B_D13
21 22
Place near JDIM2 DDR_B_D8 VSS DQ13
23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 26
DQ9 DM1
27 28
DDR_B_DQS#1 VSS VSS M_CLK_DDR2
29 30 M_CLK_DDR2 7
DDR_B_DQS1 DQS1# CK0 M_CLK_DDR#2
31 32 M_CLK_DDR#2 7
DQS1 CK0#
33 34
DDR_B_D10 VSS VSS DDR_B_D14
35 36
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 38
+1.8V DQ11 DQ15
39 40
VSS VSS

41 42

330U_D2E_2.5VM_R7
VSS VSS
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 46
DQ17 DQ21
C25

C28

C29

C27

C24

C57

C42

C26

C56
+

C79
47 48
DDR_B_DQS#2 VSS VSS
49 50 PM_EXTTS#1 7
DDR_B_DQS2 DQS2# NC DDR_B_DM2
@ 51 52
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 54
DDR_B_D18 VSS VSS DDR_B_D22
55 56
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 58
DQ19 DQ23
59 60
DDR_B_D28 VSS VSS DDR_B_D26
61 62
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 64
DQ25 DQ29
65 66
DDR_B_DM3 VSS VSS DDR_B_DQS#3
67 68
DM3 DQS3# DDR_B_DQS3
69 70
NC DQS3
Layout Note: DDR_B_D30
71
VSS VSS
72
DDR_B_D29
73 74
Place one cap close to every 2 pullup DDR_B_D31 75
DQ26 DQ30
76 DDR_B_D27
DQ27 DQ31
C
resistors terminated to +0.9VS DDR_CKE2_DIMMB
77
VSS VSS
78
DDR_CKE3_DIMMB C
7 DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB 7
CKE0 NC/CKE1
81 82
VDD VDD
83 84
DDR_B_BS#2 NC NC/A15 DDR_B_MA14
8 DDR_B_BS#2 85 86 DDR_B_MA14 7
BA2 NC/A14
87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
89 90
DDR_B_MA9 A12 A11 DDR_B_MA7
91 92
DDR_B_MA8 A9 A7 DDR_B_MA6
93 94
A8 A6
95 96
DDR_B_MA5 VDD VDD DDR_B_MA4
97 98
DDR_B_MA3 A5 A4 DDR_B_MA2
99 100
DDR_B_MA1 A3 A2 DDR_B_MA0
101 102
+0.9VS A1 A0
103 104
DDR_B_MA10 VDD VDD DDR_B_BS#1
105 106 DDR_B_BS#1 8
DDR_B_BS#0 A10/AP BA1 DDR_B_RAS#
8 DDR_B_BS#0 107 108 DDR_B_RAS# 8
DDR_B_WE# BA0 RAS# DDR_CS2_DIMMB#
8 DDR_B_WE# 109 110 DDR_CS2_DIMMB# 7
DDR_B_V WE# S0#
111 112
DDR_B_CAS# VDD VDD M_ODT2
8 DDR_B_CAS# 113 114 M_ODT2 7
CAS# ODT0
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

7 DDR_CS3_DIMMB# NC/S1# NC/A13
117 118
M_ODT3 VDD VDD
1 1 1 1 1 1 1 1 1 1 1 1 1 7 M_ODT3 119 120
NC/ODT1 NC
121 122
DDR_B_D32 VSS VSS DDR_B_D36
123 124
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 126
2 2 2 2 2 2 2 2 2 2 2 2 2 DQ33 DQ37
127 128
VSS VSS
C33

C32

C30

C44

C36

C46

C31

C37

C45

C41

C40

C34

C35

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 132
DQS4 VSS DDR_B_D39
133 134
DDR_B_D34 VSS DQ38 DDR_B_D38
135 136
DDR_B_D35 DQ34 DQ39
137 138
DQ35 VSS DDR_B_D44
139 140
DDR_B_D40 VSS DQ44 DDR_B_D45
141 142
B DDR_B_D41 DQ40 DQ45 B
143 144
DQ41 VSS DDR_B_DQS#5
145 146
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
Layout Note: 147
DM5 DQS5
148
Place these resistor 149 150
DDR_B_D42 VSS VSS DDR_B_D46
151 152
closely JP42,all DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 154
trace length Max=1.5" DQ43 DQ47
155 156
DDR_B_D48 VSS VSS DDR_B_D52
157 158
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 160
DQ49 DQ53
161 162
VSS VSS M_CLK_DDR3
163 164 M_CLK_DDR3 7
NC,TEST CK1 M_CLK_DDR#3
165 166 M_CLK_DDR#3 7
DDR_B_DQS#6 VSS CK1#
167 168
DQS6# VSS
DDR_B_V

DDR_B_DQS6 169 170 DDR_B_DM6

DQS6 DM6
171 172
DDR_B_D51 VSS VSS DDR_B_D54
173 174
RP14 RP6 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 176
DDR_B_MA14 DDR_B_MA7 DQ51 DQ55
3 2 4 1 177 178
DDR_B_MA11 DDR_B_MA9 DDR_B_D56 VSS VSS DDR_B_D60
4 1 3 2 179 180
DDR_B_D61 DQ56 DQ60 DDR_B_D57
181 182
RP12 56_0404_4P2R_5% RP5 56_0404_4P2R_5% DQ57 DQ61
183 184
DDR_B_MA8 DDR_B_MA3 DDR_B_DM7 VSS VSS DDR_B_DQS#7
3 2 4 1 185 186
DDR_B_MA5 DDR_B_MA1 DM7 DQS7# DDR_B_DQS7
4 1 3 2 187 188
DDR_B_D59 VSS DQS7
189 190
RP3 56_0404_4P2R_5% RP13 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 192
DDR_B_RAS# DDR_B_MA12 DQ59 DQ62 DDR_B_D63
1 4 2 3 193 194
DDR_B_BS#1 DDR_B_MA6 ICH_SM_DA VSS DQ63
2 3 1 4 13,16,19 ICH_SM_DA 195 196
ICH_SM_CLK SDA VSS R44
13,16,19 ICH_SM_CLK 197 198
RP9 56_0404_4P2R_5% RP4 56_0404_4P2R_5% SCL SAO
+3VS 199 200 1 2 +3VS
DDR_B_CAS# DDR_B_MA0 VDDSPD SA1
3 2 4 1

1
10K_0402_5%
DDR_CS2_DIMMB# 4 1 3 2 DDR_B_MA4 1 1 10K_0402_5%

R45
C43 C38 FOX_AS0A426-NARN-7F~N
A RP10 56_0404_4P2R_5% RP11 56_0404_4P2R_5% A
DDR_B_WE#
DDR_B_BS#0
3
4
2
1
2
1
3
4
DDR_B_MA2
DDR_B_MA10
0.1U_0402_16V4Z
2 2
2.2U_0603_6.3V6K SO-DIMM B
REVERSE
2

RP8 56_0404_4P2R_5% RP2 56_0404_4P2R_5%

DDR_CS3_DIMMB# 4 1 4 1 M_ODT2 Bottom side
M_ODT3 3 2 3 2 DDR_B_MA13

56_0404_4P2R_5% RP7
DDR_CKE2_DIMMB
Security Classification Compal Secret Data Compal Electronics, Inc.
4 1 Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title
DDR_CKE3_DIMMB 1 2 3 2 DDR_B_BS#2
R49 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR2 SO-DIMM II
56_0404_4P2R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 14 of 51
5 4 3 2 1
 A B C D E

+5VS +CRT_VCC

CRT D17
@ DAN217_SC59
D16
@ DAN217_SC59 F1
W=40mils
D19 W=40mils +CRT_VCC +CRT_VCC +3VS +3VS +3VS
1 2 2 1

1
VGA@ 1.1A_6VDC_FUSE RB411DT146 SOT23 原原原4.7K 原原原10K

2
33 VGA_CRT_R 2 1 1 1
R47 0_0402_5% R3 R6 R22 R25 R23

2K_0402_5%

2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
0.1U_0402_16V4Z
VGA@ D15 C6

C401
2 1 @ DAN217_SC59 0.1U_0402_16V4Z
33 VGA_CRT_G

3
R46 0_0402_5% 2 2
+3VS

1
VGA@ @
33 VGA_CRT_B 2 1

2
R48 0_0402_5%

G
28 MSEN#
UMA@
9 3VDDCDA
1 UMA@ JCRT1 VGA_DDC_DATA_C 1 3 2 1 1
2 1 CRT_R_C 1 2 CRT_R_L 6 R27 0_0402_5%

S
9 CRT_R

2
R376 0_0402_5% L21 Q3

G
11
UMA@ BK1608LL121-T 0603 1 16 BSS138_NL_SOT23 UMA@
9 3VDDCCL
2 1 CRT_G_C 1 2 CRT_G_L 7 17 VGA_DDC_CLK_C 1 3 2 1
9 CRT_G
R374 0_0402_5% L20 12 R20 0_0402_5%

S
UMA@ BK1608LL121-T 0603 2
2 1 CRT_B_C 1 2 CRT_B_L 8
9 CRT_B Q2
R375 0_0402_5% L19 13 VGA@
33 VGA_DDCDATA

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
BSS138_NL_SOT23
1 BK1608LL121-T 0603
150_0402_1%

150_0402_1%

150_0402_1%
1 1 3 2 1
1

1
@ @ @ 1 1 1 DDC_MD2 9 R26 0_0402_5%
C398 C399 C400 For EMI VGA@
R333

R332

R331
14
C3 C1 C2 4 2 1
2 2 2 R19 0_0402_5%
10
2 2 2
15 33 VGA_DDCCLK
2

2
1 5
4.7P_0402_50V8C 4.7P_0402_50V8C 4.7P_0402_50V8C C7

100P_0402_50V8J
SUYIN_070549FR015S208CR
+CRT_VCC HSYNC_L
1 2 CONN@
R324 0_0603_5% 2
1 2 2 1 1 VGA_DDC_DATA_C
C402 0.1U_0402_16V4Z R336 10K_0402_5% 1 2 VSYNC_L C385
R323 0_0603_5% 1
5
1

100P_0402_50V8J

100P_0402_50V8J
UMA@ 2
1 1
OE#
P

CRT_HSYNC 1 2CRT_HSYNC_B 2 4 D_CRT_HSYNC C4 VGA_DDC_CLK_C

9 CRT_HSYNC A Y 2
R119 30_0402_5% C384 C383
G

U4

15P_0402_50V8J

15P_0402_50V8J
VGA@ 74AHCT1G125GW_SOT353-5 2 2
3

33 VGA_HSYNC 2 1 1
R391 0_0402_5% +CRT_VCC
VGA@

100P_0402_50V8J
2 2 1 1 2 C8 2
33 VGA_VSYNC 2
R393 0_0402_5% C5 0.1U_0402_16V4Z
5
1

UMA@
OE#
P

CRT_VSYNC 1 2CRT_VSYNC_B 2 4 D_CRT_VSYNC

9 CRT_VSYNC A Y
R120 30_0402_5%
G

74AHCT1G125GW_SOT353-5 U5
3

Close to GMCH Close to VGA

LVDSAC+ UMA@ R371 1 2 0_0402_5% GMCH_LVDSAC+

LCD +3VS R41 1 2 47K_0402_5% LVDSAC- UMA@ R369 1 2 0_0402_5% GMCH_LVDSAC- GMCH_LVDSAC+
GMCH_LVDSAC-
9
9
JP4 LVDSA0+ UMA@ R367 1 2 0_0402_5% GMCH_LVDSA0+
LCD_DET# 1 2 BIST LVDSA0- UMA@ R365 1 2 0_0402_5% GMCH_LVDSA0- GMCH_LVDSA0+ 9
28 LCD_DET# 1 2 BIST 28 GMCH_LVDSA0- 9
3 4
3 4 LVDSAC+ LVDSA1+ UMA@ R363 0_0402_5% GMCH_LVDSA1+
5 6 1 2
5 6 LVDSAC- LVDSA1- UMA@ R359 0_0402_5% GMCH_LVDSA1- GMCH_LVDSA1+ 9
+LCDVDD 7 8 1 2
7 8 GMCH_LVDSA1- 9
9 10
9 10 LVDSA0+ LVDSA2+ UMA@ R354 0_0402_5% GMCH_LVDSA2+
11 12 1 2
LCD POWER CIRCUIT +3VS
0.1U_0402_16V4Z1
EDID_CLK_LCD
EDID_DAT_LCD
13
11
13
12
14
14 LVDSA0- LVDSA2- UMA@ R346 1 2 0_0402_5% GMCH_LVDSA2- GMCH_LVDSA2+
GMCH_LVDSA2-
9
9
2 15 15 16 16
@ C426 17 18 LVDSA1+ LVDSBC+ UMA@ R361 1 2 0_0402_5% GMCH_LVDSBC+
LVDSBC+ 17 18 LVDSA1- LVDSBC- UMA@ R357 0_0402_5% GMCH_LVDSBC- GMCH_LVDSBC+ 9
W=60mils LVDSBC-
19
19 20
20 1 2
GMCH_LVDSBC- 9
21 22
+3VALW +LCDVDD 21 22 LVDSA2+ LVDSB0+ UMA@ R349 0_0402_5% GMCH_LVDSB0+
W=60mils U39 W=60mils LVDSB0+
23
23 24
24
LVDSA2- LVDSB0- UMA@ R344
1 2
0_0402_5% GMCH_LVDSB0- GMCH_LVDSB0+ 9
25 26 1 2
+LCDVDD LVDSB0- 25 26 GMCH_LVDSB0- 9
6 1 27 28
3 IN OUT 27 28 DISPOFF# LVDSB1+ UMA@ R340 0_0402_5% GMCH_LVDSB1+ 3
1 29 29 30 30 1 2
3 4 LVDSB1+ 31 32 DAC_BRIG LVDSB1- UMA@ R337 1 2 0_0402_5% GMCH_LVDSB1- GMCH_LVDSB1+ 9
EN NC 1 1 31 32 DAC_BRIG 28
C429 LVDSB1- 33 34 INVT_PWM GMCH_LVDSB1- 9
33 34 INVT_PWM 28
0.1U_0402_16V7K~N 5 2 C428 C427 35 36 LVDSB2+ UMA@ R335 1 2 0_0402_5% GMCH_LVDSB2+
2 GND GND 4.7U_ 0603_6.3V 0.1U_0402_16V7K~N LVDSB2+ 35 36 INVPWR_B+ LVDSB2- UMA@ R330 0_0402_5% GMCH_LVDSB2- GMCH_LVDSB2+ 9
37 38 1 2
AOZ1320CI-04_SOT23-6 2 2 LVDSB2- 37 38 INVPWR_B+ GMCH_LVDSB2- 9
39 40
UMA@ CH751H-40_SC76 D25 39 40 EDID_CLK_LCD UMA@ R32 0_0402_5% GMCH_EDID_CLK_LCD
41 42 1 2 GMCH_EDID_CLK_LCD 9
GND GND EDID_DAT_LCD UMA@ R30 0_0402_5% GMCH_EDID_DAT_LCD
9,28 GMCH_LVDDEN 2 1 1 2 GMCH_EDID_DAT_LCD 9
ACES_88242-4001
CH751H-40_SC76 CONN@
28,33 VGA_LVDDEN 2 1 VGA_LVDSAC+ R370 1 2 0_0402_5% VGA@ LVDSAC+
D24 VGA@ R325 34 VGA_LVDSAC+ VGA_LVDSAC- R368 1 2 0_0402_5% VGA@ LVDSAC-
CH751H-40_SC76 34 VGA_LVDSAC-
28 LCD_TEST_EN LCD_TEST_EN2 1 B+ 2 1 INVPWR_B+ VGA_LVDSA0+ R366 1 2 0_0402_5% VGA@ LVDSA0+
D26 SUPPRE_KC FBMA-L11-201209-221LMA30T 34 VGA_LVDSA0+ VGA_LVDSA0- R364 1 2 0_0402_5% VGA@ LVDSA0-
34 VGA_LVDSA0-
0.1U_0603_50V4Z

2 2 0.1U_0603_50V4Z
2
10K_0402_5%

R373

C407

C397

VGA_LVDSA1+ R362 1 2 0_0402_5% VGA@ LVDSA1+

+3VS 34 VGA_LVDSA1+ VGA_LVDSA1- R358 1 2 0_0402_5% VGA@ LVDSA1-
34 VGA_LVDSA1-
1 1 VGA_LVDSA2+ R353 0_0402_5% VGA@ LVDSA2+
1 2
2

34 VGA_LVDSA2+ VGA_LVDSA2- R345 1 2 0_0402_5% VGA@ LVDSA2-

1

4.7K_0402_5% R29 34 VGA_LVDSA2-

VGA_LVDSBC+ R360 1 2 0_0402_5% VGA@ LVDSBC+
34 VGA_LVDSBC+ VGA_LVDSBC- R356 1 2 0_0402_5% VGA@ LVDSBC-
34 VGA_LVDSBC-
1

VGA_LVDSB0+ R348 1 2 0_0402_5% VGA@ LVDSB0+

DISPOFF# @ R342 34 VGA_LVDSB0+ VGA_LVDSB0- R343 1 2 0_0402_5% VGA@ LVDSB0-
28 BKOFF# DISPOFF# 28 34 VGA_LVDSB0-
9 BIA_PWM BIA_PWM 2 1 INVT_PWM
10_0402_5% VGA_LVDSB1+ R341 1 2 0_0402_5% VGA@ LVDSB1+
1

34 VGA_LVDSB1+ VGA_LVDSB1- R338 1 2 0_0402_5% VGA@ LVDSB1-

1
D18 34 VGA_LVDSB1-
C413 VGA_LVDSB2+ R334 1 2 0_0402_5% VGA@ LVDSB2+
4 @ 1N4148_SOT23 @ 1U_0603_10V4Z 34 VGA_LVDSB2+ VGA_LVDSB2- R329 1 2 0_0402_5% VGA@ LVDSB2- 4
2 34 VGA_LVDSB2-
2

VGA_CLK_LCD R33 1 2 0_0402_5% VGA@ EDID_CLK_LCD

33 VGA_CLK_LCD
VGA_DAT_LCD R31 1 2 0_0402_5% VGA@ EDID_DAT_LCD
33 VGA_DAT_LCD

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT CONN/LCD CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 15 of 51
A B C D E

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

+3VM_CK505
FSLC FSLB FSLA CPU SRC PCI
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz +3VS 1
R558
2
0_0805_5% 1 1 1 1 1 1 1
C657 C629 C665 C625 C649 C626 C661
0 1 0 200 100 33.3
10U_0805_10V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N
2 2 2 2 2 2 2
0 1 1 166 100 33.3

FSB Frequency Selet: +1.25VS

Place close to U6
D +1.25VM_CK505 D
CPU Driven Stuff R1107 R1135 R1083
1 2 0.1U_0402_16V4Z~N 22U_0805_6.3V4Z 0.1U_0402_16V4Z~N
*(Default) No Stuff R1074 R1086 R1098 R1113 R1128 R1139 R532 0_0805_5% 1 1 1 1
C630
1 1
C623
1
C662 C664 C663 C627
Stuff R1086 R1139 R1135 R1074 R1139 R1135 C631
2 2 2 2 2 2 2
667MHz 22U_0805_6.3V4Z 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N
No Stuff R1083 R1107 R1128
R1113 R1098
Stuff
R1135 R1139
+3VM_CK505 U6
800MHz
No Stuff R1083 R1086 R1098 R1128 2
VDDPCI NC
48
9
VDD48
R1074 R1107 R1113 16
VDDPLL3
61
VDDREF
64
SCLK ICH_SM_CLK 13,14,19
39 63
VDDSRC SDATA ICH_SM_DA 13,14,19
55
VDDCPU
38
PCI_STOP# H_STP_PCI# 19
37
CPU_STOP# H_STP_CPU# 19
+1.25VM_CK505 12
R263 VDD96_IO
20
2.2K_0402_5% VDDPLL3_IO R495
26
FSA 2 VDDSRC_IO R_CPU_BCLK 0_0402_5%
1 1 2 MCH_CLKSEL0 7 54 1 2 CLK_CPU_BCLK 4
CPU0 R_CPU_BCLK# 0_0402_5%
36 53 1 2 CLK_CPU_BCLK# 4
R264 VDDSRC_IO CPU0# R496
5 CPU_BSEL0 1 2 49
C R262 1K_0402_5% VDDCPU_IO C
0_0402_5% R497
+VCCP 51 R_MCH_BCLK 1 2 0_0402_5%
CPU1_F CLK_MCH_BCLK 7
50 R_MCH_BCLK# 1 2 0_0402_5%
CPU1#_F CLK_MCH_BCLK# 7
+3VS 2 1 R498
2

10K_0402_5% R550 R499

@ R197 +3VS 2 1 47 R_CLK_PCIE_LAN 1 2 0_0402_5%
SRC8/CPU2_ITP CLK_PCIE_LAN 22
10K_0402_5% R562 46 R_CLK_PCIE_LAN# 1 2 0_0402_5%
SRC8#/CPU2_ITP# CLK_PCIE_LAN# 22
1K_0402_5% R500
475_0402_1% 1 2 R556 SATA_REQ1
19 CLKSATAREQ#
1

FSB PCI0/CR#_A R491

1 2 MCH_CLKSEL1 7
475_0402_1% 1 2 R563 MCH_REQ 3 34 R_PCIE_EXPR 1 2 0_0402_5%
7 CLKMCHREQ# PCI1/CR#_B SRC10 CLK_PCIE_EXPR 26
1 2 R198 27 CLK_DEBUG_PORT 22_0402_5% 1 2 R564 35 R_PCIE_EXPR# 1 2 0_0402_5%
5 CPU_BSEL1 SRC10# CLK_PCIE_EXPR# 26
R196 1K_0402_5% 22_0402_5% 1 2 R576 PCI2_TME 4 R490
28 CLK_PCI_TPM PCI2/TME
0_0402_5%
33_0402_5% 1 2 R577 PCI_CLK3 5 R533
25 CLK_PCI_CB PCI3
33 R_EXPR_CARD_REQ# 1 2 0_0402_5%
33_0402_5% 1 27_SEL SRC11/CR#_H R_MCARD_REQ# EXPR_CARD_REQ# 26
28 CLK_PCI_EC 2 R578 6 32 1 2 0_0402_5%
PCI4/27_Select SRC11#/CR#_G R538 MCARD_REQ# 27
33_0402_5% 1 2 R565 ITP_EN 7
17 CLK_PCI_ICH PCI_F5/ITP_EN R566
30 R_CLK_PCIE_MCard 1 2 0_0402_5%
SRC9 CLK_PCIE_MCARD 27
R509 31 R_CLK_PCIE_MCard# 1 2 0_0402_5%
SRC9# CLK_PCIE_MCARD# 27
10K_0402_5% CLK_XTAL_IN 60 R567
FSC X1
2 1 1 2 MCH_CLKSEL2 7 1 2 +3VS
CLK_XTAL_OUT 59 R489 R484 10K_0402_5%
R494 X2 R_PCIE_LAN_REQ# 1 0_0402_5%
5 CPU_BSEL2 1 2 44 2 PCIE_LAN_REQ# 22
R492 1K_0402_5% SRC7/CR#_F R_ROBSON_REQ#
43 1 2 ROBSON_REQ# 27
0_0402_5% SRC7#/CR#_E @ R501 0_0402_5%
1

1 2 +3VS
@ R493 @ R485 10K_0402_5%
@ R487
B 0_0402_5% 41 R_CLK_Rob 1 2 0_0402_5% B
SRC6 CLK_PCIE_Rob 27
33_0402_5% 1 2 R265 FSA 10 40 R_CLK_Rob# 1 2 0_0402_5%
CLK_PCIE_Rob# 27
2

19 CLK_48M_ICH USB_48MHZ/FSLA SRC6# @ R488

FSB 57 R587
FSLB/TEST_MODE R_MCH_3GPLL 0_0402_5%
27 1 2 CLK_MCH_3GPLL 7
SRC4 R_MCH_3GPLL# 0_0402_5%
28 1 2 CLK_MCH_3GPLL# 7
33_0402_5% 1 SRC4#
2 R510 FSC 62 R588
19 CLK_14M_ICH REF0/FSLC/TEST_SEL
R585
24 R_PCIE_ICH 1 2 0_0402_5%
SRC3/CR#_C CLK_PCIE_ICH 19
+1.25VM_CK505 45 25 R_PCIE_ICH# 1 2 0_0402_5%
VDDSRC_IO SRC3#/CR#_D CLK_PCIE_ICH# 19
R586

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# R583

21 R_PCIE_SATA 1 2 0_0402_5%
SRC2/SATA CLK_PCIE_SATA 18
For 27_SEL, 0 = Enable DOT96 & SRC1, 42 22 R_PCIE_SATA# 1 2 0_0402_5%
GNDSRC SRC2#/SATA# CLK_PCIE_SATA# 18
R584
1 = Enable SRC0 & 27MHz 8
GNDPCI
For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed 11 17 R_SSCDREFCLK R5811 2UMA@ 0_0402_5%
GND48 SRC1/SE1/27MHz_NonSS MCH_SSCDREFCLK 7
18 R_SSCDREFCLK# R5821 2UMA@ 0_0402_5%
SRC1#/SE2/27MHz_SS MCH_SSCDREFCLK# 7
1 = Overclocking of CPU and SRC NOT allowed 15
GND
19 R579
CLK_XTAL_OUT GND R_MCH_DREFCLK
13 1 2UMA@ 0_0402_5% CLK_MCH_DREFCLK 7
+3VM_CK505 +3VM_CK505 SRC0/DOT96 R_MCH_DREFCLK# 1
52 14 2UMA@ 0_0402_5% CLK_MCH_DREFCLK# 7
CLK_XTAL_IN GNDCPU SRC0#/DOT96# R580
23 R249 1 2VGA@ 0_0402_5%
GNDSRC CLK_PCIE_VGA 33
2

R248 1 2VGA@ 0_0402_5% CLK_PCIE_VGA# 33

R591 R574 29
GNDSRC CK_PWRGD
A
Placed 10K_0402_5% 10K_0402_5% CK_PWRGD/PD#
56
CK_PWRGD 19 A
VGA@ 58
Y1 within 500 GNDREF
1 2 CLK_EN#
1

2 1 mils of ICS9LPRS365BGLFT_TSSOP64 @ R511 0_0402_5% CLK_EN# 46

ITP_EN 27_SEL PCI2_TME
CK505M
14.31818MHz_20P_1BX14318BE1A
2 2
2

C640 C634 R244 R592 R575

18P_0402_50V8J~N
1 1
18P_0402_50V8J~N 10K_0402_5% 10K_0402_5%
UMA@
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
@ Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

Clock Generator
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Routing the trace at least 10mil AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 16 of 51
5 4 3 2 1
 5 4 3 2 1

+3VS

1 2 PCI_DEVSEL#
R223 8.2K_0402_5%
1 2 PCI_STOP#
R218 8.2K_0402_5% 25 PCI_AD[0..31]
1 2 PCI_TRDY# U7B
R209 8.2K_0402_5% PCI_AD0 D20 A4 PCI_REQ0#
AD0 REQ0# PCI_REQ0# 25
PCI_FRAME# PCI_AD1 PCI_GNT0#
D
1
R204
2
8.2K_0402_5% PCI_AD2
E19
D19
AD1 PCI GNT0#
D7
E18 PCI_REQ1#
PCI_GNT0# 25 D
PCI_PLOCK# PCI_AD3 AD2 REQ1#/GPIO50
1 2 A20 C18
R212 8.2K_0402_5% PCI_AD4 AD3 GNT1#/GPIO51 PCI_REQ2#
D17 B19
PCI_IRDY# PCI_AD5 AD4 REQ2#/GPIO52
1 2 A21 F18
R210 8.2K_0402_5% PCI_AD6 AD5 GNT2#/GPIO53 PCI_REQ3#
A19 A11
PCI_SERR# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 C19 C10
R238 8.2K_0402_5% PCI_AD8 AD7 GNT3#/GPIO55
A18
PCI_PERR# PCI_AD9 AD8 PCI_CBE#0
1 2 B16 C17 PCI_CBE#0 25
R211 8.2K_0402_5% PCI_AD10 AD9 C/BE0# PCI_CBE#1
A12 E15 PCI_CBE#1 25
PCI_AD11 AD10 C/BE1# PCI_CBE#2
E16 F16 PCI_CBE#2 25
PCI_AD12 AD11 C/BE2# PCI_CBE#3
A14 E17 PCI_CBE#3 25
+3VS PCI_AD13 AD12 C/BE3#
G16
PCI_AD14 AD13 PCI_IRDY#
A15 C8 PCI_IRDY# 25
PCI_AD15 AD14 IRDY# PCI_PAR
B6 D9 PCI_PAR 25
PCI_PIRQA# PCI_AD16 AD15 PAR PCI_PCIRST#
1 2 C11 G6
R239 8.2K_0402_5% PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
A9 D16 PCI_DEVSEL# 25
PCI_PIRQB# PCI_AD18 AD17 DEVSEL# PCI_PERR#
1 2 D11 A7
R213 8.2K_0402_5% PCI_AD19 AD18 PERR# PCI_PLOCK#
B12 B7
PCI_PIRQC# PCI_AD20 AD19 PLOCK# PCI_SERR#
1 2 C12 F10 PCI_SERR#
R208 8.2K_0402_5% PCI_AD21 AD20 SERR# PCI_STOP#
D10 C16 PCI_STOP# 25
PCI_PIRQD# PCI_AD22 AD21 STOP# PCI_TRDY#
1 2 C7 C9 PCI_TRDY# 25
R206 8.2K_0402_5% PCI_AD23 AD22 TRDY# PCI_FRAME#
F13 A17 PCI_FRAME# 25
PCI_PIRQE# PCI_AD24 AD23 FRAME#
1 2 E11
R240 8.2K_0402_5% PCI_AD25 AD24 PCI_PLTRST#
E13 AG24
PCI_PIRQF# PCI_AD26 AD25 PLTRST# CLK_PCI_ICH
1 2 E12 B10 CLK_PCI_ICH 16
R237 8.2K_0402_5% PCI_AD27 AD26 PCICLK PCI_PME#
D8 G7 2 1 +3V_SB
PCI_PIRQG# PCI_AD28 AD27 PME# 10K_0402_5% R202
1 2 A6
R236 8.2K_0402_5% PCI_AD29 AD28
E8
PCI_PIRQH# PCI_AD30 AD29
2 1 D6
R216 8.2K_0402_5% PCI_AD31 AD30
A3
AD31

C 1 2 PCI_REQ0# PCI_PIRQA# F9
Interrupt I/F F8 PCI_PIRQE# C
R215 8.2K_0402_5% PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
B5 G11
PCI_REQ1# PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
1 2 C5 F12 PCI_PIRQG# 25
R226 8.2K_0402_5% PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
A10 B3
PCI_REQ2# PIRQD# PIRQH#/GPIO5
1 2
R205 8.2K_0402_5% ICH8M REV 1.0
1 2 PCI_REQ3#
R207 8.2K_0402_5%

PCI_GNT3#
1

R201
@
1K_0402_5%
2

B B
Boot BIOS Strap +3VS

5
@ U8
PCI_GNT0# SPI_CS#1 Boot BIOS PCI_PCIRST# 2

P
B PCI_RST#
4 PCI_RST# 21,25
Y
1
A

1
G
A16 swap override Strap 0 1 SPI NC7SZ08P5X_NL_SC70-5 R245

3
R246 100K_0402_5%
0_0402_5%
Low= A16 swap override Enble @
PCI_GNT3# 1 1 LPC *(Defaul) 2 1

2
High= Default *
+3VS

5
@ U9
PCI_GNT0# PCI_PLTRST# 2

P
B PLT_RST#
4 PLT_RST# 7,19,22,26,27,28,33
Y
Place closely pin B10 1
A
1

1
G
NC7SZ08P5X_NL_SC70-5 R308

3
CLK_PCI_ICH @ R219 100K_0402_5%
1K_0402_5% R307 @
2

0_0402_5%
2

2
R203 2 1

@ 10_0402_5%
1

A A
1
C314

@ 8.2P_0402_50V
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 17 of 51
5 4 3 2 1

DELL CONF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

+3VS

R285
GATEA20 2 1

10K_0402_5%

R242
KB_RST# 2 1

10K_0402_5%
D +RTC_CELL D

R252 330K_0402_5%
1 2 LAN100_SLP +VCCP
R271
R275 1M_0402_5% H_FERR# 2 1
1 2 SM_INTRUDER# LPC_AD[0..3] 27,28
U7A 56_0402_5%
ICH_RTCX1 AG25 E5 LPC_AD0
ICH_INTVRMEN ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1
1 2 AF24 F5
RTCX2 FWH1/LAD1 LPC_AD2
G8
R292 330K_0402_5% R306 1 ICH_RTCRST# FWH2/LAD2 LPC_AD3
+RTC_CELL 2 AF23 F6
20K_0402_5% RTCRST# FWH3/LAD3
SM_INTRUDER# AD22 C4 LPC_FRAME#
INTRUDER# FWH4/LFRAME# LPC_FRAME# 27,28
1 2CLR_CMOS#

RTC
LPC
ICH_INTVRMEN AF25 G9 LPC_DRQ0#
J1 LAN100_SLP INTVRMEN LDRQ0# TP23 PAD
1 AD21 E6
ICH_RTCX1 NO SHORT PADS C373 LAN100_SLP LDRQ1#/GPIO23 TP24 PAD
R602 1U_0603_10V6K B24 AF13 GATEA20
GLAN_CLK A20GATE GATEA20 28
1 2 ICH_RTCX2 AG26 H_A20M#
2 A20M# H_A20M# 4
D22
10M_0402_5% LAN_RSTSYNC H_DPRSTP_R# H_DPRSTP#
AF26 2 1 H_DPRSTP# 5,7,46
DPRSTP# R296 0_0402_5%
1 1 C21 AE26
LAN_RXD0 DPSLP#
B21 H_DPSLP# 5
C683 C684 LAN_RXD1 H_FERR#
C22 AD24 H_FERR# 4
12P_0402_50V8J LAN_RXD2 FERR#

LAN / GLAN
12P_0402_50V8J
1

2 2 H_PWRGOOD
D21 AG29 H_PWRGOOD 5
LAN_TXD0 CPUPWRGD/GPIO49
E20
OUT
IN

LAN_TXD1 H_IGNNE#
C20 AF27 H_IGNNE# 4
Y2 LAN_TXD2 IGNNE#
within 2" from R1557
32.768KHZ QTFM28-32768K125P10L AH21 AE24 H_INIT#
GLAN_DOCK#/GPIO13 INIT# H_INIT# 4 +VCCP
H_INTR
NC

NC

AC20 H_INTR 4
INTR

CPU
C R217 1 2 24.9_0402_1% GLAN_COMP D25 AH14 KB_RST# C
+1.5VS GLAN_COMPI RCIN# KB_RST# 28
C25
2

GLAN_COMPO

1
+3VS AD23 H_NMI
NMI H_NMI 4
R613 33_0402_5% 1 2 HDA_BITCLK_R AJ16 AG28 H_SMI# R273
23 ACZ_BITCLK HDA_BIT_CLK SMI# H_SMI# 4
R612 33_0402_5% 1 2 HDA_SYNC_R AJ15
23 ACZ_SYNC HDA_SYNC
AA24 H_STPCLK# 56_0402_5%
STPCLK# H_STPCLK# 4
R284 33_0402_5% 1 2 HDA_RST_R# AE14
23 ACZ_RST#

2
10K_0402_5% SATA_LED# HDA_RST# THRMTRIP_ICH#
2 1 R276 AE27 1 2 R283 24_0402_1%
H_THERMTRIP# 4,7
ADC_ACZ_SDIN0 THRMTRIP#
23 ADC_ACZ_SDIN0 AJ17
HDA_SDIN0
AH17 AA23 IDE_DD[0..15] 21
HDA_SDIN1 TP8
AH15
HDA_SDIN2 IDE_DD0 placed within 2" from ICH8M

IHDA
AD13 V1
HDA_SDIN3 DD0 IDE_DD1
U2
R256 33_0402_5% 1 HDA_SDOUT_R DD1 IDE_DD2
23 ACZ_SDOUT 2 AE13 V3
HDA_SDOUT DD2 IDE_DD3
T1
PSATA_ITX_DRX_N0 PSATA_ITX_DRX_N0_C DD3 IDE_DD4
21 PSATA_ITX_DRX_N0 1 2 PAD TP25 AE10 V4
C369 3900P_0402_50V7K HDA_DOCK_EN#/GPIO33 DD4 IDE_DD5
AG14 T5
HDA_DOCK_RST#/GPIO34 DD5 IDE_DD6
AB2
PSATA_ITX_DRX_P0 PSATA_ITX_DRX_P0_C SATA_LED# DD6 IDE_DD7
21 PSATA_ITX_DRX_P0 1 2 29 SATA_LED# AF10 T6
C370 3900P_0402_50V7K SATALED# DD7 IDE_DD8
T3
PSATA_IRX_DTX_N0_C DD8 IDE_DD9
21 PSATA_IRX_DTX_N0_C AF6 R2
PSATA_IRX_DTX_P0_C SATA0RXN DD9 IDE_DD10
21 PSATA_IRX_DTX_P0_C AF5 T4
PSATA_ITX_DRX_N0_C SATA0RXP DD10 IDE_DD11
close ICH8 AH5
SATA0TXN DD11
V6
PSATA_ITX_DRX_P0_C AH6 V5 IDE_DD12
SATA0TXP DD12 IDE_DD13
U1
DD13 IDE_DD14
AG3 V2
SATA1RXN DD14 IDE_DD15
AG4 U6
SATA1RXP DD15

IDE
AJ4
SATA1TXN IDE_DA0
AJ3 AA4 IDE_DA0 21
SATA1TXP DA0 IDE_DA1
AA1 IDE_DA1 21
DA1

SATA
AF2 AB3 IDE_DA2
SATA2RXN DA2 IDE_DA2 21
AF1
B SATA2RXP IDE_DCS1# B
AE4 Y6 IDE_DCS1# 21
SATA2TXN DCS1# IDE_DCS3# +3VS
AE3 Y5 IDE_DCS3# 21
SATA2TXP DCS3#
CLK_PCIE_SATA# AB7 W4 IDE_DIOR#
16 CLK_PCIE_SATA# SATA_CLKN DIOR# IDE_DIOR# 21
CLK_PCIE_SATA AC6 W3 IDE_DIOW#
16 CLK_PCIE_SATA SATA_CLKP DIOW# IDE_DIOW# 21
Y2 IDE_DDACK# IDE_DIORDY R560 1 2 4.7K_0402_5%
DDACK# IDE_DDACK# 21
R269 AG1 Y3 IDE_IRQ IDE_IRQ R573 1 2 8.2K_0402_5%
SATARBIAS# IDEIRQ IDE_IRQ 21
1 2 AG2 Y1 IDE_DIORDY
SATARBIAS IORDY IDE_DIORDY 21
CLOSE TO JP3 W5 IDE_DDREQ
DDREQ IDE_DDREQ 21
24.9_0402_1%
Within 500 mils ICH8M REV 1.0

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS
@ R254
1K_0402_5%
2 1 ACZ_SDOUT

XOR Chain Entrance Strap

A
ICH RSVD HDA SDOUT Description A

0 0 RSVD

0 1 Enter XOR Chain

1 0 Normal Operation (Default)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

1 1 Set PCIE port config bit 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(2/4)-LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 18 of 51
5 4 3 2 1
 5 4 3 2 1

2SERIRQ +3V_SB +3V_SB

+3VS
R291
1
10K_0402_5% +3VS Place closely pin G5 Place closely pin AG9

1 2PCI_CLKRUN# CLK_48M_ICH CLK_14M_ICH

2
R610 8.2K_0402_5%
R272 R259 R615 R300 R611

1
1 2EC_THERM# 2.2K_0402_5% 2.2K_0402_5% 8.2K_0402_5%
@ R257 8.2K_0402_5% 10K_0402_5% 10K_0402_5% R235 R303
U7C

1
1 2OCP# 26 ICH_SMB_CLK
ICH_SMB_CLK AJ26 AJ12 @ 10_0402_5% @ 10_0402_5%
R305 8.2K_0402_5% ICH_SMB_DATA SMBCLK SATA0GP/GPIO21
26 ICH_SMB_DATA AD19 AJ10

2
CL_RST#1 SMBDATA SATA1GP/GPIO19

SATA
AG21 AF11

GPIO
LINKALERT# SATA2GP/GPIO36

SMB
ME_SMB_CK AC17 AG11 1 1
ME_SMB_DA SMLINK0 SATA3GP/GPIO37 C331 C371
AE19
SMLINK1 CLK_14M_ICH
AG9 CLK_14M_ICH 16
D ICH_RI# CLK14 CLK_48M_ICH @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C D

Clocks
AF17 G5 CLK_48M_ICH 16
RI# CLK48 2 2
PAD TP26 F4 D3 ICH_SUSCLK TP27 PAD
SUS_STAT#/LPCPD# SUSCLK
+3V_SB 2 1ICH_LOW_BAT# 4 XDP_DBRESET#
XDP_DBRESET# AD15
R280 8.2K_0402_5% SYS_RESET# SLP_S3#
AG23 SLP_S3# 28
PM_BMBUSY# SLP_S3# SLP_S4#
7 PM_BMBUSY# AG12 AF21 SLP_S4# 28
BMBUSY#/GPIO0 SLP_S4#
1 2ICH_PCIE_WAKE# AD18 SLP_S5#
SLP_S5# 28
R260 1K_0402_5% EC_LID_OUT# SLP_S5#
28 EC_LID_OUT# AG22
SMBALERT#/GPIO11
S4_STATE#/GPIO26
AH27 TP28 PAD R250 0_0402_5%
2ICH_RI# H_STP_PCI# M_PWROK

GPIO
1 16 H_STP_PCI# AE20 1 2
H_STP_CPU# STP_PCI#/GPIO15 PM_PWROK

SYS
R258 10K_0402_5% AG18 AE23
16 H_STP_CPU# STP_CPU#/GPIO25 PWROK PM_PWROK 7,28
1 2 R251
1 2XDP_DBRESET# 25,28 PCI_CLKRUN# AH11 AJ14 DPRSLPVR
DPRSLPVR 7,46
10K_0402_5%
CLKRUN#/GPIO32 DPRSLPVR/GPIO16

Power MGT
R261 10K_0402_5%
ICH_PCIE_WAKE# AE17 AE21 ICH_LOW_BAT#
26,27 ICH_PCIE_WAKE# WAKE# BATLOW#
1 2 CL_RST#1 28 SERIRQ SERIRQ AF12
R295 10K_0402_5% EC_THERM# SERIRQ PBTN_OUT#
4,28 EC_THERM# AC13 C2 PBTN_OUT# 28
THRM# PWRBTN#
VGATE 1 2 VRMPWRGD AJ20 AH20 PLT_RST#
28,46 VGATE VRMPWRGD LAN_RST# PLT_RST# 7,17,22,26,27,28,33
R616 0_0402_5% 1 2
PAD TP29 SST_CTL AJ22 AG27 PM_RSMRST# R299 10K_0402_5%
TP7 RSMRST#
1 2 EC_LID_OUT#
R289 10K_0402_5% OCP# AJ8 E1 CK_PWRGD_R 1 2 CK_PWRGD
4 OCP# TACH1/GPIO1 CK_PWRGD CK_PWRGD 16
ISOLATEB AJ9 R486 0_0402_5%
22 ISOLATEB TACH2/GPIO6
AH9 E3 M_PWROK RSMRST# -> CLPWROK -> PWROK
TACH3/GPIO7 CLPWROK M_PWROK 7
EC_SMI# AE16
28 EC_SMI# GPIO8
EC_SCI# AC19 AJ25 PM_SLP_M# TP30 PAD
28 EC_SCI# GPIO12 SLP_M#
PAD TP31 AG8
TACH0/GPIO17 CL_CLK0
PAD TP32 AH12 F23 CL_CLK0 7
GPIO18 CL_CLK0
AE11 AE18
GPIO20 CL_CLK1

GPIO
Controller Link
AG10
SCLOCK/GPIO22 CL_DATA0
AH25 F22 CL_DATA0 7
C RP29 QRT_STATE0/GPIO27 CL_DATA0 C
PAD TP33 AD16 AF19
QRT_STATE1/GPIO28 CL_DATA1
+3V_SB 5 4 USB_OC#1 16 CLKSATAREQ#
CLKSATAREQ# AG13 R224 3.24K_0402_1%
SATACLKREQ#/GPIO35
6 3 USB_OC#2 AF9 D24 CL_VREF0_ICH 1 2 +3VS
SLOAD/GPIO38 CL_VREF0
7 2 USB_OC#3 AJ11 AH23 CL_VREF1_ICH TP34 PAD
SDATAOUT0/GPIO39 CL_VREF1

1
1 USB_OC#4

0.1U_0402_16V4Z~N
8 AD10 1
SDATAOUT1/GPIO48 C322 R220
AJ23 CL_RST# 7
10K_1206_8P4R_5% SB_SPKR CL_RST# 453_0402_1%
24 SB_SPKR AD9
SPKR
AJ27
MEM_LED/GPIO24 2

MISC
RP28 MCH_ICH_SYNC# AJ13 AJ24 2 1
7 MCH_ICH_SYNC# ACIN 28,39,40

2
USB_OC#5 MCH_SYNC# ME_EC_ALERT/GPIO10
5 4 AF22 0_0402_5% R618
USB_OC#8 PAD TP48 ICH_RSVD EC_ME_ALERT/GPIO14
6 3 AJ21 AG19 LAN_WOL_EN
USB_OC#9 TP3 WOL_EN/GPIO9
7 2
8 1 USB_OC#0 ICH8M REV 1.0
10K_1206_8P4R_5%

2 1 USB_OC#7
R614 10K_0402_5%
U7D
PCIE_RXN1 P27 V27 DMI_RXN0 DMI_RXN0 7
27 PCIE_RXN1 PERN1 DMI0RXN
modify follow intel check list-1003 PCIE_RXP1 P26 V26 DMI_RXP0 DMI_RXP0 7
27 PCIE_RXP1 PERP1 DMI0RXP
Robson 27 PCIE_TXN1 0.1U_0402_16V7K~N 2 1@C652 PCIE_C_TXN1 N29 U29 DMI_TXN0 DMI_TXN0 7
PETN1 DMI0TXN
100K_0402_5% 27 PCIE_TXP1 0.1U_0402_16V7K~N 2 1@C644 PCIE_C_TXP1 N28 U28 DMI_TXP0 DMI_TXP0 7

Direct Media Interface

PETP1 DMI0TXP
1 2 LAN_WOL_EN
R297 PCIE_RXN2 M27 Y27 DMI_RXN1 DMI_RXN1 7
26 PCIE_RXN2 PERN2 DMI1RXN
PCIE_RXP2 M26 Y26 DMI_RXP1 DMI_RXP1 7
26 PCIE_RXP2 PERP2 DMI1RXP
100K_0402_5% Express Card 26 PCIE_TXN2 0.1U_0402_16V7K~N 2 1 C639 PCIE_C_TXN2 L29 W29 DMI_TXN1 DMI_TXN1 7
PETN2 DMI1TXN
1 2 VRMPWRGD 26 PCIE_TXP2 0.1U_0402_16V7K~N 2 1 C637 PCIE_C_TXP2 L28 W28 DMI_TXP1 DMI_TXP1 7
R617 PETP2 DMI1TXP

PCI-Express
K27 AB26 DMI_RXN2 DMI_RXN2 7
PERN3 DMI2RXN DMI_RXP2
K26 AB25 DMI_RXP2 7
DPRSLPVR PERP3 DMI2RXP DMI_TXN2
1 2 J29 AA29 DMI_TXN2 7
@ R301 499_0402_1% PETN3 DMI2TXN DMI_TXP2
J28 AA28 DMI_TXP2 7
B PETP3 DMI2TXP B
PCIE_RXN4 H27 AD27 DMI_RXN3 DMI_RXN3 7
27 PCIE_RXN4 PERN4 DMI3RXN
2 1 PLT_RST# PCIE_RXP4 H26 AD26 DMI_RXP3 DMI_RXP3 7
27 PCIE_RXP4 PERP4 DMI3RXP
R317 10K_0402_5% WLAN 27 PCIE_TXN4 0.1U_0402_16V7K~N 2 1 C622 PCIE_C_TXN4 G29 AC29 DMI_TXN3 DMI_TXN3 7
PETN4 DMI3TXN
@ 27 PCIE_TXP4 0.1U_0402_16V7K~N 2 1 C628 PCIE_C_TXP4 G28 AC28 DMI_TXP3 DMI_TXP3 7
PETP4 DMI3TXP
GLAN_RXN F27 T26 CLK_PCIE_ICH#
22 GLAN_RXN PERN5 DMI_CLKN CLK_PCIE_ICH# 16
GLAN_RXP F26 T25 CLK_PCIE_ICH
22 GLAN_RXP PERP5 DMI_CLKP CLK_PCIE_ICH 16
GLAN 22 GLAN_TXN 0.1U_0402_16V7K~N 2 1 C320GLAN_TXN_C E29
PETN5
22 GLAN_TXP 0.1U_0402_16V7K~N 2 1 C321 GLAN_TXP_C E28 Y23 R253 24.9_0402_1% Within 500 mils
PETP5 DMI_ZCOMP DMI_IRCOMP
Y24 1 2 +1.5VS
DMI_IRCOMP
D27
PERN6/GLAN_RXN USB20_N0
D26 G3 USB20_N0 30
PERP6/GLAN_RXP USBP0N USB20_P0
C29
PETN6/GLAN_TXN USBP0P
G2
USB20_N1
USB20_P0 30 USB0
C28 H5 USB20_N1 30
PETP6/GLAN_TXP USBP1N USB20_P1
USBP1P
H4
USB20_N2
USB20_P1 30 USB1
C23
B23
SPI_CLK
SPI_CS0#
USBP2N
USBP2P
H2
H1 USB20_P2
USB20_N2
USB20_P2
30
30 USB2 RSMRST circuit
E22 J3 USB20_N3 R298 0_0402_5%
SPI_CS1# USBP3N USB20_N3 30
SPI

J2 USB20_P3 USB3 1 2
USBP3P USB20_P3 30
D23 K5
SPI_MOSI USBP4N @ Q36
F21 K4
SPI_MISO USBP4P USB20_N5 EC_RSMRST# PM_RSMRST#

C
K2 USB20_N5 26 28 EC_RSMRST# 3 1
USB_OC#0 USBP5N USB20_P5 Express Card

E
30 USB_OC#0 AJ19 K1 USB20_P5 26
USB_OC#1 OC0# USBP5P USB20_N6 BAV99DW-7_SOT363 MMBT3906_SOT23
30 USB_OC#1 AG16 L3 USB20_N6 30
USB_OC#2 OC1#/GPIO40 USBP6N USB20_P6
USB FingerPrinter

B
USB_OC#2 AG15 L2 USB20_P6 30

1 2
USB_OC#3 OC2#/GPIO41 USBP6P USB20_N7
AE15 M5 USB20_N7 30
OC3#/GPIO42 USBP7N

2
USB_OC#4 AF15 M4 USB20_P7 BlueTooth
+3VS OC4#/GPIO43 USBP7P USB20_P7 30
USB_OC#5 AG17 M2 USB20_N8 @ R319 @ D30B @ D30A
OC5#/GPIO29 USBP8N USB20_N8 30
EC_SWI# AD12 M1 USB20_P8 Camera 2.2K_0402_5% BAV99DW-7_SOT363
28 EC_SWI# OC6#/GPIO30 USBP8P USB20_P8 30
USB_OC#7 AJ18 N3 USB20_N9
OC7#/GPIO31 USBP9N USB20_N9 30
USB_OC#8 AD14 N2 USB20_P9 Felica
USB20_P9 30

1
OC8# USBP9P
1

A 2.2K_0402_5% USB_OC#9 AH18 @ R304 A

6
2.2K_0402_5% R309 R625 OC9# USBRBIAS
F2 1 2 1 2
USBRBIAS# R225 22.6_0402_1%
F3
Q23 USBRBIAS 2.2K_0402_5%
SSM3K7002FU_SC70-3 ICH8M REV 1.0 Within 500 mils
2

2
S

3 1 ICH_SMB_DATA
13,14,16 ICH_SM_DA
S

3 1ICH_SMB_CLK
13,14,16 ICH_SM_CLK Security Classification Compal Secret Data Compal Electronics, Inc.
G
2

For(DDR/CLKGEN/G-sensor/WWAN) For(WLAN/EXP-Card/LAN) Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

Q35
G

ICH8(3/4)-PM,USB,GPIO
2

+5VS SSM3K7002FU_SC70-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 19 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

+RTC_CELL
20 mils

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N
1 1

C353

C355
2 2 U7E
U7F 1A A23
VSS[001] VSS[099]
K7
AD25 A13 0.1U_0402_16V7K~N +VCCP A5 L1
VCCRTC VCC1_05[01] VSS[002] VSS[100]
B13 AA2 L13
ICH_V5REF_RUN VCC1_05[02] VSS[003] VSS[101]
A16 C13 AA7 L15
V5REF[1] VCC1_05[03] VSS[004] VSS[102]
T7 C14 1 1 A25 L26
V5REF[2] VCC1_05[04] C346 C333 0.1U_0402_16V4Z~N VSS[005] VSS[103]
L13 D14 AB1 L27
ICH_V5REF_SUS VCC1_05[05] VSS[006] VSS[104]
G4 E14 AB24 L4
V5REF_SUS VCC1_05[06] VSS[007] VSS[105]
D
+1.5VS 1 2 40 mils 10U_0805_6.3V6M
VCC1_05[07]
F14
2 2
AC11
VSS[008] VSS[106]
L5 D
1 AA25 G14 AC14 M12
MBK1608301YZF 0603 VCC1_5_B[01] VCC1_05[08] VSS[009] VSS[107]
1 1 1 AA26 L11 AC25 M13
+ C330 C339 C344 VCC1_5_B[02] VCC1_05[09] VSS[010] VSS[108]
AA27 L12 AC26 M14
VCC1_5_B[03] VCC1_05[10] VSS[011] VSS[109]

C618
220U_D2_4VM
AB27 L14 AC27 M15
VCC1_5_B[04] VCC1_05[11] VSS[012] VSS[110]
AB28 L16 AD17 M16
2 2 2 2 VCC1_5_B[05] VCC1_05[12] VSS[013] VSS[111]
AB29 L17 AD20 M17
+5VS +3VS VCC1_5_B[06] VCC1_05[13] L14 VSS[014] VSS[112]
D28 L18 AD28 M23
10U_0805_6.3V6M 2.2U_0603_6.3V4Z~N VCC1_5_B[07] VCC1_05[14] 0.01U_0402_16V7K~N 1 VSS[015] VSS[113]
D29 M11 2 +1.5VS AD29 M28
VCC1_5_B[08] VCC1_05[15] VSS[016] VSS[114]

CORE
E25 M18 MBK1608301YZF 0603 AD3 M29
VCC1_5_B[09] VCC1_05[16] VSS[017] VSS[115]
1

E26 P11 1 1 AD4 M3

R243 D10 VCC1_5_B[10] VCC1_05[17] C338 10U_0805_6.3V6M VSS[018] VSS[116]
E27 P18 AD6 N1
VCC1_5_B[11] VCC1_05[18] VSS[019] VSS[117]
F24 T11 AE1 N11
100_0402_5% CH751H-40PT_SOD323-2 VCC1_5_B[12] VCC1_05[19] C334 VSS[020] VSS[118]
F25 T18 AE12 N12
VCC1_5_B[13] VCC1_05[20] 2 2 VSS[021] VSS[119]
20 mils G24 U11 AE2 N13
2

VCC1_5_B[14] VCC1_05[21] VSS[022] VSS[120]

H23 U18 AE22 N14
ICH_V5REF_RUN VCC1_5_B[15] VCC1_05[22] VSS[023] VSS[121]
H24 V11 AD1 N15
VCC1_5_B[16] VCC1_05[23] VSS[024] VSS[122]
1 J23 V12 AE25 N16
C342 VCC1_5_B[17] VCC1_05[24] VSS[025] VSS[123]
J24 V14 +1.25VS AE5 N17
VCC1_5_B[18] VCC1_05[25] VSS[026] VSS[124]
K24 V16 AE6 N18
1U_0402_6.3V4K VCC1_5_B[19] VCC1_05[26] VSS[027] VSS[125]
K25 V17 AE9 N26
2 VCC1_5_B[20] VCC1_05[27] VSS[028] VSS[126]

22U_0805_6.3V4Z
L23 V18 AF14 N27
VCC1_5_B[21] VCC1_05[28] VSS[029] VSS[127]
L24 1 AF16 N4
VCC1_5_B[22] VSS[030] VSS[128]

VCCA3GP

C360
L25 R29 AF18 N5
VCC1_5_B[23] VCCDMIPLL VSS[031] VSS[129]
M24 AF3 N6
VCC1_5_B[24] VSS[032] VSS[130]
M25 AE28 AF4 P12
VCC1_5_B[25] VCC_DMI[1] 2 VSS[033] VSS[131]
N23 AE29 AG5 P13
+5V_SB +3V_SB VCC1_5_B[26] VCC_DMI[2] VSS[034] VSS[132]
N24 AG6 P14
VCC1_5_B[27] VSS[035] VSS[133]
N25 AC23 +VCCP AH10 P15
VCC1_5_B[28] V_CPU_IO[1] VSS[036] VSS[134]
P24 AC24 AH13 P16
VCC1_5_B[29] V_CPU_IO[2] VSS[037] VSS[135]
1

4.7U_ 0603_6.3V

0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N
P25 AH16 P17
R247 D9 VCC1_5_B[30] 0.1U_0402_16V4Z~N VSS[038] VSS[136]
R24 AF29 +3VS 1 1 1 AH19 P23
VCC1_5_B[31] VCC3_3[01] VSS[039] VSS[137]

C341

C340

C352
C R25 (DMI) AH2 P28 C
VCC1_5_B[32] 1 VSS[040] VSS[138]
10_0402_5% CH751H-40PT_SOD323-2 R26 AD2 0.1U_0402_16V4Z~N
+3VS AF28 P29
VCC1_5_B[33] VCC3_3[02] VSS[041] VSS[139]
R27 1 (SATA) C347 AH22 R11
2

ICH_V5REF_SUS VCC1_5_B[34] 2 2 2 VSS[042] VSS[140]

T23 AC8 +3VS AH24 R12
VCC1_5_B[35] VCC3_3[03] 2 VSS[043] VSS[141]

C354
20 mils T24 AD8 AH26 R13

VCCP_CORE
VCC1_5_B[36] VCC3_3[04] VSS[044] VSS[142]
1 T27 AE8 AH3 R14
C336 VCC1_5_B[37] VCC3_3[05] +3VS 2 VSS[045] VSS[143]
T28 AF8 AH4 R15
VCC1_5_B[38] VCC3_3[06] VSS[046] VSS[144]
T29 AH8 R16
0.1U_0402_16V4Z~N VCC1_5_B[39] VSS[047] VSS[145]
U24 AA3 AJ5 R17
2 VCC1_5_B[40] VCC3_3[07] VSS[048] VSS[146]
U25 U7 1 B11 R18
VCC1_5_B[41] VCC3_3[08] C349 VSS[049] VSS[147]
V23 V7 B14 R28
VCC1_5_B[42] VCC3_3[09] 0.1U_0402_16V4Z~N VSS[050] VSS[148]
V24 W1 B17 R4
VCC1_5_B[43] VCC3_3[10] VSS[051] VSS[149]
V25 W6 B2 T12

IDE
VCC1_5_B[44] VCC3_3[11] 2 +3VS VSS[052] VSS[150]
W25 W7 B20 T13
VCC1_5_B[45] VCC3_3[12] VSS[053] VSS[151]
L17 Y25 Y7 B22 T14
VCC1_5_B[46] VCC3_3[13] 0.1U_0402_16V4Z~N VSS[054] VSS[152]
B8 T15
VSS[055] VSS[153]
+1.5VS 1 2 AJ6 A8 C24 T16
VCCSATAPLL VCC3_3[14] VSS[056] VSS[154]
1U_0603_10V4Z

B15 1 1 1 C26 T17

VCC3_3[15] VSS[057] VSS[155]
10U_0805_6.3V6M

MBK1608301YZF 0603 AE7 B18 C27 T2

+1.5VS VCC1_5_A[01] VCC3_3[16] VSS[058] VSS[156]

C328

C359
1 1 AF7 B4 C327 C6 U12
VCC1_5_A[02] VCC3_3[17] VSS[059] VSS[157]
ARX
C374

C379

1 AG7 B9 0.1U_0402_16V4Z~N D12 U13

C378 VCC1_5_A[03] VCC3_3[18] 2 2 2 VSS[060] VSS[158]
AH7 C15 D15 U14
VCC1_5_A[04] VCC3_3[19] VSS[061] VSS[159]
AJ7 D13 D18 U15
PCI

2 2 1U_0603_10V4Z VCC1_5_A[05] VCC3_3[20] 0.1U_0402_16V4Z~N VSS[062] VSS[160]

D5 D2 U16
2 VCC3_3[21] VSS[063] VSS[161]
AC1 E10 D4 U17
VCC1_5_A[06] VCC3_3[22] VSS[064] VSS[162]
AC2 E7 E21 U23
VCC1_5_A[07] VCC3_3[23] VSS[065] VSS[163]
ATX

AC3 F11 E24 U26

VCC1_5_A[08] VCC3_3[24] VSS[066] VSS[164]
AC4 E4 U27
VCC1_5_A[09] 0.1U_0402_16V4Z~N VSS[067] VSS[165]
AC5 AC12 +3VS E9 U3
VCC1_5_A[10] VCCHDA VSS[068] VSS[166]
1 F15 U5
VSS[069] VSS[167]
AC10 AD11 +3V_SB E23 V13
+1.5VS VCC1_5_A[11] VCCSUSHDA C351 VSS[070] VSS[168]
1 AC9 1 F28 V15
B C372 VCC1_5_A[12] TP_VCCSUS1.05_INT_ICH1 VSS[071] VSS[169] B
J6 F29 V28
VCCSUS1_05[1] TP35 2 VSS[072] VSS[170]
AA5 AF20 TP_VCCSUS1.05_INT_ICH2 C356 F7 V29
1U_0603_10V4Z VCC1_5_A[13] VCCSUS1_05[2] TP36 VSS[073] VSS[171]
AA6 G1 W2
2 VCC1_5_A[14] 2 0.1U_0402_16V4Z~N VSS[074] VSS[172]
AC16 VCCSUS1_5_ICH_1 TP37 E2 W26
VCCSUS1_5[1] VSS[075] VSS[173]
G12 G10 W27
VCC1_5_A[15] VCCSUS1_5_ICH_2 VSS[076] VSS[174]
G17 J7 TP38 G13 Y28
VCC1_5_A[16] VCCSUS1_5[2] VSS[077] VSS[175]
H7 G19 Y29
VCC1_5_A[17] 0.1U_0402_16V4Z~N VSS[078] VSS[176]
C3 +3V_SB G23 Y4
VCCSUS3_3[01] VSS[079] VSS[177]
AC7 1 1 G25 AB4
VCC1_5_A[18] VSS[080] VSS[178]
AD7 AC18 G26 AB23
VCC1_5_A[19] VCCSUS3_3[02] C646 C653 VSS[081] VSS[179]
AC21 G27 AB5
VCCSUS3_3[03] VSS[082] VSS[180]
+1.5VS D1 AC22 H25 AB6
VCCPSUS

VCCUSBPLL VCCSUS3_3[04] 2 2 0.1U_0402_16V4Z~N VSS[083] VSS[181]

+1.5VS AG20 H28 AD5
VCCSUS3_3[05] VSS[084] VSS[182]
1 1 F1 AH28 H29 U4
VCC1_5_A[20] VCCSUS3_3[06] VSS[085] VSS[183]
USB CORE

C377 C381 L6 H3 W24

VCC1_5_A[21] VSS[086] VSS[184]
L7 P6 H6
0.1U_0402_16V4Z~N 0.1U_0402_16V4Z~N VCC1_5_A[22] VCCSUS3_3[07] VSS[087]
M6 P7 J1 A1
2 2 VCC1_5_A[23] VCCSUS3_3[08] VSS[088] VSS_NCTF[01]
M7 C1 +3V_SB J25 A2
VCC1_5_A[24] VCCSUS3_3[09] VSS[089] VSS_NCTF[02]
VCCSUS3_3[10]
N7 1 C362 J26
VSS[090] VSS_NCTF[03]
A28
+1.5VS W23 P1 J27 A29
VCC1_5_A[25] VCCSUS3_3[11] VSS[091] VSS_NCTF[04]
P2 J4 AH1
TP39 VCC_LAN1_05_INT_ICH_1 VCCSUS3_3[12] 0.47U_0603_10V7K VSS[092] VSS_NCTF[05]
F17 P3 J5 AH29
VCCPUSB

+3VS 0316 change design TP40 VCC_LAN1_05_INT_ICH_2 VCCLAN1_05[1] VCCSUS3_3[13] 2 VSS[093] VSS_NCTF[06]
G18 P4 K23 AJ1
VCCLAN1_05[2] VCCSUS3_3[14] VSS[094] VSS_NCTF[07]
P5 K28 AJ2
VCCSUS3_3[15] VSS[095] VSS_NCTF[08]
F19 R1 K29 AJ28
VCCLAN3_3[1] VCCSUS3_3[16] VSS[096] VSS_NCTF[09]
1 G20 R3 K3 AJ29
C329 MBK1608301YZF 0603 VCCLAN3_3[2] VCCSUS3_3[17] VSS[097] VSS_NCTF[10]
R5 K6 B1
VCCSUS3_3[18] VSS[098] VSS_NCTF[11]
1 2 A24 R6 B29
0.1U_0402_16V4Z~N L12 @ L11
4.7U_ 0603_6.3V VCCGLANPLL VCCSUS3_3[19] VSS_NCTF[12]
2 +1.5VS
GLAN POWER
10U_0805_6.3V6M

G22 VCCCL1_05_ICH
2.2U_0603_106K

1 1 +1.5VS 2 1 A26 ICH8M REV 1.0

VCCGLAN1_5[1] VCCCL1_05 TP41
1 A27
C319 MBK1608301YZF 0603 VCCGLAN1_5[2] VCCCL1_5_ICH
B26 A22
A C318 VCCGLAN1_5[3] VCCCL1_5 TP46 A
B27
2 2 @ C309 VCCGLAN1_5[4]
B28 F20 +3VS
2 VCCGLAN1_5[5] VCCCL3_3[1]
G21
VCCCL3_3[2]
+3VS B25
VCCGLAN3_3
ICH8M REV 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(4/4)-POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 20 of 51
5 4 3 2 1
 5 4 3 2 1

CDROM CONN
+5VS
IDE_DD[0..15] 18
C607 47P_0402_50V8J 10U_0805_10V4Z 0.1U_0402_16V4Z
2 1
1 1 1 1
JODD1 C542
C536 C538 C537
1
D 1 2 2 2 2 D
2
PCI_RST# R_PCI_RST# 2
17,25 PCI_RST# 1 2 3
R471 0_0402_5% IDE_DD8 3 1U_0603_10V4Z 1000P_0402_50V7K~N
4
IDE_DD7 4
5
IDE_DD9 5
6
IDE_DD6 6
7 7
IDE_DD10 8
8
Close to ODD Conn
IDE_DD5 9
IDE_DD11 9
10
IDE_DD4 10
11
IDE_DD12 11
12
IDE_DD3 12
13
IDE_DD13 13
14
IDE_DD2 14
15
IDE_DD14 15
16
IDE_DD1 16
17 17
IDE_DD15 18
IDE_DD0 18
19
IDE_DDREQ 19
20
18 IDE_DDREQ 20
21
+5VS 18 IDE_DIOR# IDE_DIOR# 21
22
IDE_DIOW# 22
18 IDE_DIOW# 23
23
24
IDE_DIORDY 24
18 IDE_DIORDY 25
IDE_DDACK# 25
26 26
1

18 IDE_DDACK# IDE_IRQ 27
18 IDE_IRQ 27
R400 18 IDE_DA1 IDE_DA1 28
@2 R405 1 PDIAG# 28
100K_0402_5% +5VS 29
IDE_DA0 29
18 IDE_DA0 30
10K_0402_5% IDE_DA2 30
31
2

18 IDE_DA2 IDE_DCS1# 31
32
18 IDE_DCS1# IDE_DCS3# 32
33 33
C ODD_ACT_LED# 18 IDE_DCS3# 34 C
29 ODD_ACT_LED# 34
35
35
36
36
+5VS 37
37
38
38
39
39
If CDROM is Slave 40
40
41
41
then SD_CSEL= Floating 42
42
43
SD_CSEL 43
else SD_CSEL= Low 2
R403
1
470_0402_5%
44
44
45
45
46
GND
47
GND

ACES_88512-4541

B B

SATA HDD CONN

JSATA1
1
PSATA_ITX_DRX_P0 GND
18 PSATA_ITX_DRX_P0 2 A+
PSATA_ITX_DRX_N0 3
18 PSATA_ITX_DRX_N0 A-
C645 3900P_0402_50V7K 4
GND
18 PSATA_IRX_DTX_N0_C 2 1 5
B- +5VS
6
B+
18 PSATA_IRX_DTX_P0_C 2 1 7
GND
C641 3900P_0402_50V7K 10U_0805_10V4Z 0.1U_0402_16V4Z
8 1
V33
+3VS 9 1 1 1 1
V33 C307 +
10 C317
V33 150U 6.3V M Y NOJ C315 C312 C316
11
GND
12 @
GND 2 2 2 2 2
13
GND
+5VS 14 V5
15 0.1U_0402_16V4Z 1000P_0402_50V7K~N
V5
16
V5
17
GND
18
Reserved
Close to SATA HDD
19
A GND A
20
V12
21
V12
22
V12
then SD_CSEL= Floating
SUYIN_127043FR022G226ZL_NR
CONN@
else SD_CSEL= Low
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/CDROM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 21 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

+3VALW
W=60mils +LAN_IO +LAN_VDD
Q26 L22 LAN_DVDD12
FBMA-L11-322513-201LMA40T_1210

D
6 1.5A

S
5 4 1 2 1 2 LAN_DVDD12
1 2 1 1 1 1 1 1 1

C386

C391

C395

C408

C12

C392

C411

C13

C15

C14
C403 C420 C425 C406 C394 C17 C414 C393 R322

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N
1 1 1 1 1 1 1 1 1 1 1
1U_0603_10V6K SI3456BDV-T1-E3_TSOP6 @ 0_0603_5%

G
3
2 2 2 2 2 2 2 2

22U_1206_6.3V6M

22U_1206_6.3V6M
B+_BIAS

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N
2 2 2 2 2 2 2 2 2 2
2
R350
D 470K_0402_5% D
1

EN_WOL 2@ R351 1 1.5M_0402_5%

These caps close to U47: Pin 16, 37, 46, 53 +LAN_IO
1

D
Q27 3.6K_0402_5%
These caps close to U47: Pin 21, 32, 38, 43, 49, 52
2
SSM3K7002FU_SC70-3 G EN_WOL# 28 U47 R9 1 2
S @ U43
3

19 GLAN_RXP 2 1 GLAN_RXP_C 29 45 LAN_EEDO 4 5 1

C387 0.1U_0402_16V7K~N HSOP EEDO LAN_EEDI DO GND
47 3 6 1@ R28 2 @ C19
EEDI/AUX DI NC
19 GLAN_RXN 2 1 GLAN_RXN_C 30 48 LAN_EECLK 2 7 0_0402_5% 0.1U_0402_16V7K~N
C388 0.1U_0402_16V7K~N HSON EESK LAN_EECS SK NC +LAN_IO LAN_DVDD12
44 1 8 +LAN_IO
GLAN_TXP EECS CS VCC 2
19 GLAN_TXP 23
HSIP AT93C46-10SU-2.7 SO 8P

1
GLAN_TXN 24
19 GLAN_TXN HSIN
54 LAN_LED3 R17
LED3 LAN_LED2
PCIE_LAN_REQ# LED2
55
LAN_LED1
0_0805_5% W=40mils
16 PCIE_LAN_REQ# 33 56 8111C@
CLKREQB LED1 LAN_LED0
57 R14

2
LED0
16 CLK_PCIE_LAN 26
REFCLK_P +LAN_VDDSR
W=40mils
1 2
27 3 LAN_MDIP0
16 CLK_PCIE_LAN# REFCLK_N MDIP0
+LAN_VDD 4 LAN_MDIN0 1 1 C417
MDIN0 LAN_MDIP1 C421 0_0805_5%
7,17,19,26,27,28,33 PLT_RST# 20 6
PERSTB MDIP1 LAN_MDIN1 8102E@
7
MDIN1

22U_1206_6.3V6M
60mil L23 LAN_MDIP2

0.1U_0402_10V7K~N
9
MDIP2 LAN_MDIN2 2 2
1 2 1 10
SROUT12 MDIN2 LAN_MDIP3
4.7UH_1098AS-4R7M_1.3A_20%
8111C@
60mil 5
MDIP3
12
13 LAN_MDIN3
+LAN_VDD FB12 MDIN3
+3VS 1 R352 2 0_0402_5% 62
1 1 +LAN_IO ENSR
C C416 C412 R339 8111C@ 21 C
DVDD12 LAN_DVDD12
1 2 1 2 64 32
RSET DVDD12
1

0_0805_5% R347 2.49K_0402_1% 38

2 2 DVDD12
22U_1206_6.3V6M

R327 C792 close to U47(PIN63)

0.1U_0402_10V7K~N

8102E@ 43
DVDD12
1K_0402_5% 49 , then C783 close to C792
DVDD12
28 PCIE_PME# 19 52
LANWAKEB DVDD12 L18
2

ISOLATEB
19 ISOLATEB 36
ISOLATEB
22
30mil FBML10160808121LMT_0603
2 1
EVDD12 LAN_AVDD12 LAN_AVDD12
28 +LAN_VDD
EVDD12
2

LAN_XTAL1 60 1 2
R328 CKTAL1 C389 0.1U_0402_16V7K~N 8111C@
LAN_XTAL2 LAN_AVDD12
L92, C788, C778 15K_0402_5% 61
CKTAL2 VDD33
16
37
+LAN_IO 1
C390
2
0.1U_0402_16V7K~N
1 2
VDD33
close to U28(Pin 1) <200mil

C11

C410

C404

C396
46 R2 1 1 1 1
1

VDD33 0_0603_5%
53
VDD33
65
EXPOSE_PAD

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N

0.1U_0402_10V7K~N
+LAN_VDDSR
W=40mils L24 2 2 2 2
63 +LAN_VDDSR
VDDSR FBML10160808121LMT_0603
25
EGND LAN_AVDD33
Y6 2 2 1 +LAN_IO
AVDD33
27P_0402_50V8J

27P_0402_50V8J

31 59
EGND AVDD33
1 2 1 2
2 2 8 LAN_AVDD12 C418 0.1U_0402_16V7K~N
AVDD12
C422

C423

25MHZ_20P_1BX25000CK1A LAN_DVDD12 1 R326 2 0_0402_5% 15 11 1 2

8102E@ NC AVDD12 C10 0.1U_0402_16V7K~N
17 14
NC AVDD12
18 58 LAN_DVDD12
1 1 NC AVDD12
34
NC These caps close to U47: Pin 8, 11, 14, 58
0.1U_0402_10V6K

0.1U_0402_10V6K

35
NC
39 50
NC IGPIO LAN_CABDT +LAN_IO
40 51 LAN_CABDT 28
NC OGPIO @
41 R634
B NC JLAN2 B
1 1 42
NC

1
C9

C16

@ @ 1 2 +3VS
RTL8111C-GR_QFN64_9X9 R355 LAN_LED0 1 R10 2 LAN_ACTIVITY# 13
220_0402_5% Yellow LED-
8111C@ 10K_0402_5% 10K_0402_5%
2 2 12
+LAN_IO Yellow LED+
R12
49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

2
2

D20 RJ45_TX3- 8
PR4-
R11

R13

R15

@ @ LAN_LED2 1 2 LED2_LED3
RJ45_TX3+ 7
@ @ T51 CH751H-40PT_SOD323-2 PR4+
75_1206_8P4R_5% RJ45_RX1- 6
1

C409 1 0.01U_0402_16V7K V_DAC C405 D21 PR2-

2 1 24 5 4
LAN_MDIN3 TCT1 MCT1 RJ45_TX3- 1000P_1206_2KV7K LAN_LED3 1 RJ45_TX2-
2 23 6 3 2 5
LAN_MDIP3 TD1+ MX1+ RJ45_TX3+ PR3-
3 22 7 2
TD1- MX1- CH751H-40PT_SOD323-2 RJ45_TX2+
8 1 2 1 4
C415 1 0.01U_0402_16V7K V_DAC +LAN_IO PR3+
2 4 21
LAN_MDIN2 TCT2 MCT2 RJ45_TX2- RP1 RJ45_RX1+
5 20 3
LAN_MDIP2 TD2+ MX2+ RJ45_TX2+ PR2+
6 19
TD2- MX2-

1
RJ45_TX0- 2
C424 1 V_DAC PR1-
2 0.01U_0402_16V7K 7 18 R372 15
LAN_MDIN1 TCT3 MCT3 RJ45_RX1- RJ45_TX0+ GND
8 17 10K_0402_5% 1
LAN_MDIP1 TD3+ MX3+ RJ45_RX1+ PR1+
9 16 14
TD3- MX3- R4 0_0402_5% D22 LED2_LED3 1 R8 GND
1 2 2 LINK_10_1000# 11

2
C419 1 V_DAC LAN_LED1 1 LED1_LED3 Green LED-
2 0.01U_0402_16V7K 10 15 2 220_0402_5%
LAN_MDIN0 TCT4 MCT4 RJ45_TX0- LED1_LED3 1 R5
11 14 2 LINK_100_1000# 9
LAN_MDIP0 TD4+ MX4+ RJ45_TX0+ R7 0_0402_5% CH751H-40PT_SOD323-2 220_0402_5% Orange LED-
12 13 1 2
TD4- MX4-
+LAN_IO 10
D23 Green-Orange LED+
1

1
49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

R321 1 2 0_0402_5% LAN_LED3 1 2

R16

R18

R21

R24

BOTH_GST5009-LF C-1775553
CH751H-40PT_SOD323-2 CONN@
@ @ @ @ R1 1 2 0_0402_5%
A A
2

U47
2 2
C18 C20
0.1U_0402_10V6K 0.1U_0402_10V6K
1 1
@ @
RTL8102E-GR QFN 64P
AS CLOSE AS T51 8102E@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Broadcom BCM5787M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4121P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 22 of 51
5 4 3 2 1
 A B C D E F G H

+5VS
Adjustable Output
R294 U23
1 2 1 5
10K_0603_1% EN NC +VDDA
4.7U_0805_10V4Z

0.1U_0402_16V7K~N 2
GND
3 4
1 VIN VOUT 1
C364

C363

0.1U_0402_16V7K~N
4.7U_0805_10V4Z~N
RT9198-4GPBG SOT-23 5P 4.75V
1 1

2 2

C382

C380
HD Audio Codec For EMI +3VS

0_0603_5%
20mil 0.1U_0402_16V4Z 1 2

2
R568 +3VS

2
+AVDD_AC97 R302
1 1 1
R313
C671 C680 C666 100K_0402_5% HP_JD
L36 1 2 0.1U_0402_16V4Z 40mil 10U_1206_16V4Z
100K_0402_5%
+VDDA

1
FBM-L11-160808-800LMT_0603 2 2 2 D
1 1 1

1
C685 PLUG_IN# 2 Q24
24 PLUG_IN#
2 C687 C669 0.1U_0402_16V4Z G SSM3K7002FU_SC70-3 2
10U_1206_16V4Z
25

38
S

3
1

9
2 2 2 U21
0.1U_0402_16V4Z C672 1000P_0402_50V7K~N

DVDD_IO
DVDD
AVDD1

AVDD2

1
D
C677 1000P_0402_50V7K~N 24 PLUG_IN 2 Q25
G SSM3K7002FU_SC70-3
14 35 LINEL 1 2 AMP_LEFT 24 S

3
NC LINE_OUT_L R593 6.8K_0402_5%
15 36 LINER 1 2 AMP_RIGHT 24
NC LINE_OUT_R @ C668 1000P_0402_50V7K~N R589 6.8K_0402_5%
16 39 HP_LOUT 1 2 HP_LEFT 24
MIC2_L HP_OUT_L R554 0_0603_5%
17 41 HP_ROUT 1 2 HP_RIGHT 24
MIC2_R HP_OUT_R R546 0_0603_5%
23 45 @ C667 1000P_0402_50V7K~N
LINE1_L NC
24 46 DMIC_CLK 30
LINE1_R DMIC_CLK
18 43
CD_L NC
20 44
CD_R NC
2 1 1 2
19 @ R597 10_0402_5% @ C673 10P_0402_50V8J
CD_GND ACZ_BITCLK_CODEC
6 1 2 ACZ_BITCLK 18
C_MIC1 BIT_CLK R598 0_0402_5%
24 MIC1 1 2 21 MIC1_L
C689 2.2U_0603_10V6K
24 MIC2 1 2 C_MIC2 22 8 AC97_SDIN0_CODEC
1 2 0_0402_5% ADC_ACZ_SDIN0 18
C690 2.2U_0603_10V6K MIC1_R SDATA_IN R600
24 MONO_IN 12 37
PCBEEP MONO_OUT
29
3 LINE1_VREFO 3
18 ACZ_RST# 11 RESET#
31
GPIO1
18 ACZ_SYNC 10
SYNC 26
5
MIC1_VREFO_L
28 10mil +MIC1_VREFO_L
18 ACZ_SDOUT SDATA_OUT 26
2
MIC1_VREFO_R
32 10mil +MIC1_VREFO_R
30 DMIC_DATA GPIO0
3 30
HP_JD GPIO3 MIC2_VREFO
R603
2 1
39.2K _0402_1%
13
34
SENSE A
27 AC97_VREF
10mil
SENSE B VREF
24 MIC_JD 1 2 1
R604 20K_0402_1% 47 40
EAPD JDREF
24 EAPD 2 R572 1 C681
1

2 2 2 0_0402_5% 48 33 10U_0805_10V4Z
SPDIFO NC R569 2
C686

C682

C674
10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

4 26 20K_0402_1%
DVSS1 AVSS1
7 42
@ 1 @ 1 @ 1 DVSS2 AVSS2
2

ALC268-GR_LQFP48

Reserved for TEST

2 R627 1
0_0402_5%
1 2
R548 0_0402_5%
1 2
R314 0_0402_5%
1 2
4 R561 0_0402_5% 4

GND AGND

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Codec ALC268
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 23 of 51
A B C D E F G H

GRATIS - FOR FREE

hexainf@hotmail.com
 A B C D E

Speaker Connector ACES_88266-04001~N

INTSPK_R1 4 6
R537 4 G2
INTSPK_R2 3 5
W=40Mil INTSPK_L1 3 G1
2 1 +5VS 2
INTSPK_L2 2
1 1 1
1
C648 C651 0_0402_5% +5VS JSPK1

2
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 D4 D5

16
15
6
U18 R520 1 2 10K_0402_5% PACDN042_SOT23-3~D
PACDN042_SOT23-3~D
@ @

VDD
PVDD1
PVDD2
@ R512 1 2 10K_0402_5%

1
4 C642 1 2 7 2 R513 1 2 10K_0402_5% 4
0.47U_0603_10V7K RIN+ GAIN0
3 @ R521 1 2 10K_0402_5%
GAIN1
C638 1 2 AMP_R 17
23 AMP_RIGHT
0.47U_0603_10V7K RIN-
ROUT+ 18 SPK_R1 1 2 INTSPK_R1 MICROPHONE IN JACK
R505 0_0603_5%
3K_0402_5% R622 FOX_JA6333L-B3S0-7F~N
14 SPK_R2 1 2 INTSPK_R2 3K_0402_5%
2 R620
1 5
ROUT- +MIC1_VREFO_R
C650 1 2 9 R504 0_0603_5% 2 1
LIN+ 1K_0402_5% +MIC1_VREFO_L
0.47U_0603_10V7K 4 10
R621 23 MIC_JD
4 SPK_L1 1 2 INTSPK_L1 9
LOUT+ R502 0_0603_5% MIC-2
23 MIC2 1 2 1 2 3 8
C636 1 2 AMP_L 5 L40 CHB2012U170_0805 6 7
23 AMP_LEFT LIN-
0.47U_0603_10V7K 8 SPK_L2 1 2 INTSPK_L2 23 MIC1 1 2 1 2 MIC-1 2
LOUT- R503 0_0603_5% L37 CHB2012U170_0805 1

2
R605 1 1
1K_0402_5% C692 C691 D12
JMIC1
12 220P_0402_50V7K @
NC 2 2 PACDN042_SOT23-3~D
10

1
10K_0402_5% @ R506 BYPASS 220P_0402_50V7K
2 1 19
SHUTDOWN
1
C654

GND1
GND2
GND3
GND4
GND

2 1U_0603_10V4Z
+3VS P3017THF TSSOP 20P
21

20
13
11
1
HEADPHONE OUT JACK
1

3 FOX_JA6333L-B3S0-7F~N 3
R508 5
100K_0402_5%
PLUG_IN 4 10
23 PLUG_IN
9
2

HP_OUTR R607 1 2 47_0402_5% HP_R 1 2 HPR 3 8

D29 CH751H-40_SC76 L38 CHB2012U170_0805 6 7
2 1 R523 1 2 PLUG_IN GAIN0 GAIN1 GAIN HP_OUTL R608 1 2 47_0402_5% HP_L 1 2 HPL 2
L39 CHB2012U170_0805 1
2.7K_0402_5% 2 2
1

1
D
@
1

2 Q31 0 0 6dB C694 C693 JHP1

28 EC_MUTE# 470P_0402_50V7K
G SSM3K7002FU_SC70-3 R609 R606470P_0402_50V7K
1K_0402_5%

2
S @ 1K_0402_5% @ 1K_0402_5% 1 1
100P_0402_50V8J
3

R507 D31
1

2
C624 PACDN042_SOT23-3~D
* 0 1 10dB
2

@
2

1
1 0 15.6dB
23 EAPD +3VS
Change to 100p from 0.01u for EMI +3VS
-1012 1 1 21.6dB

5
Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off U19 Reserve the 0 ohm resistor.

1
PLUG_IN# 2

P
23 PLUG_IN# B
4 HP_MUTE# R288 for voltage filtering
EAPD Y 0_0603_5%
1
A

G
NC7SZ08P5X_NL_SC70-5 1 2

2
C361 1U_0603_10V4Z
2 2

19

10
+VDDA U20
@

PVDD

SVDD
28 EC_MUTE# EC_MUTE# 2 1 HP_MUTE# 14 11 HP_OUTR
SHDNR# OUTR
1

R266 0_0402_5%
R626 18 9 HP_OUTL
10K_0402_5% SHDNL# OUTL

C695
2

1 2 R286 2.2K_0402_5% 4
NC-4
23 HP_RIGHT 1 2 HP_INR 1 2 HPINR 15
INR
1

C357 2.2U_0603_6.3V6K 6
R624 1U_0603_10V4Z NC-6
23 HP_LEFT 1 2 HP_INL 1 2 HPINL 13
10K_0402_5% C358 2.2U_0603_6.3V6K INL
C366 8
R287 2.2K_0402_5% NC-8
EC Beep 28 BEEP# 1 2 1
R311
2 C688 12
2

NC-12
R277 560_0402_5% 1 2 MONO_IN MONO_IN 23 1 16
1U_0603_10V4Z C1P NC-16
1 2 1

PGND

SGND
3

PVss

SVss
1U_0603_10V4Z 20
C1N NC-20
1

47K_0402_5% C 1 2 C375
2 Q37 1U_0603_10V4Z
R623 2
B TPA4411MRTJR QFN 20P

17
E 2SC2411K_SC59 2.4K_0402_5%
3

C367
R312 1
19 SB_SPKR 1 2 1 2
C376
ICH Beep
1

1 R278 560_0402_5% 1U_0603_10V4Z 1

1U_0603_10V4Z D11 2
1 2
R310 RB751V_SOD323
47K_0402_5% 10K_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP/Audio Jack
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 24 of 51
A B C D E
 5 4 3 2 1

+1.8VS_CR
AP2301GN_SOT23-3
+1.8V Q34 +3VS

D
3 1

4.7U_ 0603_6.3V

0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_ 0603_6.3V

0.1U_0402_10V6K
0.01U_0402_25V7K~N
R601 AS CLOSE AS U44

G
1 1 1

2
1 2 +3VS
31,45 SUSP

C647

C620

C632

C619

C621
100K_0402_5% 1 +3VS_PHY

4.7U_ 0603_6.3V

0.1U_0402_10V6K
+3VS_PHY L15
2 2 2

C679
1 1 2
+3VS FBM-L11-160808-601LMT_0603
2

C660

C675

0.1U_0402_10V6K

0.1U_0402_10V6K

4.7U_ 0603_6.3V
PLACE C1139, C1140

120
125

102
103
122
2 AS CLOSE AS U44

26
56

15
14
91
92

67
73
79
81
1 1

7
U44

C337

C343

C345
D PLACE C1141, C1142 AS CLOSE AS U44 D

PCI_VCC
PCI_VCC

AVCC
AVCC
AVCC
AVCC
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8

VCC3.3
VCC3.3
VCC3.3
VCC3.3
17 PCI_AD[0..31] 2 2
PCI_AD31 19
PCI_AD30 AD31 R542 5.9K_0402_1%
20
PLACE C1136, C1137, C1138 PCI_AD29 AD30
21 78 1 2
AS CLOSE AS U44 PCI_AD28 AD29 REF
22
PCI_AD27 AD28 OZ129XI
23 83
PCI_AD26 AD27 XI OZ129XO +3VS
24 84

+1.8VS_CR
PCI_AD25
PCI_AD24
PCI_AD23
25
27
AD26
AD25
AD24
OZ129 XO

TPBIAS
76 IEEE1394_TPBIAS0
IEEE1394_TPAP0
29 75
PCI_AD22 AD23 TPA+ IEEE1394_TPAN0 R594
30 AD22 TPA- 74
1

PCI_AD21 31 72 IEEE1394_TPBP0 22K_0402_5%

R282 PCI_AD20 AD21 TPB+ IEEE1394_TPBN0
32 71
470_0402_5% PCI_AD19 AD20 TPB-
34
PCI_AD18 AD19
35
PCI_AD17 AD18 MC_3V#
36 4 Layout Note: Place close to
2

PCI_AD16 AD17 MC_3V# SDCLK_MSCLK

37 113
PCI_AD15 47
AD16 SD_CLK/MS_CLK
111 SDD3 OZ129 and Shield GND.
AD15 SD_D3
1

D PCI_AD14 SDD2
48 112
SUSP Q21 PCI_AD13 AD14 SD_D2 SDD1 C643
2 49 107
SSM3K7002FU_SC70-3 PCI_AD12 AD13 SD_D1 SDD0 OZ129XI
G 50 108 2 1
PCI_AD11 AD12 SD_D0 SD_CMD
S 51 110
3

PCI_AD10 AD11 SD_CMD SD_WP 15P_0402_50V8J

52 117
AD10 SD_WP

2
PCI_AD9 53 114 SDCD# X3
PCI_AD8 AD9 SD_CD#
54
PCI_AD7 AD8 CLK_PCI_CB
57
PCI_AD6 AD7 XDD7_MSD1 24.576MHz_16P_3XG-24576-43E1
58 95

1
PCI_AD5 AD6 MS_D1/XD_D7 XD_D6 C635
59 AD5 XD_D6 93

1
10_0402_5%~D
PCI_AD4 60 89 XD_D5 2 1 OZ129XO
PCI_AD3 AD4 XD_D5 XD_D4 R595
61 87
PCI_AD2 AD3 XD_D4 XDD3_MSBS @ 15P_0402_50V8J
62 88
C PCI_AD1 AD2 MS_BS/XD_D3 XDD2_MSD0 C
63 AD1 MS_D0/XD_D2 90
PCI_AD0 64 94 XDD1_MSD2

2
AD0 MS_D2/XD_D1 XDD0_MSD3
96
MS_D3/XD_D0 XDCE#
119
PCI_CBE#3 XD_CE# XDRB#
17 PCI_CBE#3 28 100
C/BE3# XD_RB#

4.7P_0402_50V8C
PCI_CBE#2 38 118 XDCLE
17 PCI_CBE#2 C/BE2# XD_CLE +3VS_CR
PCI_CBE#1 46 109 XDALE 1
17 PCI_CBE#1 C/BE1# XD_ALE
PCI_CBE#0 55 105 XDWE#
17 PCI_CBE#0 C/BE0# XD_WE#
101 XDRE# C676
R514 XD_RE# XDWP# @ SDCLK
98
PCI_AD21 CBS_IDSEL XD_WPO# MSCD# 2 +3VS
1 2 5 99 1
CLK_PCI_CB IDSEL MS_CD# XDCD#
16 CLK_PCI_CB 45 PCI_CLK XD_CD# 97
100_0402_5% PCI_DEVSEL# 42 +3VS_CR C324
17 PCI_DEVSEL# DEVSEL#

1
PCI_FRAME# 39 10P_0402_50V8J
17 PCI_FRAME# FRAME# 2
PCI_IRDY# 40 85 R241 @
17 PCI_IRDY# IRDY# PHY_TEST0

3
S

4.7U_ 0603_6.3V

0.1U_0402_10V6K
PCI_TRDY# 41 86 470_0402_5%
17 PCI_TRDY# TRDY# PHY_TEST1 G
PCI_STOP# 43 MC_3V# 2 U45 1
17 PCI_STOP# STOP#
PCI_PAR 44 AP2301GN_SOT23-3
17 PCI_PAR

2
PCI_REQ0# PAR C323 C326
17 PCI_REQ0# 17 2 D

1
PCI_GNT0# PCI_REQ# NC
17 PCI_GNT0# 18 PCI_GNT# NC 8

1
PCI_RST# MMCD4 D 2 MSCLK
17,21 PCI_RST# 1 PCI_RST# NC 9
PCI_PIRQG# 11 10 MMCD5 1 2 MC_3V# 1
17 PCI_PIRQG# INTA# NC
CB_PME# 3 13 Q82 G
28 CB_PME# PME# NC
6 126 MMCD6 C332 S SSM3K7002FU_SC70-3 C325

3
@ R524 2 CLKRUN# NC
1 100K_0402_5% 127 MMCD7 1U 10V Z Y5V 0603 10P_0402_50V8J
NC 2 @ 2
106 128
R525 1 MEDIA_LED NC
19,28 PCI_CLKRUN# 2 0_0402_5%~D
AGND
AGND
AGND
AGND
AGND
AGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

LED behave: OZ129TN_LQFP128_14X14 +3VS_CR +3VS_CR

12
16
33
66
68
104
115
116
121
123
124

82
80
77
70
69
65

Idel ---------> low

B L16 J8IN1 B
Accress data --> always high
2 1 3 21
0_0603_5% XD-VCC SD-VCC
28
XDD0_MSD3 R529 33_0402_5% XDD0 MS-VCC
1 2 32
XDD1_MSD2 R540 33_0402_5% XDD1 XD-D0 SDCLK R227 22_0402_5% SDCLK_MSCLK
1 2 10 XD-D1 7 IN 1 CONN SD_CLK 20 1 2
XDD2_MSD0 R544 1 2 33_0402_5% XDD2 9 14 SDDAT0 R535 1 2 33_0402_5% SDD0
XDD3_MSBS R553 33_0402_5% XDD3 XD-D2 SD-DAT0 SDDAT1 R530 33_0402_5% SDD1
1 2 8 12 1 2
XD_D4 R528 33_0402_5% XDD4 XD-D3 SD-DAT1 SDDAT2 R229 33_0402_5% SDD2
1 2 7 30 1 2
IEEE1394_TPBIAS0 XD_D5 R531 33_0402_5% XDD5 XD-D4 SD-DAT2 SDDAT3 R557 33_0402_5% SDD3
1 2 6 XD-D5 SD-DAT3 29 1 2
XD_D6 R536 1 2 33_0402_5% XDD6 5 27 SDDAT4 R519 1 2 33_0402_5% MMCD4
XD-D6 SD-DAT4
1U_0603_10V4Z

XDD7_MSD1 R541 1 2 33_0402_5% XDD7 4 23 SDDAT5 R518 1 2 33_0402_5% MMCD5

XD-D7 SD-DAT5
1

1
56.2_0402_1%

56.2_0402_1%

1 18 SDDAT6 R517 1 2 33_0402_5% MMCD6

XDWE# R526 33_0402_5% XDWE SD-DAT6 SDDAT7 R516 33_0402_5% MMCD7
1 2 34 16 1 2
R547 R555 C656 XDWP# R230 33_0402_5% XDWP XD-WE SD-DAT7
1 2 33
XDALE R231 33_0402_5% XD_ALE XD-WP SDCD R551 1
1 2 35 1 2 33_0402_5% SDCD#
2 XDCD# R234 33_0402_5% XDCD XD-ALE SD-CD SDWP R545 1
1 2 40 2 2 33_0402_5% SD_WP
2

XDRB# R515 33_0402_5% XDRB XD-CD SD-WP SDCMD R522 1 SD_CMD

1 2 39 25 2 33_0402_5%
XDRE# R222 33_0402_5% XDRE XD-R/B SD-CMD
1 2 38
XDCE# R233 33_0402_5% XDCE XD-RE MSCLK R228 1 SDCLK_MSCLK
1 2 37 26 2 22_0402_5%
IEEE1394_TPAP0 XDCLE R232 33_0402_5% XD_CLE XD-CE MS-SCLK MSBS R527 1
IEEE1394_TPAP0 30 1 2 36 13 2 33_0402_5% XDD3_MSBS
XD-CLE MS-BS MSINS R221 1
22 2 33_0402_5% MSCD#
IEEE1394_TPAN0 MS-INS
IEEE1394_TPAN0 30
11 17 MSDATA0 R534 1 2 33_0402_5% XDD2_MSD0
IEEE1394_TPBP0 7in1-GND MS-DATA0 MSDATA1 R539 1 XDD7_MSD1
IEEE1394_TPBP0 30 31 15 2 33_0402_5%
7in1-GND MS-DATA1 MSDATA2 R543 1
41 19 2 33_0402_5% XDD1_MSD2
IEEE1394_TPBN0 7in1-GND MS-DATA2 MSDATA3 R552 1
IEEE1394_TPBN0 30 42 7in1-GND MS-DATA3 24 2 33_0402_5% XDD0_MSD3
1

1
56.2_0402_1%

56.2_0402_1%

TAITW_R015-A10-LM
R559 R570
A A
2

2
270P_0402_50V7K

2 5.1K_0402_1%

2
C659 R571
1
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2007/09/01 Deciphered Date 2008/09/01
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
OZ129_Card Reader / 1394
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Layout Note: Place close to OZ129 Chipset. Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 25 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

D D

Express Card Power Switch Express Card

+1.5VS_CARD +3VS_CARD
(1A) (1.5A)
JEXP1

1
R480 2 USB20_N5_R GND
19 USB20_N5 1 0_0402_5% 2
USB_D-

C288

C287

C291

C286

C273

C274
R481 2 1 0_0402_5% USB20_P5_R 3
19 USB20_P5 USB_D+
1 1 1 1 1 1 EXPR_CPUSB# 4
CPUSB#
5
RSV
6
+3VS RSV

10U_0805_6.3V6M
+3VS +1.5VS 19 ICH_SMB_CLK R172 2 1 0_0402_5% 7
2 2 2 2 2 2 SMB_CLK

10U_0805_6.3V6M
0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N
19 ICH_SMB_DATA R174 2 1 0_0402_5% 8
SMB_DATA
+1.5VS_CARD 9
C +1.5V C
10
+1.5V
C276

C275

C303

R175 1 2 0_0402_5% 11
19,27 ICH_PCIE_WAKE# WAKE#
1 1 1 +3VS_CARD_AUX 12
PERST# +3.3VAUX
13
PERST#
+3VS_CARD 14
U46 +3.3V
15
2 2 2 +3.3V
0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

12 11 16 EXPR_CARD_REQ# R177 1 2 0_0402_5% 16

1.5Vin 1.5Vout CPUSB# R181 1 CLKREQ#
14 13 2 0_0402_5% 17
1.5Vin 1.5Vout CPPE#
16 CLK_PCIE_EXPR# 18
REFCLK-
16 CLK_PCIE_EXPR 19
+3VS_CARD_AUX REFCLK+
2 3 20
3.3Vin 3.3Vout PCIE_RXN2 GND
4 5 19 PCIE_RXN2 21
3.3Vin 3.3Vout PCIE_RXP2 PERn0
(0.5A) 19 PCIE_RXP2 22
PERp0
17 15 23
AUX_IN AUX_OUT PCIE_TXN2 GND
19 PCIE_TXN2 24
PETn0

0.1U_0402_16V7K~N C284

0.1U_0402_16V7K~N C283
PLT_RST# 6 19 PCIE_TXP2 25
7,17,19,22,27,28,33 PLT_RST# SYSRST# OC# 19 PCIE_TXP2 PETp0
1 1 26
PERST# GND
28,31,42,45 SUSP# 1R157 20_0402_5% 20 8
SHDN# PERST#
27
GND
28,31,42,45 SUSP# 1 16 28
STBY# NC 2 2 GND
29 31
GND GND
+3VALW @ 1 R171 2 100K_0402_5% CPUSB# 10 7 30 32
CPPE# GND GND GND
@ 1 R169 2 100K_0402_5% EXPR_CPUSB# 9 FOX_1CX41202-KH_26P
CPUSB# conn@
18
RCLKEN

P2231NF_QFN20
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Express Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4121P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 26 of 51
5 4 3 2 1
 A B C D E

+3VS

Mini-Express Card---WLAN 0.01U_0402_16V7K~N 4.7U_ 0603_6.3V Robson

1 1 1
+1.5VS +3VS C678 C365 C368 +1.5VS +3VS
19,26 ICH_PCIE_WAKE#
JMINI1
1 2 2 2 2
CH_DATA @ R3151 0_0402_5% 1 2 JMINI3
30 CH_DATA 2 3 4
CH_CLK @ R3161 0_0402_5% 3 4 0.1U_0402_16V4Z~N
30 CH_CLK 2 5 6 1 2
5 6 1 2
16 MCARD_REQ# 7 8 3 4
7 8 3 4
9 10 5 6
9 10 5 6
16 CLK_PCIE_MCARD# 11 12 16 ROBSON_REQ# 1 2 ROB_REQE# 7 8 1 2 LPC_FRAME# 18,28
11 12 @ R199 0_0402_5% 7 8 R168 LPC_AD3
16 CLK_PCIE_MCARD 13 14 9 10 1 0_0402_5%
2 @
1 13 14 CLK_PCIE_Rob# 9 10 R186 LPC_AD2 1
15 16 16 CLK_PCIE_Rob# 11 12 1 0_0402_5%
2 @
15 16 CLK_PCIE_Rob 11 12 R187
17 18 1 2 +3VS 16 CLK_PCIE_Rob 13 14 1 0_0402_5%
2 LPC_AD1
@
17 18 WL_DIS# R619 10K_0402_5% 13 14 R188 LPC_AD0
19 20 15 16 1 0_0402_5%
2 @
R628 0_0402_5% 19 20 WL_DIS# 28 PLT_RST# 1 15 16 R185 0_0402_5% @
21 22 2 17 18 LPC_AD[0..3] 18,28
PCIE_RXN4 1 21 22 PLT_RST# 7,17,19,22,26,28,33 17 18
19 PCIE_RXN4 2PCIE_C_RXN4 23 24 1 2 +3VALW 16 CLK_DEBUG_PORT
@ R189 0_0402_5% 19 20
PCIE_RXP4 1 23 24 19 20
19 PCIE_RXP4 2PCIE_C_RXP4 25 26 R290 0_0402_5% @ R178 0_0402_5% 21 22
R629 0_0402_5% 25 26 PCIE_RXN1 1 21 22 PLT_RST# 7,17,19,22,26,28,33
27 28 19 PCIE_RXN1 2 PCIE_C_RXN1 23 24
27 28 PCIE_RXP1 PCIE_C_RXP1 23 24
29 30 19 PCIE_RXP1 1 2 25 26
PCIE_TXN4 29 30 @ R176 0_0402_5% 25 26
19 PCIE_TXN4 31 32 27 28
PCIE_TXP4 31 32 27 28
19 PCIE_TXP4 33 34 29 30
33 34 PCIE_TXN1 29 30
35 36 19 PCIE_TXN1 31 32
35 36 PCIE_TXP1 31 32
37 38 19 PCIE_TXP1 33 34
37 38 33 34
39 40 35 36
39 40 35 36
41 42 37 38
41 42 WLAN_LED# 37 38
43 44 WLAN_LED# 29 39 40
43 44 39 40
45 46 41 42
45 46 41 42
47 48 R633 43 44
47 48 43 44
49 50 45 46
49 50 45 46
51 52 1 2 +3VS 47 48
51 52 47 48
49 50
49 50
53 54 51 52
GND1 GND2 100K_0402_5% 51 52
53 54
+1.5VS FOX_AS0B226-S40N-7F GND1 GND2

0.01U_0402_16V7K~N FOX_AS0B226-S40N-7F

1 1
C308 C304

2 2
2 +1.5VS +3VS 2
0.01U_0402_16V7K~N
0.01U_0402_16V7K~N

1 1 2 2 1
@ C306 @ C298
@C285 @ C310 @C313
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_1206_16V4Z
2 2 1 1 2

0.01U_0402_16V7K~N

Mini-Express Card---WWAN Mini-Express Card---Bluetooth

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 27 of 51
A B C D E

GRATIS - FOR FREE

hexainf@hotmail.com
 L10
+3VALW +EC_AVCC 2 1
+EC_AVCC
1
+3VALW
2 FBM-11-160808-601-T_0603
Board ID +3VALW
C271
C278
1 1 1 1 1 1 1000P_0402_50V7K~N 0.1U_0402_16V4Z~N

0.1U_0402_16V4Z~N
C277

0.1U_0402_16V4Z~N
C300

0.1U_0402_16V4Z~N
C302

0.1U_0402_16V4Z~N
C289

1000P_0402_50V7K~N
C296

1000P_0402_50V7K~N
C297

1
ECAGND 2 12 1 2006-01-27 change Brd ID
FBM-11-160808-601-T_0603 L9
2 2 2 2 2 2
Ra 100K_0402_5%
R153

2
AD_BID
1

111
125

1
22
33
96

67
9
U28 C272
Rb 100K_0402_5% 0.1U_0402_16V4Z

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
CLK_PCI_EC R152 2

2
1

R183 0_0402_5%
R182 GATEA20 1 21 1 2
18 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 15
KB_RST# 2 23 BEEP# M/B rev:0.1; 0.2; 0.3; 1.0
18 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 24
@ 10_0402_5% SERIRQ 3 26 W_DISABLE#
19 SERIRQ
LPC_FRAME# 4
SERIRQ# FANPWM1/GPIO12
27 ACOFF
W_DISABLE# Voltage:0.0; 0.4; 0.8; 1.0
18,27 LPC_FRAME# ACOFF 40
2

LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13

1 18,27 LPC_AD3 5
@ C301 LPC_AD2 LAD3 C281 1 ECAGND
18,27 LPC_AD2 7 PWM Output 2 100P_0402_50V8K
LPC_AD1 LAD2 BATT_TEMP
18,27 LPC_AD1 8 63 BATT_TEMP 47
15P_0402_50V8J LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP
LAD0 LPC & MISC
18,27 LPC_AD0 10 64 BATT_OVP 47
2 BATT_OVP/AD1/GPIO39 ADP_I
65 ADP_I 40 C279
CLK_PCI_EC ADP_I/AD2/GPIO3A AD_BID
+3VALW 16 CLK_PCI_EC 12
PCICLK AD Input AD3/GPIO3B
66
R173 PLT_RST# 13 75 MIC_DIAG BATT_OVP 1 2 ECAGND
7,17,19,22,26,27,33 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 MIC_DIAG 30
1 2 EC_RST# 37 76 POW_MON
+3VALW ECRST# SELIO2#/AD5/GPIO43 POW_MON 46
EC_SCI# 20
19 EC_SCI# SCI#/GPIO0E 100P_0402_50V8K
2

47K_0402_5% PCI_CLKRUN# 38
19,25 PCI_CLKRUN# CLKRUN#/GPIO1D
2 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 15
R195 C293 70 EN_DFAN1
KSI[0..7] EN_DFAN1/DA1/GPIO3D EN_DFAN1 4
10K_0402_5% 0.1U_0402_16V4Z DA Output 71 IREF
29 KSI[0..7] IREF/DA2/GPIO3E IREF 40
KSI0 55 72 CHGVADJ_EC 1 2 CHGVADJ 40
1

EC_PME# 1 KSO[0..15] KSI1 KSI0/GPIO30 DA3/GPIO3F R150 0_0402_5%

1 2 56
22 PCIE_PME#
R190
@ R193
0_0402_5%
0_0402_5%
29 KSO[0..15]
KSI2
KSI3
KSI4
57
58
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33 PSCLK1/GPIO4A
83 EC_MUTE#
BIST
EC_MUTE# 24
C280
+3VALW
SPI Flash (8Mb*1)
25 CB_PME# 1 2 59 84 BIST 15 1 2
+5VALW KSI5 KSI4/GPIO34 PSDAT1/GPIO4B VGA_ON
60 85 VGA_ON 44
KSI5/GPIO35 PSCLK2/GPIO4C

2
KSI6 61 PS2 Interface 86 LCD_DET# 0.1U_0402_16V4Z~N
KSI6/GPIO36 PSDAT2/GPIO4D LCD_DET# 15
EC_SMB_DA1 R479 2 1 4.7K_0402_5% KSI7 62 87 TP_CLK 20mils
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 29
KSO0 39 88 TP_DATA U29
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 29
EC_SMB_CK1 R476 2 1 4.7K_0402_5% KSO1 40 R162 8 4
+3VS KSO2 KSO1/GPIO21 10K_0402_5% VCC VSS
41

1
KSO3 KSO2/GPIO22 SPI_PULLDOWN 2 R156
42 97 1 4.7K_0402_5% 3
EC_SMB_DA2 R154 2 KSO4 KSO3/GPIO23 SDICS#/GPXOA00 EN_WOL# W
1 4.7K_0402_5% 43 98 EN_WOL# 22
KSO5 KSO4/GPIO24 SDICLK/GPXOA01 STB_SB
KSO5/GPIO25 Int. K/B
44 99 STB_SB 31 7
EC_SMB_CK2 R148 2 KSO6 SDIDO/GPXOA02 VGATE HOLD
1 4.7K_0402_5% 45 109 VGATE 19,46
KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 FSEL#SPICS# 2 SPI_CS#
46
KSO7/GPIO27 SPI Device Interface 1 1
S
30 MIC_DIAG MIC_DIAG 1R43 2 10K_0402_5% KSO8 47 R155 15_0402_5%
KSO9 KSO8/GPIO28 FRD#SPI_SO SPI_CLK SPI_CLK_R
48 119 2 1 6
ESB_CLK R192 2 KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI C
1 4.7K_0402_5% 49 120 R158 15_0402_5%
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK FWR#SPI_SI SPI_SI SPI_SO 2
50 SPI Flash ROM 126 2 1 5 2 1 FRD#SPI_SO
ESB_DAT R191 2 KSO12 KSO11/GPIO2B SPICLK/GPIO58 FSEL#SPICS# D Q
1 4.7K_0402_5% 51 128 R165 15_0402_5% R160 15_0402_5%
KSO13 KSO12/GPIO2C SPICS# 1MX8 W25X80-VSS-IG SOIC 8P
52
MSEN# @ R635 2 KSO14 KSO13/GPIO2D
1 4.7K_0402_5% 53
KSO15 KSO14/GPIO2E TS_RST#
54 73 TS_RST# 29
WL_DIS# KSO15/GPIO2F CIR_RX/GPIO40 MSEN#
27 WL_DIS# 81 74 MSEN# 15
+3VALW BT_DIS# KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG
30 BT_DIS# 82 89 FSTCHG 40
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHG_LED#
90 BATT_CHG_LED# 29
JECDB1 BATT_CHGI_LED#/GPIO52 CAPSLED# @ C282
91 CAPSLED# 29
EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_LOW_LED# ACIN
1 47 EC_SMB_CK1 77 GPIO 92 BATT_LOW_LED# 29 1 2 2 1 1 2 SPI_CLK_R
1 EC_SMB_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 SCRLED# C299 100P_0402_50V8J @ R163 15_0402_5%
2 47 EC_SMB_DA1 78 93 SCRLED# 29
E51_TXD 2 EC_SMB_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON 0.1U_0402_16V4Z~N
3
3 4,29,34 EC_SMB_CK2 79
SCL2/GPIO46 SM Bus SYSON/GPIO56
95 SYSON 31,43
4 4,29,34 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON
4 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 46
127 ACIN
AC_IN/GPIO59 ACIN 19,39,40
ACES_85205-0400
CONN@
6 SLP_S3# 100 EC_RSMRST#
Wireless_BTN
19 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 19
14 SLP_S5# 101 EC_LID_OUT#
+5VS 19 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 19 +3VS SW2
15 EC_SMI# 102 EC_ON
19 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 29 SC12P-D-V-TR DIPTRONICS 1P2T_3P
R145 16 LID_SW# 103 EC_SWI#
LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# 19
4.7K_0402_5% ESB_CLK R1841 2 0_0402_5% 17 104 ICH_PWROK
29 ESB_CLK SUSP#/GPIO0B ICH_PWROK/GPXO06

1
TP_DATA 1 2 29 ESB_DAT ESB_DAT 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 15

3
TP_CLK 1 2 EC_PME# 19 GPIO 106 LCD_TEST_EN
EC_PME#/GPIO0D WL_OFF#/GPXO09 LCD_TEST_EN 15
4.7K_0402_5% 15,33 VGA_LVDDEN VGA_LVDDEN 1R180 20_0402_5% VGA_LVDD_EN 25 107 LAN_CABDT R318
LAN_CABDT 22

3
R146 FAN_SPEED1 EC_THERM#/GPIO11 GPXO10 PSID_DISABLE# 100K_0402_5%
4 FAN_SPEED1 28 108
GMCH_LVDDEN 1R179 FAN_SPEED1/FANFB1/GPIO14 GPXO11 PSID_DISABLE# 39
9,15 GMCH_LVDDEN 2 0_0402_5% GMCH_LVDD_EN 29

2
E51_TXD FANFB2/GPIO15
30
VGA_THER# EC_TX/GPIO16 SLP_S4#
33 VGA_THER# 31 110 SLP_S4# 19
EC_RX/GPIO17 PM_SLP_S4#/GPXID1

2
ON_OFF 32 112 EC_ENBKL
29 ON_OFF ON_OFF/GPIO18 ENBKL/GPXID2
PWR_SUS_LED# 34 114 USB_EN @ R320
29 PWR_SUS_LED# PWR_LED#/GPIO19 GPXID3 USB_EN 30
NUMLED# 36 GPI 115 EC_THERM# 1.5M_0402_5%
29 NUMLED# NUMLED#/GPIO1A GPXID4 EC_THERM# 4,19
116 SUSP# W_DISABLE# W_DISABLE#
GPXID5 PBTN_OUT# SUSP# 26,31,42,45
117

1
+3VALW XCLKO 1 R170 GPXID6 PBTN_OUT# 19
2 XCLKI 118 PS_ID
@ 20M_0603_5% XCLKI GPXID7 PS_ID 39
122
XCLKO XCLK1
123 124 1 2
XCLK0 V18R C295 0.1U_0402_16V4Z
AGND

EC_MUTE# 1 2
GND
GND
GND
GND
GND

10K_0402_5%
R147 C2921 2
C294 C290 KB926QFC0_LQFP128
TPM 1.2 Conn
11
24
35
94
113

69
1

4
15P_0402_50V8J

15P_0402_50V8J

4.7U_ 0603_6.3V CLOSE TO EC

OUT
IN

JTPM1
ECAGND
LPC_FRAME# 1 2 LPC_AD0
GND1 RES0 LPC_AD1
NC

NC

7,17,19,22,26,27,33 PLT_RST# 3 4
SERIRQ IAC_SDATA_OUT RES1 LPC_AD2
5 6
PCI_CLKRUN# GND2 3.3V LPC_AD3
7 8
2

IAC_SYNC GND3
+3VS 12mA 9
IAC_SDATA_IN GND4
10 CLK_PCI_TPM 16
X2 ICH_PWROK 1 2 +3VALW 11 12
+3VALW PM_PWROK 7,19 IAC_RESET# IAC_BITCLK
R166 0_0402_5%
Q1 32.768KHZ_12.5P_1TJS125BJ2A251
APX9132ATI-TRL_SOT23-3

GND
GND
GND
GND
GND
GND
LID_SW# 3 2
GND

VOUT VDD EC_ENBKL D1 @ ACES_88018-124L

13
14
15
16
17
18
CH751H-40_SC76 CONN@
9 GMCH_ENBKL 2 R34 1 1 2 DISPOFF# DISPOFF# 15
1

UMA@ 0_0402_5%
33 G7X_ENBKL 2 R36 1
2

VGA@ 0_0402_5%
100K_0402_5%

R35

REED Switch R35

Security Classification Compal Secret Data Compal Electronics, Inc.
UMA@
1

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/BIOS/TPM
2.2K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
VGA@ Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 28 of 51
 A B C D E

+3VALW
INT_KBD CONN. JKB1
KSO8 C599 100P_0402_25V8K KSI7 C597 100P_0402_25V8K

KSI[0..7] KSI0 1 KSI3 C593 100P_0402_25V8K KSI6 C596 100P_0402_25V8K

Power Button 28 KSI[0..7]
KSI1 2
1
2

2
KSO[0..15] KSI2 KSO9 C600 100P_0402_25V8K KSI5 C595 100P_0402_25V8K

100K_0402_5%
28 KSO[0..15] 3
KSI3 3
4 4 C592 100P_0402_25V8K C580 100P_0402_25V8K

R151
KSI4 5 KSI2 KSO0
KSI5 5
6
KSI6 6 KSI1 C591 100P_0402_25V8K KSO1 C581 100P_0402_25V8K
7

1
D8 KSI7 7
8
KSO0 8 KSO10 C601 100P_0402_25V8K KSO2 C582 100P_0402_25V8K
2 ON_OFF 28 9
PWR_ON-OFF_BTN# KSO1 9
1 10
51ON# KSO2 10 KSO11 C602 100P_0402_25V8K KSI4 C594 100P_0402_25V8K
3 51ON# 39 11 11
KSO3 12
1 KSO4 12 KSI0 C590 100P_0402_25V8K KSO3 C583 100P_0402_25V8K 1
13
DAN202U_SC70 KSO5 13
14
+3VALW KSO6 14 KSO12 C603 100P_0402_25V8K KSO4 C584 100P_0402_25V8K
15
15

1
2 KSO7 16
KSO8 16 KSO13 C604 100P_0402_25V8K KSO5 C585 100P_0402_25V8K
17
17

2
C270 D6 KSO9 18 18

1
@ R164 1000P_0402_50V7K~N RLZ20A_LL34 KSO10 19 KSO14 C606 100P_0402_25V8K KSO6 C586 100P_0402_25V8K
4.7K_0402_5% 1 KSO11 19
20

2
KSO12 20 KSO15 C605 100P_0402_25V8K KSO7 C587 100P_0402_25V8K
21
KSO13 21
22

1
R1611 22
28 EC_ON
EC_ON 2 20_0402_5% KSO14 23
KSO15 23
24
25
24
25
For EMI
26
Q14 26
27

3
SSM3K7002F 1N SC59-3 G1
28 G2
ACES_88514-2601_26P
CONN@

@ SW3
SW_1BT002-0121L_4P
Function/B CONN.
PWR_ON-OFF_BTN# 3 1 POWER SWITCH 28 TS_RST#

1
4 2 R51
0_0402_5% JFN1
2 1 2
5
6

SCRLED# 1
28 SCRLED# 2

2
FOR ENE CAPSLED# 2
28 CAPSLED# 3
L2 2 NUMLED# 3
28 ESB_CLK 1 28 NUMLED# 4
MBK1005801YZF 0402 R_TS_RST# 4
5
L3 2 PWR_SUS_LED# 5
28 ESB_DAT 1 6
MBK1005801YZF 0402 6
7
BT_LED# 7
30 BT_LED# 8
8
9
Regulator for ENE sensor 4,28,34 EC_SMB_CK2
4,28,34 EC_SMB_DA2
@ R54 1
@ R53 1
2 0_0402_5%
2 0_0402_5%
CK2
DA2
10
11
9
10
FN_WIFI_LED# 11
12
FOR CYPRESS PWR_ON-OFF_BTN# 12
13
R167 1 0_0402_5% 13
+5VS
Adjustable Output 27 WLAN_LED# 2 +3VALW 14
14
IDE_ACT_LED# 15
R42 APL5151-33BC-TRL SOT23 5P 3.3V 15
+3VS @ 1 2 16
L1 16
1 2 3 4 17
SHDN# BP +3VS_FUN BK1608LL121-T 0603 GND
18
10K_0603_1% GND
2 GND CK2 DA2 ACES_88512-1641_16P
1 5 CONN@ +3VALW
1 VIN VOUT +3VS_FUN

1
C22
D2

1
U54 2 R52
1U_0402_6.3V4K R50 3
2 C21 @ 10_0402_5% +3VS PWR_ON-OFF_BTN# 1
.33U 10V \_0603_+-10% @ 10_0402_5% 2

2
1 C23
1

2
1 @ C48 2 1
@ C47 0.1U_0402_16V4Z DAN217_SC59

5
15P_0402_50V8J U31 @
15P_0402_50V8J 2 SATA_LED# 2

P
2 18 SATA_LED# B
4 IDE_ACT_LED#
3 ODD_ACT_LED# Y 3
21 ODD_ACT_LED# 1 A

G
AS CLOSE AS JFN1 NC7SZ08P5X_NL_SC70-5

3
Touch PAD/B CONN. TP/B
CONN@
TO M/B
+5VS
ACES_88514-0441_4P
BAT_LOW_LED +5VALW 6
G2
5
D13 G1
4
BATT_LOW_LED# 1 R630 4
28 BATT_LOW_LED# 2 3 Y 1
28 TP_CLK
TP_CLK 3
220_0402_5% TP_DATA 3
1 28 TP_DATA 2
BATT_CHG_LED# 1 R631 C80 2
28 BATT_CHG_LED# 2 2 1 1
220_0402_5% B 0.01U_0402_16V7K
12-22/Y2BHC-A30/2C_Y/B~D 2 JP2
BATT_CHG_LED

C81

C82
1 1
BLUE IN RIGHT SIDE @ @
D14
12-21-BHC-ZL1M2RY-2C BLUE

100P_0402_25V8K

100P_0402_25V8K
2 2

28 PWR_SUS_LED#
PWR_SUS_LED#2 1 1 R632 2
220_0402_5%

4 PWR_SUS_LED 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_OK/BTN/KB/TP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 29 of 51
A B C D E

GRATIS - FOR FREE

hexainf@hotmail.com
 +USB_AS
W=60mils

+5VALW +USB_AS CM1293-04SO_SOT23-6 JUSBP1

4 3 1
USB_P1- USB_P0+ 19 USB20_N0 4 3 USB_P0- VCC
1 4 USB20_N0 2
U32 CH1 CH4 USB20_P0 USB_P0+ USB_N
80 mils 1
GND OUT
8
19 USB20_P0
1
1 2
2
3
4
USB_P
GND
2 7 5
IN OUT L8 WCM-2012-900T_4P GND
3 6 2 5 +USB_AS 6
USB_EN# IN OUT Vn Vp GND
1 4 5 USB_OC#0 19 2 1 7
C85 EN# OC# R132 0_0402_5% GND
8
GND

1
RT9711PS SO 8P 2 @ 1
0.1U_0402_16V4Z @ R65 USB_P1+ 3 6 USB_P0- R133 0_0402_5% SUYIN_020133MR004S536ZL
2 470_0402_5% CH2 CH3 CONN@
@
D28

2
close to JUSBP1 & JUSBP4

1
D
USB_EN# @ Q8 +USB_AS
2
SSM3K7002FU_SC70-3
W=60mils
G

1
S

3
R70 L7
100K_0402_5% JUSBP4
@ USB20_N1 3 4 1
19 USB20_N1 3 4 VCC
USB_P1- 2

2
USB_P1+ USB_N
3
+5VALW +USB_BS USB20_P1 USB_P
19 USB20_P1 2 1 4
2 1 GND
5
WCM2012F2S-900T04_0805 @ GND
6
U33 GND
80 mils 1
GND OUT
8
2
R131
1
0_0402_5%
7
8
GND
GND
2 7 2 1
IN OUT R129 0_0402_5% SUYIN_020133MR004S536ZL
3 6
IN OUT

1
1 USB_EN# 4 5 USB_OC#1 19 CONN@
C305 EN# OC# @ R200 +5VALW
RT9711PS SO 8P 470_0402_5%
0.1U_0402_16V4Z

2
2

1 2
R85
D 10K_0402_5%
USB_EN# 2 @ Q17
G SSM3K7002FU_SC70-3

1
1
S USB_EN#

3
@ R64

1
100K_0402_5% D
USB_EN Q12
28 USB_EN 2
G SSM3K7002FU_SC70-3
Felica Conn

2
S

3
CONN@
ACES_88512-0641_6P
Check Module pin define Camera Conn 1
+5VS 1
USB20_N9 2
19 USB20_N9 2
JCA1 USB20_P9 3
19 USB20_P9 3
1 4
1 +USB_AS TP2 LEC 4
2 5 8
USB20_P8 2 +USB_BS 5 G2
19 USB20_P8 3 6 7
3 6 G1
USB20_N8
4
4 W=80mils 1
JFE1
19 USB20_N8 5
L42 2 5
+5VS 1 MBK1608221YZF_0603 6
DMIC_DATA 6 @ C432
23 DMIC_DATA 7 1
L43 2 7 10U_0805_10V4Z 2
+3VS 1 MBK1608221YZF_0603 FBM-L10-160808-301_0603 8 1 470P_0402_50V7K
DMIC_CLK 8 +
23 DMIC_CLK 2 1 9 1 1
MIC_DIAG L41 9 C311 + C146 C261
28 MIC_DIAG 10
10 150U 6.3V M Y NOJ C76
11
GND 2 150U 6.3V M Y NOJ
1 1 12
L42, L43 AS CLOSE JCA1 AS POSSIBLE @ C430 @ C431 GND 2 2 2
ACES_88460-1001
AS CLOSE AS JCA1 CLOSE TO JUSBP3
2 2 L41 AS CLOSE JCA1 AS POSSIBLE
470P_0402_50V7K

100P_0402_50V 100P_0402_50V

+USB_BS
W=80mils
D27
1 3 USB20_P8 +3VS
GND IO2 JUSBP3
USB20_N8 2
IO1 VIN
4 +5VS Bluetooth 1
1
2

2
R274 IEEE1394_TPBN0 2
PRTR5V0U2X_SOT143-4 25 IEEE1394_TPBN0 3
10K_0402_5% JBT2 IEEE1394_TPBP0 3
25 IEEE1394_TPBP0 4
@ IEEE1394_TPAN0 4
1 25 IEEE1394_TPAN0 5
USB20_P7 1 IEEE1394_TPAP0 5
19 USB20_P7 2 25 IEEE1394_TPAP0 6
1

USB20_N7 2 6
19 USB20_N7 3 7
TP4 BT_ACTIVE 3 7
4 19 USB20_P2 8
4 8
27 CH_CLK 5 19 USB20_N2 9
BT_DIS# 5 9
Finger Print 28 BT_DIS# 6
6
10
10
UPEK CONN@ 27 CH_DATA 7
8
7 19 USB20_P3 11
12
11
ACES_88512-0641_6P +3VS 8 19 USB20_N3 12
29 BT_LED# 9
9
10
10
1 11 13
1 GND GND1
2 12 14
2 GND GND2
+3VS 3
3 ACES_88460-1001 ACES_87213-1200G
4
USB20_P6 4
19 USB20_P6 5 8 CONN@
USB20_N6 5 G2
19 USB20_N6 6 7
6 G1
JFP1

D3
1 3 USB20_P6
GND IO2
USB20_N6 2 4 +3VS
IO1 VIN

PRTR5V0U2X_SOT143-4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/BlueTooth/FP/Felcia/Camera
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 30 of 51
 A B C D E

+3VALW to +3VS Transfer +5VALW to +5VS Transfer +3VALW TO +3V_SB

4A
+5VALW TO +5V_SB
+3VALW +3VS +3VALW +3V_SB
B+_BIAS +5VALW +5VS
5.5A +5VALW
U35
8 1 10U_0805_10V4Z~N U36 JP5
1 D S
7 2 8 1 2 1
R482 D S D S 2 1
1 6 3 7 2
D S D S @ JUMP_43X79
5 4 1 1 1 6 3 1 R255 2
330K_0402_5% C611 D G C616 C610 C558 D S 0_0402_5%
5 4 1 1
SI4800BDY-T1-E3_SO8 D G C269 C609
2

1 2 10U_0805_10V4Z~N SI4800BDY-T1-E3_SO8 @ U37 @ Q19 1

3
S
2 2 2 10U_0805_10V4Z~N 10U_0805_10V4Z~N 10U_0805_10V4Z~N 10U_0805_10V4Z~N
8 1
RUNON 3VS_GATE 2 2 D S STB_SB#
G
AO3413_SOT23
1 2 7 2 2
D S

1
R483 1 RUNON 1 2 5VS_GATE 0.1U_0402_16V4Z~N 1 6 3 1 1
100K_0402_5% 0.1U_0402_16V4Z~N R470 D S C658 C655 R549
1 5 4 D

1
D G

1
C617 47K_0402_5% C633 +5V_SB
1

D 0.1U_0603_25V7K~N C608 R469 SI4800BDY-T1-E3_SO8 0.1U_0402_16V4Z~N 470_0402_5%

SUSP 2 0.1U_0603_50V7K~N 2 2 2
2 1.5M_0402_5% AOS 4466 @

2
G Q30 2
@ @
S SSM3K7002FU_SC70-3 @ 1 @ C350 1
3

1
D @ C348
2 STB_SB# 4.7U_0805_10V4Z~N
Q32 G 0.1U_0402_16V4Z~N
1 2 3VSB_GATE SSM3K7002FU_SC70-3 2 2
B+_BIAS @ S

3
R590 330K_0402_5%
1

1
D
STB_SB# 2 C670
G Q33 0.1U_0603_25V7K~N
2
S @

3
SSM3K7002FU_SC70-3

+5VALW

VGA Discharge circuit +1.2VS +VGA_CORE

1

R270

1
1
100K_0402_5% R377
R125
2

2 SUSP 470_0402_5% 2
25,45 SUSP
470_0402_5%

2
1

D VGA@

1 2
SUSP# 2 Q20 VGA@
26,28,42,45 SUSP#

1
G SSM3K7002FU_SC70-3 D D
2

S SUSP 2 SUSP 2
3

G G
S Q13 VGA@ S Q28 VGA@

3
R281 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
10K_0402_5%
1

Discharge circuit -1
+1.8VS
1 +1.25VS +1.8V +0.9VS +5VS +3VS +1.5VS

1
R62 R214 R61 R60 R69 R477 R194
+5VALW
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
2

2
1

VGA@
R293
1

1
D D D D D D D
100K_0402_5% 1.8VS ON# 2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 SUSP 2 SUSP 2
G G G G G G G
2

SYSON# S Q6 VGA@ S Q18 S Q5 S Q4 S Q10 S Q29 S Q16

3

3
SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
1

D
3 SYSON 2 Q22 3
28,43 SYSON
G SSM3K7002FU_SC70-3
2

S
3

R279
10K_0402_5% +1.8V to +1.8VS Transfer
1

+1.8V +1.8VS 4.7A

B+_BIAS
+5VALW U41
8 1 10U_0805_10V4Z~N
D S

47K_0402_5%
7 2
D S
2

R74
1 6 3
R144 VGA@ D S
5 4 1 1
100K_0402_5% C83 D G C78 C77
SI4800BDY-T1-E3_SO8 VGA@

1
2 10U_0805_10V4Z 0.1U_0402_16V4Z~N
1

+3VALW VGA@ 2 2
VGA@ VGA@
STB_SB#
+5VS
1

D
STB_SB 2 R73 1.8VS ON 1 2 1.8VS_GATE
28 STB_SB
1

G Q15 R71 1
S R72 100K_0402_5% 100K_0402_5%
3
1

SSM3K7002FU_SC70-3 VGA@ C84

2

1
R159 100K_0402_5% VGA_PWGOD# D 0.1U_0603_25V7K~N
100K_0402_5% VGA_PWGOD# 1 2 1.8VS ON# 2 2
2

D
VGA@ VGA@ R63 0_0402_5% G Q9
4 VGA_PWGOD 2 Q7 S SSM3K7002FU_SC70-3 4
44 VGA_PWGOD
2

3
VGA@ G SSM3K7002FU_SC70-3 SUSP 1 2 VGA@
S @ R66 0_0402_5%
3

VGA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4121P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 31 of 51
A B C D E

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

D D

FD1 FD2 FD3 FD4 FD5 FD6

FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL
@ @ @ @ @ @
1

1
H7 H8 H9 H10 H11 H12 H29 H15 H16 H20 H21 H23 H22
H_3P0 @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA
1

1
H17 H18 H25 H27 H28
@ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_3P2
1

1
C C
H30
@ HOLEA
H_3P1
1

H26
@ HOLEA
H_3P7
1

H3 H4 H5 H6
@ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_4P2
1

H1 H2
@ HOLEA @ HOLEA
B H_4P5 B
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screws
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 32 of 51
5 4 3 2 1
 5 4 3 2 1

9 PEG_NRX_GTX_P[0..15] PEG_NRX_GTX_P[0..15]
U38A
9 PEG_NRX_GTX_N[0..15] PEG_NRX_GTX_N[0..15] HDMI
PEG_NTX_GRX_P0 AF1 Part 1 of 5 A9
PEG_NTX_GRX_N0 PEX_RX0 GPIO0
AG2 D9
PEG_NTX_GRX_P[0..15] PEG_NTX_GRX_P1 PEX_RX0_N GPIO1 NV_INVTPWM
9 PEG_NTX_GRX_P[0..15] AG3 A10 PAD TP49
PEG_NTX_GRX_N1 PEX_RX1 GPIO2 VGA_LVDDEN
AG4 B10 VGA_LVDDEN 15,28
PEG_NTX_GRX_N[0..15] PEG_NTX_GRX_P2 PEX_RX1_N GPIO3 G7X_ENBKL
9 PEG_NTX_GRX_N[0..15] AF4 C10 G7X_ENBKL 28
PEG_NTX_GRX_N2 PEX_RX2 GPIO4
AF5 C12
PEG_NTX_GRX_P3 PEX_RX2_N GPIO5 VGA@ R417 1
AG6 B12 2 2K_0402_5% +3VS
PEG_NTX_GRX_N3 PEX_RX3 GPIO6
AG7 A12
PEG_NTX_GRX_P4 PEX_RX3_N GPIO7 THER_ALERT# For Internal Thermal
AF7 A13 THER_ALERT#
PEG_NTX_GRX_N4 PEX_RX4 GPIO8 R134 2
AF8 B13 1 10K_0402_5% +3VS Sensor
D PEG_NTX_GRX_P5 PEX_RX4_N GPIO9 VGA@ D
AG9 B15
PEG_NTX_GRX_N5 PEX_RX5 GPIO10 VGA_THER#
AG10 A15 VGA_THER# 28
PEG_NTX_GRX_P6 PEX_RX5_N GPIO11
AF10 B16
PEG_NTX_GRX_N6 PEX_RX6 GPIO12
AF11
PEG_NTX_GRX_P7 PEX_RX6_N
AG12
PEG_NTX_GRX_N7 PEX_RX7 RAM_CFG0
AG13 G2 RAM_CFG0 36
PEG_NTX_GRX_P8 PEX_RX7_N MIOBD0 RAM_CFG1

DVO / GPIO
AG15 G3 RAM_CFG1 36
PEG_NTX_GRX_N8 PEX_RX8 MIOBD1
AG16 J2
PEG_NTX_GRX_P9 PEX_RX8_N MIOBD2 PCI_DEVID2
AF16 J1 PCI_DEVID2 36
PEG_NTX_GRX_N9 PEX_RX9 MIOBD3 PCI_DEVID0
AF17 K4 PCI_DEVID0 36
PEG_NTX_GRX_P10 PEX_RX9_N MIOBD4 PCI_DEVID1
AG18 K1 PCI_DEVID1 36
PEG_NTX_GRX_N10 PEX_RX10 MIOBD5
AG19 M2
PEG_NTX_GRX_P11 PEX_RX10_N MIOBD6 PCI_IOBAR R402 1 @ 2.2K_0402_5%
AF19 M1 2
PEG_NTX_GRX_N11 PEX_RX11 MIOBD7 RAM_CFG2
AF20 N1 RAM_CFG2 36
PEG_NTX_GRX_P12 PEX_RX11_N MIOBD8 RAM_CFG3
AG21 N2 RAM_CFG3 36
PEG_NTX_GRX_N12 PEX_RX12 MIOBD9
AG22 N3
PEG_NTX_GRX_P13 PEX_RX12_N MIOBD10 PCI_DEVID3
AF22 R3 PCI_DEVID3 36
PEG_NTX_GRX_N13 PEX_RX13 MIOBD11
AF23
PEG_NTX_GRX_P14 PEX_RX13_N PEX_CFG3
AG24 G4 PEX_CFG3 36
PEG_NTX_GRX_N14 PEX_RX14 MIOB_HSYNC
close to chipset AG25
PEX_RX14_N MIOB_VSYNC
F1
PEG_NTX_GRX_P15 AG26 G1 VGA termination, close chip
PEX_RX15 MIOB_DE

PCI EXPRESS
PEG_NTX_GRX_N15 AF27
PEX_RX15_N MIOB_CTL3
F2 PCI_DEVID4
PCI_DEVID4 36 PCI_IOBAR NB8M
PEG_NRX_GTX_P0 C136 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P0 AD5 R2 R399 2 1 10K_0402_5% VGA_CRT_R R387 1 2 VGA@ 150_0402_1%
PEG_NRX_GTX_N0 PEG_NRX_C_GTX_N0 PEX_TX0 MIOB_CLKIN VGA_CRT_G
C132 1 2 VGA@ 0.1U_0402_16V7K AD6
PEX_TX0_N MIOB_CLKOUT
K2 VGA@ R389 1 2 VGA@ 150_0402_1% 0 Disable
PEG_NRX_GTX_P1 C129 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P1 AE6 K3 VGA_CRT_B R388 1 2 VGA@ 150_0402_1%
PEG_NRX_GTX_N1 C128 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N1 PEX_TX1 MIOB_CLKOUT_N
1 2 AE7
PEG_NRX_GTX_P2 PEG_NRX_C_GTX_P2 PEX_TX1_N
C118 1 2 VGA@ 0.1U_0402_16V7K AD7
PEX_TX2 MIOB_VREF
J4 1 Enable(Default)
PEG_NRX_GTX_N2 C116 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N2 AC7
PEG_NRX_GTX_P3 C126 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P3 PEX_TX2_N
1 2 AE9
PEG_NRX_GTX_N3 C119 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N3 PEX_TX3 VGA_HSYNC
1 2 AE10 AD4 VGA_HSYNC 15
PEX_TX3_N DACA_HSYNC +3VS
PEG_NRX_GTX_P4 C113 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P4 AD10
PEX_TX4 DACA_VSYNC
AC4 VGA_VSYNC VGA_VSYNC 15 BAR2_SIZE NB8M
C PEG_NRX_GTX_N4 C110 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N4 AC10 AE1 VGA_CRT_R C
PEX_TX4_N DACA_RED VGA_CRT_R 15
PEG_NRX_GTX_P5 C111 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P5 AE12 AD2 VGA_CRT_B VGA_CRT_B 15 R143 VGA@
PEG_NRX_GTX_N5 PEG_NRX_C_GTX_N5 PEX_TX5 DACA_BLUE VGA_CRT_G VGA_CLK_LCD
C112 1 2 VGA@ 0.1U_0402_16V7K AE13
PEX_TX5_N DACA_GREEN
AD1 VGA_CRT_G 15 1 2 0 32Mb(Default)
PEG_NRX_GTX_P6 C105 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P6 AD13 U9
PEG_NRX_GTX_N6 C95 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N6 PEX_TX6 DACA_IDUMP DACA_RSET R394 1
1 2 AC13 AD3 2 124_0603_1% 2.2K_0402_5%
PEG_NRX_GTX_P7 PEG_NRX_C_GTX_P7 PEX_TX6_N DACA_RSET
C124 1 2 VGA@ 0.1U_0402_16V7K AC15
PEX_TX7
VGA@ 1 16Mb
PEG_NRX_GTX_N7 C125 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N7 AD15 AB4 DACAVREF 1 2 R142 VGA@
PEG_NRX_GTX_P8 C102 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P8 PEX_TX7_N DACA_VREF C480 0.01U_0402_16V7K VGA_DAT_LCD
1 2 AE15 1 2
PEG_NRX_GTX_N8 C103 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N8 PEX_TX8 VGA@
1 2 AE16
PEG_NRX_GTX_P9 C93 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P9 PEX_TX8_N 2.2K_0402_5%
1 2 AC18 E6
PEG_NRX_GTX_N9 C94 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N9 PEX_TX9 DACB_HSYNC
1 2 AD18 F5
PEX_TX9_N DACB_VSYNC

DACs
PEG_NRX_GTX_P10 C120 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P10 AE18 F4
PEG_NRX_GTX_N10 C122 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N10 PEX_TX10 DACB_RED +3VS
1 2 AE19 D5
PEG_NRX_GTX_P11 C123 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P11 PEX_TX10_N DACB_BLUE R140
1 2 AC21 E4
PEG_NRX_GTX_N11 C121 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N11 PEX_TX11 DACB_GREEN 2.2K_0402_5% VGA@
1 2 AD21 L9
PEG_NRX_GTX_P12 C107 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P12 PEX_TX11_N DACB_IDUMP I2CB_SCL
1 2 AE21 D6 1 2
PEG_NRX_GTX_N12 C108 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N12 PEX_TX12 DACB_RSET
1 2 AE22
PEG_NRX_GTX_P13 C114 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P13 PEX_TX12_N R436 2
1 2 AD22 E7 1 10K_0402_5% VGA@
PEG_NRX_GTX_N13 C115 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N13 PEX_TX13 DACB_VREF I2CB_SDA
1 2 AD23 1 2
PEG_NRX_GTX_P14 C106 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P14 PEX_TX13_N 2.2K_0402_5%
1 2 AF25
PEG_NRX_GTX_N14 PEG_NRX_C_GTX_N14 PEX_TX14 VGA_DDCCLK
C109 1 2 VGA@ 0.1U_0402_16V7K AE25
PEX_TX14_N I2CA_SCL
D10 VGA_DDCCLK 15 <---CRT R141 VGA@
PEG_NRX_GTX_P15 C90 1 2 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_P15 AE24 E10 VGA_DDCDATA VGA_DDCDATA 15
PEG_NRX_GTX_N15 C91 VGA@ 0.1U_0402_16V7K PEG_NRX_C_GTX_N15 PEX_TX15 I2CA_SDA I2CB_SCL
1 2 AD24 F9
PEX_TX15_N I2CB_SCL I2CB_SDA
F10
CLK_PCIE_VGA I2CB_SDA VGA_CLK_LCD
AE3 E9
I2C

16 CLK_PCIE_VGA PEX_REFCLK I2CC_SCL VGA_CLK_LCD 15

16 CLK_PCIE_VGA# CLK_PCIE_VGA# AE4 D8 VGA_DAT_LCD VGA_DAT_LCD 15 <---LVDS
PEX_REFCLK_N I2CC_SDA
C7
PLT_RST# I2CH_SCL
7,17,19,22,26,27,28 PLT_RST# AC6 B7
PEX_RST_N I2CH_SDA
HDCP

N6 IFPAB_VPROBE 2 1 C521
B IFPAB_VPROBE 0.01U_0402_16V7K @ B
M5
IFPCD_VPROBE IFPCD_VPROBE 2 1 C523
XTALIN B1 0.01U_0402_16V7K @
XTALIN
AE27 PAD TP52
JTAG_TCK
AD27 PAD TP54
JTAG_TDI
CLK

AE26 PAD TP55

JTAG_TDO
TEST

XTALOUT C2 AD26 PAD TP56

XTALOUT JTAG_TMS
AD25 PAD TP57
JTAG_TRST_N 10K_0402_5% VGA@ R419
C3 D7 2 1
XTALOUTBUFF TESTMODE
R392
Y5 AF13
PEX_TSTCLK_OUT
4 3 C1 AF14 1 2
GND OUT XTALSSIN PEX_TSTCLK_OUT_N
1 2 @ 200_0402_5%
IN GND
27MHZ_16PF_X7S027000BG1H-U G72M_BGA533 VGA@
1 VGA@ 1
C556 C555 R415 OSC_SPREAD
1 VGA@2 OSC_OUT +3VS
12P_0402_50V8J 18P_0402_50V8J 22_0402_5% External Spread Spectrum
1

2 2 VGA@ C243 1 2 0.1U_0402_16V4Z

VGA@ R414 R413 VGA@
U40
10K_0402_5% 10K_0402_5% 7 5
@ VDD REF VGA@
2

@ OSC_OUT 1 4 1 2 OSC_SPREAD
XIN MODOUT R412 22_0402_5%
8 3
XOUT NC
If External Spread Spectrum not stuff than stuff resistor 2 6
VSS PD#
ASM3P1819N-SR_SO8
A VGA@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB8M-GS Main
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 33 of 51

5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

FBAD[0..63]
FBAD[0..63] 37,38

FBAA[0..12]
FBAA[0..12] 37,38
D D
FBBA[2..5]
FBBA[2..5] 38 +3VS

FBADQS[0..7] R427 VGA@

FBADQS[0..7] 37,38
EC_SMB_CK2 0_0402_5% 2 1 R149 I2CS_SCL 1 2 2.2K_0402_5%
4,28,29 EC_SMB_CK2
VGA@ R425 VGA@
FBADQS#[0..7] EC_SMB_DA2 0_0402_5% 2 1 R424 I2CS_SDA 1 2 2.2K_0402_5%
FBADQS#[0..7] 37,38 4,28,29 EC_SMB_DA2
VGA@

FBADQM#[0..7]
FBADQM#[0..7] 37,38

U38B
FBAD0 A26 G27 FBAA3 U38C
FBAD1 FBAD0 Part 2 of 5 FBA_CMD0 FBAA0 VGA_LVDSAC+ PEX_PLL_TERM
C24 D25 15 VGA_LVDSAC+ T4 A2 PEX_PLL_TERM 36
FBAD2 FBAD1 FBA_CMD1 FBAA2 VGA_LVDSAC- IFPA_TXC Part 3 of 5 MIO_A_D0 SUB_VENDOR
B24 F26 15 VGA_LVDSAC- U4 B3 SUB_VENDOR 36
FBAD3 FBAD2 FBA_CMD2 FBAA1 VGA_LVDSA0+ IFPA_TXC_N MIO_A_D1
A24 F25 15 VGA_LVDSA0+ N4 A3
FBAD4 FBAD3 FBA_CMD3 FBBA3 VGA_LVDSA0- IFPA_TXD0 MIO_A_D2
C22 G25 15 VGA_LVDSA0- N5 D4
FBAD5 FBAD4 FBA_CMD4 FBBA4 VGA_LVDSA1+ IFPA_TXD0_N MIO_A_D3
A25 J25 15 VGA_LVDSA1+ R5 A4
FBAD6 FBAD5 FBA_CMD5 FBBA5 VGA_LVDSA1- IFPA_TXD1 MIO_A_D4
B25 J27 15 VGA_LVDSA1- R4 B4
FBAD7 FBAD6 FBA_CMD6 FBACS1# VGA_LVDSA2+ IFPA_TXD1_N MIO_A_D5 PEX_CFG0
D23 M26 PAD TP51 15 VGA_LVDSA2+ T5 B6 PEX_CFG0 36
FBAD8 FBAD7 FBA_CMD7 FBACS0# VGA_LVDSA2- IFPA_TXD2 MIO_A_D6
G22 C27 FBACS0# 37,38 15 VGA_LVDSA2- T6 P4
FBAD9 FBAD8 FBA_CMD8 FBAWE# IFPA_TXD2_N MIO_A_D7 PEX_CFG1
J23 C25 FBAWE# 37,38 R6 C6 PEX_CFG1 36
FBAD10 FBAD9 FBA_CMD9 FBA_BA0 IFPA_TXD3 MIO_A_D8 PEX_CFG2
E24 D24 FBA_BA0 37,38 FBA_CKE 37,38 P6 G5 PEX_CFG2 36
FBAD11 FBAD10 FBA_CMD10 FBA_CKE VGA_LVDSBC+ IFPA_TXD3_N MIO_A_D9
F23 N27 15 VGA_LVDSBC+ W5 V4
FBAD12 FBAD11 FBA_CMD11 AODT0 R110 1 IFPB_TXC MIO_A_D10
J24 G24 2 FBAODT0 VGA_LVDSBC- W6 C4 SLOT_CLOCK_CFG 1 @2 R473 2K_0402_5%

NC
FBAD12 FBA_CMD12 FBAODT0 37,38 15 VGA_LVDSBC- IFPB_TXC_N MIO_A_HSYNC

1
FBAD13 F24 J26 FBBA2 VGA@ 0_0402_5% 15 VGA_LVDSB0+ VGA_LVDSB0+ W3 F11 I2CS_SDA
FBAD13 FBA_CMD13 IFPB_TXD4 I2CS_SDA

1
FBAD14 G23 M27 FBAA12 R94 15 VGA_LVDSB0- VGA_LVDSB0- W2 F12 I2CS_SCL
FBAD15 FBAD14 FBA_CMD14 FBARAS# R99 10K_0402_5% VGA_LVDSB1+ IFPB_TXD4_N I2CS_SCL
H24 C26 FBARAS# 37,38 15 VGA_LVDSB1+ AA2 D12
FBAD16 FBAD15 FBA_CMD15 FBAA11 10K_0402_5% VGA@ VGA_LVDSB1- IFPB_TXD5 NC_2
D16 M25 15 VGA_LVDSB1- AA3 E12
C FBAD17 FBAD16 FBA_CMD16 FBAA10 VGA_LVDSB2+ IFPB_TXD5_N GPIO14 +3VS C

LVDS/TMDS
E16 D26 VGA@ 15 VGA_LVDSB2+ AB1 C13

2
FBAD18 FBAD17 FBA_CMD17 FBA_BA1 VGA_LVDSB2- IFPB_TXD6 GPIO13
D17 D27 FBA_BA1 37,38 15 VGA_LVDSB2- AA1

2
FBAD19 FBAD18 FBA_CMD18 FBAA8 IFPB_TXD6_N
F18 K26 AB3 F6 1
FBAD20 FBAD19 FBA_CMD19 FBAA9 IFPB_TXD7 MIO_A_VDDQ_0 C239
E19 K25 AB2 G6
FBAD21 FBAD20 FBA_CMD20 FBAA6 IFPB_TXD7_N MIO_A_VDDQ_1 VGA@
E18 K24 J6
FBAD22 FBAD21 FBA_CMD21 FBAA5 R390 1 MIO_A_VDDQ_2
D20 F27 2 @ 1K_0402_5% U6 0.1U_0402_16V4Z
FBAD23 FBAD22 FBA_CMD22 FBAA7 IFPAB_RSET 2
D19 K27 A6
FBAD24 FBAD23 FBA_CMD23 FBAA4 BUFRST_N
A18 G26 V1
FBAD25 FBAD24 FBA_CMD24 FBACAS# IFPC_TXC +3VS
B18 B27 FBACAS# 37,38 W1
FBAD25 FBA_CMD25 IFPC_TXC_N

GENERAL
FBAD26 A19 N24 T1 F7
FBAD27 FBAD26 FBA_CMD26 IFPC_TXD0 STEREO
B19 R1
FBAD28 FBAD27 FBADQM#0 IFPC_TXD0_N
D18 D21 T3 A7 1 R139 2
FBAD29 FBAD28 FBADQM0 FBADQM#1 IFPC_TXD1 SWAPRDY VGA@ 10K_0402_5%
C19 F22 T2 C9
FBAD30 FBAD29 FBADQM1 FBADQM#2 IFPC_TXD1_N THERMDN
C16 F20 V2 B9
FBAD31 FBAD30 FBADQM2 FBADQM#3 IFPC_TXD2 THERMDP
C18 A21 V3
FBAD32 FBAD31 FBADQM3 FBADQM#4 IFPC_TXD2_N
N26 V27
FBAD33 FBAD32 FBADQM4 FBADQM#5
N25 W22
FBAD34 FBAD33 FBADQM5 FBADQM#6 R409 1
R25 V22 2 @ 1K_0402_5% J3
FBAD35 FBAD34 FBADQM6 FBADQM#7 IFPCD_RSET
R26 V24 D2
FBAD36 FBAD35 FBADQM7 ROM_SCLK
R27 F3
FBAD37 FBAD36 FBADQS#0 ROM_SI
T25 A22
FBAD38 T27
FBAD37 FBADQS_RN0
E22 FBADQS#1 SERIAL ROM_SO
D3
D1
FBAD39 FBAD38 FBADQS_RN1 FBADQS#2 ROMCS_N
T26 F21
FBAD40 FBAD39 FBADQS_RN2 FBADQS#3
AB23 B21
FBAD41 FBAD40 FBADQS_RN3 FBADQS#4
Y24 V26
FBAD42 FBAD41 FBADQS_RN4 FBADQS#5 G72M_BGA533 VGA@
AB24 W23
FBAD43 FBAD42 FBADQS_RN5 FBADQS#6
AB22 V23
FBAD43 FBADQS_RN6
FBAD44 AC24
FBAD44 FBADQS_RN7
W27 FBADQS#7 SLOT_CLOCK_CFG SHARE REFERENCE CLOCK
FBAD45 AC22
FBAD46 FBAD45 FBADQS0 +1.8VS
AA23 B22
FBAD47 FBAD46 FBADQS_WP0 FBADQS1
AA22
FBAD47 FBADQS_WP1
D22 0 Disable
FBAD48 T24 E21 FBADQS2
B FBAD49 FBAD48 FBADQS_WP2 FBADQS3 B
T23 C21
FBAD49 FBADQS_WP3
1

FBAD50 R24 V25 FBADQS4 1 Enable(Default)

FBAD51 FBAD50 FBADQS_WP4 FBADQS5 R423
R23 W24
FBAD52 FBAD51 FBADQS_WP5 FBADQS6 1K_0402_1%
R22 U24
FBAD53 FBAD52 FBADQS_WP6 FBADQS7
T22 W26 @
FBAD54 FBAD53 FBADQS_WP7
N23
2

FBAD55 FBAD54 FB_VREF1 15mil

P24 A16
FBAD56 FBAD55 FB_VREF
AA24
FBAD56
1

FBAD57 AA27 L24 1

FBAD57 FBA_CLK0 FBACLK0 37
FBAD58 AA26 K23 C552 R422
MEMORY INTERFACE

FBAD58 FBA_CLK0_N FBACLK0# 37

FBAD59 AB25 M22 @ 1K_0402_1%
FBAD59 FBA_CLK1 FBACLK1 38
FBAD60 AB26 N22 0.1U_0402_16V4Z @
FBAD60 FBA_CLK1_N FBACLK1# 38 2
FBAD61 AB27 M23
2

FBAD62 FBAD61 FBA_CMD27 R111

AA25 M24
FBAD63 FBAD62 NC FBA_DEBUG 1
W25 K22 2 FBAODT0
FBAD63 FBA_DEBUG 0_0402_5%
@
G72M_BGA533 VGA@
FB_VREF1=0.5 x FBVDD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB8M-GS Memory
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 34 of 51
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE +1.2VS

+VGA_CORE U38D 1400mA

J9 W17 0.1U_0402_16V4Z 1U_0402_6.3V4K
VDD_0 Part 4 of 5 PEX_IOVDD_0
J10 W18
1U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDD_1 PEX_IOVDD_1
J11 AB10 1 1 1 1 1
VDD_2 PEX_IOVDD_2 C166 C168 C187 C169 C224
L12 AB11
VDD_3 PEX_IOVDD_3 VGA@
1 1 1 1 1 1 L13 AB14
D C207 C180 C191 C183 C193 C182 VDD_4 PEX_IOVDD_4 VGA@ VGA@ VGA@ VGA@ 4.7U_ 0603_6.3V D
L15 AB15
VDD_5 PEX_IOVDD_5 2 2 2 2 2
L16 AB20
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VDD_6 PEX_IOVDD_6
M9 AB21
2 2 2 2 2 2 VDD_7 PEX_IOVDD_7
M11 AA4
VDD_8 PEX_IOVDDQ_0 0.1U_0402_16V4Z 1U_0402_6.3V4K
M12 AB5
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDD_9 PEX_IOVDDQ_1
M13 AB6
VDD_10 PEX_IOVDDQ_2
M14 AB7
VDD_11 PEX_IOVDDQ_3 0.1U_0402_16V4Z 1U_0402_6.3V4K
M15 AB8
VDD_12 PEX_IOVDDQ_4
M16 AB9 1 1 1 1 1
VDD_13 PEX_IOVDDQ_5 C161 C176 C162 C165 C267
M17 AB12
+NV_PLLVDD VDD_14 PEX_IOVDDQ_6 VGA@
N9 AB13
0.47U_0402_10V4Z 0.47U_0402_10V4Z 0.1U_0402_16V4Z VDD_15 PEX_IOVDDQ_7 VGA@ VGA@ VGA@ VGA@ 4.7U_ 0603_6.3V
N11 AB16
VDD_16 PEX_IOVDDQ_8 2 2 2 2 2
N17 AB17
VDD_17 PEX_IOVDDQ_9
1 1 1 1 1 1 R9 AB18
C233 C227 C228 C234 C195 C194 VDD_18 PEX_IOVDDQ_10
R11 AB19
VDD_19 PEX_IOVDDQ_11 0.1U_0402_16V4Z 1U_0402_6.3V4K
R17 AC9
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VDD_20 PEX_IOVDDQ_12
T9 AC11
2 2 2 2 2 2 VDD_21 PEX_IOVDDQ_13
T11 AC12
VDD_22 PEX_IOVDDQ_14
T12 AC16
0.47U_0402_10V4Z 0.47U_0402_10V4Z 0.1U_0402_16V4Z VDD_23 PEX_IOVDDQ_15
T13 AC17
VDD_24 PEX_IOVDDQ_16
T14 AC19
VDD_25 PEX_IOVDDQ_17

POWER
T15 AC20 +1.2VS
VDD_26 PEX_IOVDDQ_18
T16
VDD_27 +PEX_PLLAVDD L6 VGA@
T17 Y6
+VGA_CORE VDD_28 PEX_PLLAVDD +PEX_PLLDVDD +PEX_PLLAVDD +PEX_PLLAVDD_L 1
U12 AA5 2
VDD_29 PEX_PLLDVDD MBK1608121YZF_0603
U13 1 1 1
0.47U_0402_6.3V4Z 0.47U_0402_10V4Z VDD_30 0.1U_0402_16V4Z +3VS C173 C184 C266
U15 K5
VDD_31 MIOB_VDDQ_0 VGA@
1 1 1 1 1 U16 K6 1
C205 C203 C215 C235 C438 VDD_32 MIOB_VDDQ_1 C244 VGA@ VGA@ 4.7U_ 0603_6.3V
W13 L6
VDD_33 MIOB_VDDQ_2 2 2 2
W15
VGA@ VGA@ VGA@ VGA@ VGA@ VDD_34 VGA@ 0.01U_0402_16V7K
W16 J5
1U_0805_10V4Z 2 2 2 2 2 VDD_35 MIOBCAL_PD_VDDQ 2 0.1U_0402_16V4Z
C 0.47U_0402_10V4Z 1U_0805_10V4Z W4 +IFPA_IOVDD C
IFPA_IOVDD +PEX_PLLDVDD
W9 Y4
VDD_LP_0 IFPB_IOVDD
W10 L4 1 R114 2 VGA@ 1 1
Average to place around +VGA_CORE VDD_LP_1 IFPC_IOVDD 10K_0402_5% C485 C492
W11
plane. VDD_LP_2 +IFPAB_PLLVDD
W12 V5
+3VS VDD_LP_3 IFPAB_PLLVDD
M4 1 R107 2 VGA@ VGA@
IFPCD_PLLVDD 10K_0402_5% VGA@ 2 2
+3VS F13 AE2 +DACA_VDD 0.01U_0402_16V7K
VDD33_0 DACA_VDD 0.1U_0402_16V4Z
F14 F8 2 1
VDD33_1 DACB_VDD
0.47U_0402_10V4Z

J12 R118 10K_0402_5%

0.022U_0402_16V7K VDD33_2
J13 VGA@
VDD33_3 40mA +PLLVDD
1 1 1 1 J15 H4
VDD33_4 PLLVDD +1.8VS
C242

C229 C240 C241 J16

VDD33_5 +FBA_PLLAVDD
D13 40mA L26
VGA@ VGA@ VGA@ +1.8VS FBA_PLLAVDD +1.8VS VGA@
R44= 40.2_0402_1% (For
1U_0603_10V4Z 2 2 2 2
D14 +H_PLLVDD +IFPA_IOVDD 4700P_0402_25V7K 1 2
0.1U_0402_16V4Z H_PLLVDD DDR1/2) P/N:SD034402A80 MBK1608121YZF_0603
E15
VGA@ FBVTT_0
F15 D15 2 1 R416 1 1 1 VGA@
FBVTT_1 FBCAL_PD_VDDQ VGA@ 40.2_0402_1% +1.8VS C495 C497 C493
F16
FBVTT_2
J17
FBVTT_3
J18 F17 4700P_0402_25V7K 1U_0402_6.3V4Z 1U_0402_6.3V4Z VGA@ VGA@
FBVTT_4 FBVDDQ_0 2 2 2 4.7U_ 0603_6.3V
L19 F19 1 1 1 1 1 1
FBVTT_5 FBVDDQ_1 C189 C256 C251 C210 C206 C545
N19 J19
FBVTT_6 FBVDDQ_2 470P_0402_50V7K
R19 J22
+VGA_CORE FBVTT_7 FBVDDQ_3 VGA@ VGA@ VGA@ VGA@ VGA@
U19 L22
FBVTT_8 FBVDDQ_4 2 2 2 2 2 2 VGA@
R95 W19 M19
FBVTT_9 FBVDDQ_5
P22
+NV_PLLVDD FBVDDQ_6 4700P_0402_25V7K 4700P_0402_25V7K 22U_0805_6.3V4Z +1.8VS
1 2 T19
FBVDDQ_7
D11 U22
0_0603_5% NC FBVDDQ_8 L27
8mA FBVDDQ_9
Y22
VGA@ +IFPAB_PLLVDD 4700P_0402_25V7K 1 2
1 VGA@ 1 1 MBK1608121YZF_0603
B G72M_BGA533 C518 C506 C511 VGA@ B

VGA@ VGA@ VGA@

2 2 2
4.7U_ 0603_6.3V

2.2U_0402_6.3V6K

L29
MBK1608121YZF_0603 +1.2VS
VGA@
+PLLVDD 4700P_0402_25V7K 2 1
30mA
1 1 1
C530 C531 C541
L32 VGA@ VGA@ L25
MBK1608121YZF_0603 +1.2VS 0.1U_0402_16V4Z~N MBK1608121YZF_0603 +3VS
VGA@ 2 2 2 VGA@
VGA@
+H_PLLVDD 2 1 +DACA_VDD 4700P_0402_25V7K 2 1

1 1 2 1 1 1
C257 C559 2.2U_0402_6.3V6K C481 C483 C491 C479
VGA@ VGA@ VGA@ VGA@ VGA@
0.1U_0402_16V4Z~N 4.7U_ 0603_6.3V L31 2.2U_0402_6.3V6K
2 2 MBK1608121YZF_0603 +1.2VS 1 2 2 2
VGA@
VGA@
+FBA_PLLAVDD 2 1 0.1U_0402_16V7K 470P_0402_50V7K

1 1
C557 C551 C554
A A
VGA@ VGA@ VGA@
2 2
1U_0402_6.3V4K 4.7U_ 0603_6.3V
0.01U_0402_16V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB8M-GS Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 35 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

STRAPS PIN DESCRIPTION Value Value

U38E
B2 U17
GND_0 Part 5 of 5 GND_60
B5 U23
GND_1 GND_61
B8 U26
GND_2 GND_62
B11 V9
GND_3 GND_63
B14
GND_4 GND_64
V19 VBIOS on card (pull high)
B17
GND_5 GND_65
W14 SUB_VENDOR MIOAD1 VBIOS with system BIOS (pull down) 0
D B20 Y2 D
GND_6 GND_66
B23 Y5
GND_7 GND_67
B26
GND_8 GND_68
Y23 PEX_PLL_TERM MIOAD0 0
E2 Y26
GND_9 GND_69
E5
GND_10 GND_70
AC2 MIOAD
E8
GND_11 GND_71
AC8 PEX_CFG[2:0] [9,8,6] Recommended for G7x 001
E11 AC14
GND_12 GND_72
E14 AC23
GND_13 GND_73
E17
GND_14 GND_74
AC26 RAM_CFG[3:0] MIOAD[5:2] RAM_CFG[3] (Bandwidth 0=Full, 1=Half)
E20 AD8 34 SUB_VENDOR SUB_VENDOR R428 1 2 2K_0402_5%
GND_15 GND_75
E23 AD9
GND_16 GND_76
E26
GND_17 GND_77
AD11 VGA@ RAM_CFG[2] (0=16M or 1=32M)
AD12
GND_78
H2 AD14
GND_19 GND_79
H6
GND_20 GND_80
AD16 RAM_CFG[1:0]
H23 AD17 (Manufacture)
GND_21 GND_81
H26
GND_22 GND_82
AD19 SUB_VENDOR
J14 AD20 (01=Sam, 10=Inf, 11=Hyn)
GND_23 GND_83
K9 AC5
GND_24 GND_84

GND
K19
GND_25 GND_85
AF2 0 N0 VIDEO BIOS ROM
L2 AF3
GND_26 GND_86
L5 AF6
GND_27 GND_87
L11
GND_28 GND_88
AF9 1 BIOS ROM is present(Default)
L14 AF12
GND_29 GND_89
L17 AF15
GND_30 GND_90
L23
GND_31 GND_91
AF18 G73M-xxxx8
L26 AF21 PCI_DEVID[3:0] VIPD[5:3] G72M-0x01D8 0111
GND_32 GND_92
N12
GND_33 GND_93
AF24 MIOA_HSYNC NB8M-GS : 0X0427
N13
GND_34 GND_94
AF26 NB8M-SE : 0X0428 1000
N14
GND_35
N15
GND_36
G72MV-0x01D7 0111
N16 TBD/TBD
C GND_37 C
P2
GND_38
P5 V6
GND_39 IFPAB_PLLGND
P9 M6
GND_40 IFPCD_PLLGND
P11
GND_41
P12
GND_42
P13 M3 PAD TP53
GND_43 MIOBCAL_PU_GND
P14
GND_44
P15 AA6
GND_45 PEX_PLLGND
P16
GND_46
P17 H5
GND_47 PLLGND
P19
GND_48
P23
GND_49
P26 C15
GND_50 FBA_PLLGND
R12
GND_51
R13
GND_52
R14
GND_53 R418 1
R15 E13 2 40.2_0402_1%
GND_54 FBCAL_PU_GND
R16 H22
GND_55 FBCAL_TERM_GND +3VS
U2 VGA@
GND_56
U5
GND_57 10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
U11
GND_58 10K_0402_5% 10K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
U14
GND_59

1
G72M_BGA533
VGA@ R466 R467 R474 R453 R406 R407 R408 R398 R410 R426 R420 R438 R472 R421
VGA@ @ VGA@ @ @ @ @ @
VGA@ VGA@ VGA@ @ @ VGA@

2
RAM_CFG0
33 RAM_CFG0
RAM_CFG1
33 RAM_CFG1
RAM_CFG2
33 RAM_CFG2
B RAM_CFG3 B
33 RAM_CFG3
PCI_DEVID0
33 PCI_DEVID0
PCI_DEVID1
33 PCI_DEVID1
PCI_DEVID2
33 PCI_DEVID2
PCI_DEVID3
33 PCI_DEVID3
PCI_DEVID4
33 PCI_DEVID4
PEX_CFG0
34 PEX_CFG0
PEX_CFG1
34 PEX_CFG1
PEX_CFG2
34 PEX_CFG2
PEX_CFG3
33 PEX_CFG3
PEX_PLL_TERM
34 PEX_PLL_TERM

1
R465 R468 R475 R411
@ @ @ VGA@

2
10K_0402_5% 10K_0402_5%
10K_0402_5% 10K_0402_5%

Bandwidth RAM Type Vendor Package

A FULL R17 32M R11 Samsung R20, R19 A
(10*12.5) Infineon GDDR2(400): SA00000S800 (HYB18T256161AFL-25) Infineon GDDR2(350): SA00000T700 (HYB18T256161AF-28)
HALF R12 16M R16 Hynix R18, R19 (11*13) Samsung GDDR2 (400): SA00000FG10 (K4N56163QF-ZC25) Samsung GDDR2 (350): SA00000TB00 (K4N56163QF-ZC2A)
Infineon R18, R21 (8*13) Hynix GDDR2 (400): SA00000FF10 (HY5PS561621AFP-25) Hynix GDDR2 (350): SA00000TJ00 (HY5PS561621AFP-28)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NB8M-GS GND & STRAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 36 of 51
5 4 3 2 1
 5 4 3 2 1

U45A1 U45B1
FBA_BA0 L2 B9 FBAD14 FBA_BA0 L2 B9 FBAD25
FBA_BA1 BA0 DQ15 FBAD11 FBA_BA1 BA0 DQ15 FBAD31
L3 B1 L3 B1
BA1 DQ14 FBAD13 BA1 DQ14 FBAD27
D9 D9
FBAA12 DQ13 FBAD8 FBAA12 DQ13 FBAD30
R2 D1 R2 D1
FBAA11 A12 DQ12 FBAD9 FBAA11 A12 DQ12 FBAD26
P7 D3 P7 D3
FBAA10 A11 DQ11 FBAD12 FBAA10 A11 DQ11 FBAD28
M2 D7 M2 D7
FBAA9 A10/AP DQ10 FBAD10 FBAA9 A10/AP DQ10 FBAD29
P3 C2 P3 C2
FBAA8 A9 DQ9 FBAD15 FBAA8 A9 DQ9 FBAD24
P8 C8 P8 C8
FBAA7 A8 DQ8 FBAD3 FBAA7 A8 DQ8 FBAD18
P2 F9 P2 F9
FBAA6 A7 DQ7 FBAD1 FBAA6 A7 DQ7 FBAD23
N7 F1 N7 F1
FBAA5 A6 DQ6 FBAD5 FBAA5 A6 DQ6 FBAD17
N3 H9 N3 H9
FBAA4 A5 DQ5 FBAD7 FBAA4 A5 DQ5 FBAD21
N8 H1 N8 H1
D FBAA3 A4 DQ4 FBAD6 FBAA3 A4 DQ4 FBAD19 D
N2 H3 N2 H3
FBAA2 A3 DQ3 FBAD0 FBAA2 A3 DQ3 FBAD16
M7 H7 M7 H7
FBAA1 A2 DQ2 FBAD4 FBAA1 A2 DQ2 FBAD22 FBBA[2..5]
M3 G2 M3 G2 34,38 FBBA[2..5]
FBAA0 A1 DQ1 FBAD2 FBAA0 A1 DQ1 FBAD20
M8 G8 M8 G8
A0 DQ0 A0 DQ0
FBAD[0..63]
34,38 FBAD[0..63]
FBACLK0# K8 A9 FBACLK0# K8 A9
FBACLK0 CK VDDQ1 FBACLK0 CK VDDQ1
J8 C1 J8 C1
CK VDDQ2 CK VDDQ2 FBAA[0..12]
C3 C3 34,38 FBAA[0..12]
FBA_CKE VDDQ3 FBA_CKE VDDQ3
K2 C7 K2 C7
CKE VDDQ4 CKE VDDQ4
C9 C9
VDDQ5 VDDQ5 FBADQS[0..7]
E9 E9 34,38 FBADQS[0..7]
VDDQ6 +1.8VS VDDQ6 +1.8VS
G1 G1
FBACS0# VDDQ7 FBACS0# VDDQ7
L8 G3 L8 G3
CS VDDQ8 CS VDDQ8 FBADQS#[0..7]
G7 G7 34,38 FBADQS#[0..7]
FBAWE# VDDQ9 FBAWE# VDDQ9
K3 G9 K3 G9
WE VDDQ10 WE VDDQ10
FBARAS# K7 A1 FBARAS# K7 A1 FBADQM#[0..7]
RAS VDD1 RAS VDD1 34,38 FBADQM#[0..7]
E1 E1
FBACAS# VDD2 FBACAS# VDD2
L7 J9 L7 J9
CAS VDD3 CAS VDD3 FBA_BA0
M9 M9 34,38 FBA_BA0
FBADQM#0 VDD4 FBADQM#2 VDD4
F3 R1 F3 R1
FBADQM#1 LDM VDD5 FBADQM#3 LDM VDD5 FBA_BA1
B3 B3 34,38 FBA_BA1
UDM UDM
J1 J1
VDDL VDDL FBAODT0
J7 1 1 J7 1 1 34,38 FBAODT0
FBAODT0 VSSDL C258 C221 FBAODT0 VSSDL C265 C204
K9 K9
ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z FBA_CKE
34,38 FBA_CKE
VGA@ VGA@ VGA@ VGA@
+1.8VS FBADQS0 F7 2 2 FBADQS2 F7 2 2 FBARAS#
LDQS LDQS 34,38 FBARAS#
FBADQS#0 E8 A7 FBADQS#2 E8 A7
LDQS VSSQ1 LDQS VSSQ1 FBACAS#
B2 B2 34,38 FBACAS#
VSSQ2 VSSQ2
B8 B8
VSSQ3 VSSQ3
1

C D2 D2 FBAWE# C
VSSQ4 VSSQ4 34,38 FBAWE#
R100 FBADQS1 B7 D8 FBADQS3 B7 D8
+VRAM_VREFA 1.5K_0402_1% FBADQS#1 UDQS VSSQ5 +VRAM_VREFA FBADQS#3 UDQS VSSQ5 FBACS0#
A8 E7 A8 E7 34,38 FBACS0#
VGA@ UDQS VSSQ6 UDQS VSSQ6
F2 F2
VSSQ7 VSSQ7
F8 F8
2

VSSQ8 VSSQ8
J2 H2 J2 H2
(SSTL-1.8) VREF = .5*VDDQ VREF VSSQ9 (SSTL-1.8) VREF = .5*VDDQ VREF VSSQ9
H8 H8
VSSQ10 VSSQ10
1

1 A2 1 A2
R101 C220 NC#A2 C219 NC#A2
E2 A3 E2 A3
1K_0402_1% NC#E2 VSS1 NC#E2 VSS1
L1 E3 L1 E3
VGA@ 0.1U_0402_10V6K NC#L1 VSS2 0.1U_0402_10V6K NC#L1 VSS2
R3 J3 R3 J3
2 NC#R3 VSS3 2 NC#R3 VSS3
VGA@ R7 N1 VGA@ R7 N1 Close to U5
2

NC#R7 VSS4 NC#R7 VSS4

Close to U45A1 R8
NC#R8 VSS5
P9 Close to U45B1 R8
NC#R8 VSS5
P9 34 FBACLK0
FBACLK0

@ K4N51163QE-ZC25 @ K4N51163QE-ZC25

1
R104
R60
243_0402_1% AT END
VGA@
DDR2 BGA MEMORY DDR2 BGA MEMORY

2
+1.8VS +1.8VS FBACLK0#
34 FBACLK0#
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C539 C543 C262 C250 C264 C534 C509 C198 C550 C549 C260 C268 C547 C535 C553 C238
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 0.01U_0402_16V7K VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 0.01U_0402_16V7K
VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
B 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 37 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

U45C1 U45D1
FBA_BA0 L2 B9 FBAD46 FBA_BA0 L2 B9 FBAD32
FBA_BA1 BA0 DQ15 FBAD45 FBA_BA1 BA0 DQ15 FBAD36
L3 B1 L3 B1
BA1 DQ14 FBAD42 BA1 DQ14 FBAD33
D9 D9
FBAA12 DQ13 FBAD41 FBAA12 DQ13 FBAD38
R2 D1 R2 D1
FBAA11 A12 DQ12 FBAD47 FBAA11 A12 DQ12 FBAD39
P7 D3 P7 D3
FBAA10 A11 DQ11 FBAD40 FBAA10 A11 DQ11 FBAD35
M2 D7 M2 D7
FBAA9 A10/AP DQ10 FBAD43 FBAA9 A10/AP DQ10 FBAD37
P3 C2 P3 C2
FBAA8 A9 DQ9 FBAD44 FBAA8 A9 DQ9 FBAD34
P8 C8 P8 C8
FBAA7 A8 DQ8 FBAD61 FBAA7 A8 DQ8 FBAD49
P2 F9 P2 F9
FBAA6 A7 DQ7 FBAD58 FBAA6 A7 DQ7 FBAD55
N7 F1 N7 F1
FBBA5 A6 DQ6 FBAD63 FBBA5 A6 DQ6 FBAD53 FBAD[0..63]
N3 H9 N3 H9 34,37 FBAD[0..63]
FBBA4 A5 DQ5 FBAD56 FBBA4 A5 DQ5 FBAD54
N8 H1 N8 H1
FBBA3 A4 DQ4 FBAD59 FBBA3 A4 DQ4 FBAD52
N2 H3 N2 H3
FBBA2 A3 DQ3 FBAD57 FBBA2 A3 DQ3 FBAD50 FBAA[0..12]
M7 H7 M7 H7 34,37 FBAA[0..12]
D FBAA1 A2 DQ2 FBAD60 FBAA1 A2 DQ2 FBAD51 D
M3 G2 M3 G2
FBAA0 A1 DQ1 FBAD62 FBAA0 A1 DQ1 FBAD48
M8 G8 M8 G8
A0 DQ0 A0 DQ0 FBBA[2..5]
34 FBBA[2..5]
FBACLK1# K8 A9 FBACLK1# K8 A9
FBACLK1 CK VDDQ1 FBACLK1 CK VDDQ1 FBADQS[0..7]
J8 C1 J8 C1 34,37 FBADQS[0..7]
CK VDDQ2 CK VDDQ2
C3 C3
FBA_CKE VDDQ3 FBA_CKE VDDQ3
K2 C7 K2 C7
CKE VDDQ4 CKE VDDQ4 FBADQS#[0..7]
C9 C9 34,37 FBADQS#[0..7]
VDDQ5 VDDQ5
E9 E9
VDDQ6 +1.8VS VDDQ6 +1.8VS
G1 G1
FBACS0# VDDQ7 FBACS0# VDDQ7 FBADQM#[0..7]
L8 G3 L8 G3 34,37 FBADQM#[0..7]
CS VDDQ8 CS VDDQ8
G7 G7
FBAWE# VDDQ9 FBAWE# VDDQ9
K3 G9 K3 G9
WE VDDQ10 WE VDDQ10 FBA_BA0
34,37 FBA_BA0
FBARAS# K7 A1 FBARAS# K7 A1
RAS VDD1 RAS VDD1 FBA_BA1
E1 E1 34,37 FBA_BA1
FBACAS# VDD2 FBACAS# VDD2
L7 J9 L7 J9
CAS VDD3 CAS VDD3 FBAODT0
M9 M9 34,37 FBAODT0
FBADQM#7 VDD4 FBADQM#6 VDD4
F3 R1 F3 R1
FBADQM#5 LDM VDD5 FBADQM#4 LDM VDD5 FBA_CKE
B3 B3 34,37 FBA_CKE
UDM UDM
J1 J1
VDDL VDDL FBARAS#
J7 1 1 J7 1 1 34,37 FBARAS#
FBAODT0 VSSDL C130 C131 FBAODT0 VSSDL C139 C147
K9 K9
ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z ODT 0.1U_0402_16V4Z 1U_0402_6.3V4Z FBACAS#
34,37 FBACAS#
VGA@ VGA@ VGA@ VGA@
FBADQS7 2 2 FBADQS6 2 2 FBAWE#
F7 F7 34,37 FBAWE#
+1.8VS FBADQS#7 LDQS FBADQS#6 LDQS
E8 A7 E8 A7
LDQS VSSQ1 LDQS VSSQ1 FBACS0#
B2 B2 34,37 FBACS0#
VSSQ2 VSSQ2
B8 B8
VSSQ3 VSSQ3
1

D2 D2
R103 FBADQS5 VSSQ4 FBADQS4 VSSQ4
B7 D8 B7 D8
C +VRAM_VREFB 1.5K_0402_1% FBADQS#5 UDQS VSSQ5 +VRAM_VREFB FBADQS#4 UDQS VSSQ5 C
A8 E7 A8 E7
VGA@ UDQS VSSQ6 UDQS VSSQ6
F2 F2
VSSQ7 VSSQ7
F8 F8
2

VSSQ8 VSSQ8
J2 H2 J2 H2
(SSTL-1.8) VREF = .5*VDDQ VREF VSSQ9 VREF VSSQ9
H8 H8
VSSQ10 VSSQ10
1

A2 (SSTL-1.8) VREF = .5*VDDQ A2

1 NC#A2 1 NC#A2
R102 C223 E2 A3 C222 E2 A3
1K_0402_1% NC#E2 VSS1 NC#E2 VSS1
L1 E3 L1 E3
VGA@ 0.1U_0402_10V6K NC#L1 VSS2 0.1U_0402_10V6K NC#L1 VSS2
R3 J3 R3 J3
2 NC#R3 VSS3 2 NC#R3 VSS3
VGA@ R7 N1 VGA@ R7 N1
2

NC#R7 VSS4 NC#R7 VSS4

Close to U45C1 R8
NC#R8 VSS5
P9 Close to U45D1 R8
NC#R8 VSS5
P9

@ K4N51163QE-ZC25 @ K4N51163QE-ZC25

DDR2 BGA MEMORY

DDR2 BGA MEMORY

FBACLK1
34 FBACLK1

+1.8VS +1.8VS

1
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R86
R62
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C190 C175 C217 C218 C149 C163 C490 C489 C488 C487 C513 C499 C486 C503 C496 C494 243_0402_1% AT END
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 0.01U_0402_16V7K VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 0.01U_0402_16V7K VGA@
B VGA@ VGA@ B

2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 0.01U_0402_16V7K 1U_0402_6.3V4Z 0.1U_0402_16V4Z
FBACLK1#
34 FBACLK1#
Close to U7

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/07/10 Deciphered Date 2007/07/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM DDRB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 38 of 51
5 4 3 2 1
 5 4 3 2 1

PL16
PJPDC1 FBM-L11-160808-601LMT 0603~D
TYCO_1566065-2~D 2 1 DOCK_PSID ADPIN VIN
1
Low_PWR PL17
9 GND_4
2 FBMA-L11-322513-151LMA50T_1210~D
DC+_1
8
GND_3
3 1 2
DC+_2
7 4
GND_2 DC-_1
6 5 PR189
GND_1 DC-_2 1M_0402_1%~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D
MH1
MH2
D 1 2 D

100P_0402_50V8J~D

100P_0402_50V8J~D

100P_0402_50V8J~D
1

1
VIN

PC157

PC159
VS VIN

PC311

PC312

PC158

PC160

0.01U_0402_25V7K~D
2

1
PR191 PR192
@

1
PR190 10K_0402_5%~D 1K_0402_5%~D

PC161
82.5K_0402_1%~D 1 2 ACIN 19,28,40

2
PR193

2
8
22K_0402_1%~D
N41 1 2 N40 3 PU12A

P
+
1
N35 O
2

19.6K_0402_1%~D
.1U_0402_16V7K~D
-

G
1

1
1

1
LM393DR_SO8 PR195

PC162

PR194

4
PC163 PD1 10K_0402_5%~D
1000P_0402_50V7K~D RLZ4.3B_LL34

2
2

2
PR198
10K_0402_5%~D
2 1
RTCVREF
3.3V

8
5 PU12B

P
VIN +
7
O
6
-

G
2

LM393DR_SO8
Vin Detector

4
C PD3 C

PJP1
PD4 @ JUMP_43X118 RLS4148_LL34-2 Max. typ. Min.
1 1

BATT+ 2 1 1
1 2
2 L-->H 18.234 17.841 17.449
CH751H-40PT_SOD323-2 PR203
33_1206_5% VS
H-->L 17.597 17.210 16.813
2

PQ50
CHGRTCP 3 TP0610K-T1-E3_SOT23-3
1
0.22U_1206_25V7K

32.8
1

PR205
100K_0402_5%~D PC165
PC164

0.1U_0603_25V7K~D
2

PR206
2

22K_0402_1%~D
29 51ON# 1 2

+5VALWP +3VALWP
1

RTCVREF PR207
B 200_0805_5% B
3.3V

DA204U_SOT323~D
PU14G920AT24U_SOT89-3
2

2
@ PR208

PD5

2.2K_0402_5%~D
3 2 1 2
OUT IN

2
0_0402_5%~D
1
4.7U_0805_6.3V6K~N

GND
1

PC167
PC166

PR209
1U_0805_25V4Z~D PR212
2

1
1 PJP2 PQ53 33_0402_5%~D
2

1
@ JUMP_43X118 DOCK_PSID 1 3 1 2

S
PS_ID 28
+1.2VSP 1 2 +1.2VS
1 2 FDV301N_NL_SOT23-3~D

G
2
+5VALWP

15K_0402_1%~D 100K_0402_1%~D
2
+5VALWP
PJP3 PJP4

PR213

DA204U_SOT323~D
@ JUMP_43X118 @ JUMP_43X118
1 2 1 2

10K_0402_1%~D
+5VALWP 1 2 +5VALW 1 2 +1.5VS

2
+1.5VSP

PD6
1
2

1
C

PR214
PJP5 PJP6 2 PQ54
@ JUMP_43X118 @ JUMP_43X118 B MMST3904-7-F_SOT323-3 @

2
1 2 1 2 E
+0.9VSP +0.9VS

2
1 2 1 2
PR215

1
@
1

PJP7 PJP8 PD7 PR216

@ JUMP_43X118 @ JUMP_43X118 SM24_SOT23 1 2 PSID_DISABLE# 28
1

+3VALWP 1 2 +3VALW +VCCPP 1 2 +VCCP

1 2 1 2 @ 10K_0402_1%~D

PJP9 PJP10
A @ JUMP_43X118 @ JUMP_43X118 A

+1.8VP 1 2 +1.8V 1 2
1 2 1 2

PJP11
@ JUMP_43X118 PJP12
1 1 @ JUMP_43X118
2 2
+VGA_COREP 1 2
1 2 +VGA_CORE Security Classification Compal Secret Data
PJP13 2006/10/1 2007/5/01 Title
@ JUMP_43X118 PJP14
Issued Date Deciphered Date
1 2 @ JUMP_43X118
DCIN / Precharge
+1.25VSP 1 2 +1.25VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 2 Size Document Number Rev
1 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JAL30 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 39 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 A B C D E

PQ55 PQ56 B+
VIN FDS4435BZ_SO8 FDS4435BZ_SO8
PR217
8 1 1 8 0.015_2512_1%
D S S D

0.01U_0402_25V7K~D
7 2 2 7 PJP15
D S S D CHG_B+
6 3 3 6 1 4 2 1
D S S D 2 1

1
5 4 4 5
D G G D

2
1_1210_5%~D 1_1210_5%~D

PC171

PC315

PC172

PC316

PC173
2 3 @ JUMP_43X118 PC168 PR218

1
100K_0402_1%~D

2
PR339

0.01U_0402_25V7K~D

1
2

100K_0402_1%~D

CHGEN#

2
1

1000P_0402_50V7K~D

1000P_0402_50V7K~D
PC170 PC175 PC177

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

1
2

5
6
7
8

1
0.01U_0603_50V7K~D

PC174

PR219
.1U_0402_16V7K~D PU15 0.1U_0805_25V7K

1 2

1
1 1 2 1 28 1 2 PQ57 /BATDRV 1
CHGEN PVCC

2
1

4
3
2
1
PR272

AO4712_SO8
PR220

2
PC178 PC176 2.2_0603_5%~D PQ58

G
S
S
S
0.1U_0603_25V7K~D @0.1U_0603_25V7K~D 27 1 2 4 FDS4435BZ_SO8

2
BTST

2
2

PR221

D
D
D
D
340K_0402_1%~D 2 26 DH_CHG
ACN HIDRV
3

3
2
1

5
6
7
8
ACP PR222

1
2

4 25 LX_CHG PL18 0.02_2512_1%

PC169 ACDET ACDRV PH PD8 10UH_SIL1045RA-100PF_4.5A_30% BATT+
5
2.2U_0805_25V6K ACDET
2 1 1 2 1 2 1 4
1

10U_1206_25V6M~D
RLS4148_LL34-2 PC179

REGN
2 3

2
PR224 0.1U_0603_25V7K~D

10U_1206_25V6M~D
5
6
7
8

PC181
PR223 56.2K_0402_1% ACSET

PC180
2
54.9K_0402_1% 1 2 6 PQ59
VREF ACSET
24 AO4712_SO8

2
REGN

1
1

1
1

1
PR225 PC183
PC182 100K_0402_1%~D 4
0.01U_0402_25V7K~D 1U_0603_10V6K~D

2
2

2
90W adapter 1 2 7
ACOP
PR226 PC184 23 DL_CHG

3
2
1
LODRV
Icharge=(Vsrset/Vvdac)*(0.1/PR34)=3A 340K_0402_1%~D CP setting 0.47U_0603_16V7K~N
1

Iadapter=(Vacset/Vvdac)*(0.1/PR217)=4.27A PGND
22
OVPSET 8 PC185
OVPSET .1U_0402_16V7K~D
Input OVP : 22.3V
1 2
2 Input UVP : 17.26V 9 21 2
AGND LEARN ACOFF 28
2

1
Fsw : 300KHz PR227
54.9K_0402_1% VREF PC186 PC187
20 CELLS 0.1U_0603_25V7K~D @0.1U_0603_25V7K~D

2
CELLS
1

10
PQ60 VREF
3

1
SI2301BDS-T1-E3_SOT23-3 PC188
1U_0603_10V6K~D
VREF PR228 19

2
100K_0402_1%~D SRP
CELLS GND 3 Cell
1 2 2 11 18
VDAC SRN
2

VREF 4 Cell
PR229 17
BAT
1

100K_0402_1%~D

1
PC189 VADJ 12
0.1U_0603_25V7K~D VADJ PC190
1

ACSET 0.1U_0603_25V7K~D

2
CELLS 29
TP RTCVREF
ACGOOD# 13
ACGOOD ICHG setting
1

D VREF
2 3cell/4cell# 47 PR231
G 16 2 1 IREF 28
SRSET

2
S PQ61 /BATDRV 14 49.9K_0402_1%~D @
3

BATDRV

1
SSM3K7002F_SC59-3 PR232 PR230

1
PR234 100K_0402_1%~D
Cells selector IADAPT
15 1 2 100K_0402_1%~D PC191
@0.01U_0402_25V7K~D
100K_0402_1%~D

1
BQ24751ARHDR_QFN28_5X5 PR233

2
10_0603_5%~D ACIN 19,28,39

1
3 D @ 3
28 ADP_I ACGOOD# 2 PQ62
G SSM3K7002F_SC59-3

1
S

3
PC192 IREF Current
100P_0402_50V8J~D

2
2.968V 3A
PR235 +COINCELL
PQ63
B+ 1 2 3 TP0610K-T1-E3_SOT23-3
1 B+_BIAS
COIN RTC Battery
470K_0402_5%~D

100_0805_5%~D 32.8
1

VREF
0.1U_0805_25V7M~N
2

+5VALW PR1 REGN

1K_0402_5%~D
PR236

PC193

2
1

RTCVREF PR237
2

1
100K_0402_1%~D
1
1
220K_0402_5%

1SS355_SOD323-2

PD9 PR51
Z4012
2

@ 0_0402_5%~D

1
PR238

PR53
4.32K_0402_1%~D CHGEN#

2
2

PJP24 28 CHGVADJ 1 2 VADJ

2

1
D
32.8 +COINCELL 1
1

1
1

1
PQ64 D +RTC_CELL PQ65
2 28 FSTCHG 2
2 PR54 SSM3K7002F_SC59-3
2 3 G
RHU002N06_SOT323 G1 10K_0402_1%~D
0.1U_0603_25V7K~D

G 4 S

3
G2
220K_0402_5%

S PD2
3

1
2

BAT54CW_SOT323~D ACES_85204-02001

2
1
PC194

PR239

4 4
1
27.4 PC1
2

1U_0603_10V4Z~D
1

2 Move to power schematic

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/1 Deciphered Date 2007/5/01 Title
Charger/RTC BATTERY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B JAL30 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 40 of 51
A B C D E
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PJP20 PR240
@ JUMP_43X118 0_0805_5%
1 2 1 2
1 2

2200P_0402_50V7K~D

2200P_0402_50V7K~D
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
VL

5
6
7
8
PC195

PC196

PC197
PQ66

8
7
6
5

1
PC200
D D

PC198

PC199
PQ67

1U_0603_10V6K~D

2
2
PC201

4.7U_0805_6.3V6K~N
0.1U_0603_25V7K~D 4

1
PC202
4

PC203
1
+5VALWP

2
AO4466_SO8

3
2
1
AO4466_SO8

1
2
3
PL21

7
PL20 PU16 PC207 2 1
1 2 1U_0603_10V6K~D 4.7UH_SIL104R-4R7PF_5.7A_30%

LDO
VIN

VCC
+3VALWP 4.7UH_SIL104R-4R7PF_5.7A_30% 33 19 1 2
TP PVCC

8
7
6
5

5
6
7
8

1
680P_0603_50V8J~D 4.7_1206_5%~D
1

@ PR242
680P_0603_50V8J~D 4.7_1206_5%~D
PQ68 DH3 26 15 DH5 PQ69
UGATE2 UGATE1

@ PR241
AO4712_SO8 PR243 PR245
0_0402_5%~D

2 1 BST3A 24 17 BST5A 2 1 AO4712_SO8

BOOT2 BOOT1
2

1 0_0603_5%~D

2
2

2
PR244

61.9K_0402_1%~D
4 0_0603_5%~DPC208 4

2
PC204 + PC205

2
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D

1
1

PR246
220U_6.3V_M LX3 25 16 LX5 1
1

2 PHASE2 PHASE1

PC206

PC209
1
2
3

3
2
1

2
+ PC210

2
DL3 23 18 DL5 @ 220U_6.3V_M

1
LGATE2 LGATE1
10K_0402_1%~D

@
2
2

22
PGND

2
PR247

C FB3 30 C
OUT2

10K_0402_1%~D
PR248
10
OUT1
32
VL
1

REFIN2

1
@ 11 FB5
2VREF_ISL6237 FB1

1 2 1
REF
PC211 0.22U_0603_10V7K~D
9
BYP
8
LDOREFIN @ PR249 0_0402_5%~D
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical) SKIP
29 2 1 VL
PR250 0_0402_5%~D
1 2
3.3VALWP PD10 PR251
20
NC POK2
28

Imax=6A VS RLZ5.1B_LL34 100K_0402_1%~D

POK
1 2 1 2 4 13 PR253
EN_LDO POK1
2
200K_0402_5%~D

330K_0402_1%
Iocp=10.133A
2
PR252

PC212 14 12 ILM1 2 1
0.22U_0603_25V7-K EN1 ILIM1
PR255
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
2
B 330K_0402_1% B

0_0402_5%~D
@ PR254 ISL6237IRZ-T_QFN32_5X5

21
VL 0_0402_5%~D
806K_0603_1%

PR256
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
2

1
PR257

2VREF_ISL6237 1
PR260

1
PR259
@ 47K_0402_5%~D
PC308
PR258
@
5VALWP
1

2 1 1 2 1U_0603_10V6K~D Imax=6A
2

2VREF_ISL6237 2
47 MAINPWON 0_0402_5%~D
0.047U_0402_16V7K~N

0_0402_5%~D

Iocp=10.146A
1

PC213
2

0.047U_0603_16V7K~D

PC214
2

PQ74
TP0610K-T1-E3_SOT23-3
@
1 3

PD16
1 2

A 1SS355TE-17_SOD323-2 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/1 Deciphered Date 2007/05/30 Title
+3VALWP, +5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JAL30 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 41 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

PC215 PC216

1
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D

2
PGOOD1 PGOOD2 串1K電電 上@ 2
PR261
1 1
PR262
2
+5VALWP +5VALWP
2.2_0603_1%~D 2.2_0603_1%~D

PJP21 +5VALWP
@ JUMP_43X118

1
B+ 1 2 PC217 PC218
D 1 2 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D D
ISL6228_B+

2
1
680P_0402_50VK X7R
470P_0402_50V8J~D
1

1
PR263 ISL6228_B+ 2 PR264 1 2 PR265 1 ISL6228_B+

PC313

PC314
1K_0402_1%~D 10_0603_1% 10_0603_1%
2

2
@

2
PC220
1000P_0402_50V7K~D PR267

1
PR266 18.2K_0402_1%~D
1000P_0402_25V8-J 3.3K_0402_5%~D PR268 PC219 22K_0402_1%~D
45.3K_0402_1%~D 1000P_0402_50V7K~D
PR269

1
PC221
2 1 1 2

1
PR270

1
2 1
29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
68K_0402_1% GND_T

2
PR271 PR290 PR273 3.3K_0402_5%~D
1 2 8 28 2 1 90.9K_0402_1%~N PR274 1000P_0402_25V8-J
FB1 PGOOD2 +5VALWP 39,41 PC222
12.1K_0402_1% 1K_0402_1%~D 2 1 1 2

1
@
ISL6228_B+ PR275
9 27 1 2
VO1 FB2
68K_0402_1%
4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

1
PC225

PC223

8
7
6
5

PC224 PQ70 PR276

0.033U_0402_16V7K~D 10 26 1 2
2

OCSET1 VO2
1 2
AO4466_SO8 12.1K_0402_1%
C C
2

4
PR278 1.5V_EN 11 25
PR279 EN1 PU17 OCSET2 PR280
12.1K_0402_1% 1 2 0_0402_5%~D
ISL6228HRTZ-T_QFN28_4X4 1 2 ISL6228_B+
1

1
2
3

PL23 0_0603_5%~D SUSP# 26,28,31,45

+1.5VSP 1 2 LX_1.5V 12 24 0.033U_0402_16V7K~D

PHASE1 EN2 PC228

4.7U_1206_25V6K~D

4.7U_1206_25V6K~D
1

5
6
7
8

1
1.8UH_SIL104R-1R8PF_9.5A_30% PQ72 PC230

PC229

PC226
1 2
8
7
6
5

1 PR281 1 2
220U_D2_4VM

4.7_1206_5%~D PQ71 0.01U_0402_25V7K~D

2
+ AO4712_SO8 UG_1.5V @
PC227

13 23
680P_0603_50V8J~D

UGATE1 PHASE2

2
PR282
2

4 12.1K_0402_1%
2 4 PR284 AO4466_SO8
1

0_0603_5%~D
PC231

2 1 2 1BST_1.5V 14 22 UG_VCCPP 1 2

1
BOOT1 UGATE2 PL24
2

3
2
1
LGATE1

LGATE2
PC232 PR283 LX_VCCPP
PGND1

PGND2

BOOT2
1 2
PVCC1

PVCC2
+VCCPP
1
2
3

1
.1U_0402_16V7K~D 0_0603_5%~D
DCR 10m ohm(max)

220U_D2_4VM
5
6
7
8
PR285 1.8UH_SIL104R-1R8PF_9.5A_30%
PQ73 4.7_1206_5%~D
1.5VP AO4712_SO8
1
15

16

17

18

19

20

21
Imax=5A +

PC233
PC234

680P_0603_50V8J~D
2
PR286 4 DCR 10m ohm(max)

1
2
Iocp=9A +5VALWP BST_VCCPP

PC237
+5VALWP 1 2 1 2
+VCCPP
2

2
2.2_0603_5%~D.1U_0402_16V7K~D

2
PC235 PC236 Imax=5A

3
2
1
1U_0402_6.3V6K~D 1U_0402_6.3V6K~D
1

1
Iocp=9A
LG_1.5V LG_VCCPP

B B
PR287
0_0402_5%~D
2 1 1.5V_EN
26,28,31,45 SUSP#
1

0.01U_0402_25V7K~D
PC238

@
2

A A

Security Classification Compal Secret Data

2006/10/1 2007/5/01 Title
Issued Date Deciphered Date
+1.5VP/VCCPP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JAL30 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 42 of 51
5 4 3 2 1
 5 4 3 2 1

D PJP22 D
@ JUMP_43X118
1 2 6269_B+
B+ 1 2

10U_1206_25V6M~D

10U_1206_25V6M~D
PHASE_1.8V

PC286

1
6269_1.8V UG_1.8V

PC287
PR341

1
1 2 1 2 AO4712

2
@ PR340
10K_0402_1%~D 0_0603_5%~D
+5VALW
PC288 Rds(on)=15mohm~18mohm
0.1U_0603_25V7K~D

1
BOOT_1.8V 1.8VP
PR342

5
6
7
8
0_0603_5%~D Imax=9A

17

16

15

14

13
PU23 PR343 4.7_0603_5%

2
1 2 6269_1.8V PQ79 Iocp=12.6A

PHASE

UG
GND

PGOOD

BOOT
AO4466_SO8
PC289 4
1 12 1 2
VIN PVCC
2.2U_0603_6.3V6K~D

3
2
1
6269_1.8V LG_1.8V
C
2
VCC LG
11 PL31
1.8UH_SIL104R-1R8PF_9.5A_30%
+1.8VP C
1

PR344 1 2 +1.8VP
PC290 0_0402_5%~D

2
2.2U_0603_6.3V6K~D 1 2 3 10 1
2

FCCM PGND

5
6
7
8
PR346
PR345 4.7_1206_5%~D + PC291
22K_0402_1%~D PQ80 220U_6.3V_M
1 2 4 9 ISEN_1.8V
1 2 AO4712_SO8

2 1
28,31 SYSON EN ISEN 2
PR347 4 PC293

COMP
1

2
FSET
PC292 16.5K_0402_1%~D 680P_0603_50V8J~D

VO
PR348

FB

1
.1U_0402_16V7K~D 2K_0402_1%~D
2

3
2
1
ISL6269CRZ-T_QFN16_4X4~N

1
1
68P_0402_50V8J~N
1

PR349

1
2200P_0402_25V7K~N
PC294

1
2

33K_0402_1%~D PC295
PR350 0.01U_0402_25V7K~D

2
1
PC296

57.6K_0402_1%
2

1
PR351
2

B 1K_0402_1%~D B

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/1 Deciphered Date 2007/05/30 Title
NB_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JAL30 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 43 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

D @ PJP23 D
JUMP_43X118
1 2 6269_B++
B+ 1 2

10U_1206_25V6M~D
6269_VGA

10U_1206_25V6M~D
PHASE_VGA

PC297

1
UG_VGA

PC298
10K_0402_1%~D PR353
VGA@ PR352 1 2 1 2 AO4712

2
VGA@
2.2_0603_5%~D PC299 0.1U_0603_25V7K~D Rds(on)=15mohm~18mohm

2
VGA@ +5VALW VGA@
31 VGA_PWGOD

1
VGA@ BOOT_VGA +VGA_COREP
PR354

5
6
7
8
0_0603_5%~D Imax=9A

17

16

15

14

13
PU24 PR355 4.7_0603_5%

2
1 2 6269_VGA PQ81 Iocp=12.6A

PHASE

UG
GND

PGOOD

BOOT
VGA@ AO4466_SO8
PC300 4 VGA@
1 12 1 2 VGA@
VIN PVCC
2.2U_0603_6.3V6K~D

3
2
1
6269_VGA LG_VGA
C
2
VCC LG
11 PL33
1.8UH_SIL104R-1R8PF_9.5A_30%
+1.15V C
1

PR356 1 2 +VGA_COREP
PC301 0_0402_5%~D

2
2.2U_0603_6.3V6K~D 1 2 3 10 VGA@ 1
2

FCCM PGND

5
6
7
8
VGA@ PR359
PR357 VGA@ 4.7_1206_5%~D + PC302
22K_0402_1%~D PQ82 VGA@ 220U_6.3V_M
1 2 4 9 ISEN_VGA
1 2 AO4712_SO8 VGA@
VGA@

2 1
28 VGA_ON EN ISEN 2
PR358 4 PC304

COMP
1

2
FSET
PC303 16.5K_0402_1%~D 680P_0603_50V8J~D
VGA@

VO
.1U_0402_16V7K~D VGA@ PR360

FB
VGA@

1
2K_0402_1%~D
2

VGA@
VGA@

3
2
1
ISL6269CRZ-T_QFN16_4X4~N

1
VGA@
1
68P_0402_50V8J~N
1

PR361

1
2200P_0402_25V7K~N
PC305

33K_0402_1%~D

1
VGA@
2

VGA@ PC306
PR362 VGA@ 0.01U_0402_25V7K~D

2
1
PC307

57.6K_0402_1% VGA@
2

1
PR363 VGA@
2

B 2.15K_0402_1%~D B
VGA@

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/10/1 Deciphered Date 2007/05/30 Title
+VGA_COREP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS JAL60 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 44 of 51
5 4 3 2 1
 5 4 3 2 1

+5VALW +1.5VSP

PJP16
VGA@

2
@ JUMP_43X118

1U_0603_10V6K~D

2
1

PC263

1
D +1.8V D

1U_0603_10V6K~D
1

PC264

1
VGA@
PJP17

1
2
@ JUMP_43X118

6
PU19

2
5

VCNTL
VIN
7

2
POK
3 +1.2VSP
VOUT PU20
4 1 6

1K_0402_1%~D

1U_0603_10V6K~D

1U_0603_10V6K~D
VOUT VIN VCNTL +3VALW
PR315

1
PC266

PC267
1 2 8 2 2 5

4.7U_0805_6.3V6K~N
EN FB GND NC

1
26,28,31,42 SUSP# PC265

VGA@

PR316

PC268
GND

1
0_0402_5%~D 9 VGA@ 3 7

2
VIN VREF NC

2
VGA@ PR317 4 8

2
APL5913-KAC-TRL_SO8~N 0.01U_0402_25V7K~D 1K_0402_1%~D VOUT NC
VGA@ VGA@ 9

2
TP
1

PC269 APL5331KAC-TRL_SO8~N

1
.1U_0402_16V7K~D PR318

2K_0402_1%~D
2

@ +0.9VSP

1
0_0402_5%~D D

PR319

1
VGA@ 1 2 2

1U_0603_10V6K~D
1
25,31 SUSP PR320 PC270

PC271
G

2
S

2
1
PQ78

2
PC272
@

2
C .1U_0402_16V7K~D C
RHU002N06_SOT323 1K_0402_1%~D.1U_0402_16V7K~D

+5VALW +1.5VSP

PJP18

2
@ JUMP_43X118
1U_0603_10V6K~D

2
1

PC273

1
2

1U_0603_10V6K~D
1

PC274
2
6

PU21
5
VCNTL

VIN
7
POK
3 +1.25VSP
VOUT
4
1.15K_0402_1%

1U_0603_10V6K~D
PR321 VOUT
1

26,28,31,42 SUSP#
1 2 8
EN FB
2 PC276
PC275
PR322
GND

0_0402_5%~D 9
2

VIN
1

B APL5913-KAC-TRL_SO8~N 0.01U_0402_25V7K~D B
1

PC277
1

.1U_0402_16V7K~D
2.05K_0402_1%~D
2

@
PR323
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
+1.25VSP / +0.9VSP/ +1.2VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JAL30 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 45 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com
 5 4 3 2 1

+5VS

2
5

5
PC112

CPU_VID6

CPU_VID5

CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR142 +CPU_B+

28
PL13

VR_ON
2 1 1_0603_5%~D
FBMA-L18-453215-900LMA90T_1812
@ 1 2 B+

1
5600P_0402_25V7K
1 1

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

100U_25V_M

100U_25V_M
1U_0603_10V6K~D
D D

1
PC114

PC115

PC116

PC113

PC155
+ +

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D
PR143 499_0402_1%~D

1
PC118

PC119
1U_0603_10V6K~D
7,19 DPRSLPVR 1 2

1
PC117

PC120

2
PR144 0_0402_5%~D @ 2 2

2
5,7,18 H_DPRSTP# 1 2

5
PR1460_0402_5%~D

PR1470_0402_5%~D

PR1480_0402_5%~D

PR1490_0402_5%~D

PR1500_0402_5%~D

PR1510_0402_5%~D

PR1520_0402_5%~D
PR145 0_0402_5%~D

1
16 CLK_EN# 1 2

1
0_0402_5%~D
+3VS PR154 0_0402_5%~D PQ43

PR153
1 2 4 SI7686DP-T1-E3_SO8

2
+3VS

1U_0603_10V6K~D
PC122

2
1.91K_0402_1%~D

1
PC121
PR155 0.22U_0603_10V7K~D P_0.36H_ETQP4LR36WFC_24A_20%

3
2
1
1 BOOT_CPU1 1 2 1 2 2 1 +CPU_CORE
2

PR156

4.7_1206_5%~D
PR157

1
10K_0402_1%~D
3.65K_1206_1%
2.2_0603_5%~D PQ44 @ PQ45 PL14

1
PR158

PR160
SI7636DP-T1-E3_SO8
499_0402_1%~D

49

48

47

46

45

44

43

42

41

40

39

38

37

PR159
SI7636DP-T1-E3_SO8
PR161
2

1_0402_5%~D

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

680P_0603_50V8J~D
1 2

2
19,28 VGATE 1 36 4 4 PR162 @ 0_0402_5%~D

2
PGOOD BOOT1 G G

PC123
5 H_PSI# 1 2
2 35 UGATE_CPU1 VSUM PC124
PSI# UGATE1

S
S
S

S
S
S
POW_MON 28 PC147 PR181 10K_0402_1%~D 1 2

2
1U_0603_10V6K~D
1 2 1 2 3 34 PHASE_CPU1 VCC_PRM

3
2
1

3
2
1
PMON PHASE1 ISEN1
C PR164 147K_0402_1%~D 4 33 0.22U_0603_16V7K~D C
RBIAS PGND1
1 2
VR_TT# 5 32 LGATE_CPU1
VR_TT# LGATE1 +CPU_B+

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
PR165 @ 4.22K_0402_1% PH2

1
1 2 1 2 6 31
NTC PVCC

PC125

PC126

PC127
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2

2
SOFT LGATE2 PQ46
1 2 @
@ 0.015U_0402_16V7K PC128 8 29 SI7686DP-T1-E3_SO8
0.068U_0603_50V7K~N PC129 OCSET ISL6262ACRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2
PR166 11.5K_0402_1%~D 10 27 UGATE_CPU2 P_0.36H_ETQP4LR36WFC_24A_20%
COMP UGATE2 PR167 PC130
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 2 1
PC131 FB BOOT2 PL15
1 2

1
DROOP

1000P_0402_50V7K~D 12 25 0.22U_0603_10V7K~D
2.2_0603_5%~D PQ48
FB2 NC

1
VDIFF

ISEN2

ISEN1
VSUM

10K_0402_1%~D
VSEN

PR169 6.81K_0402_1%~D PQ47 PR168

GND

D
VDD
RTN

DFB

1
VIN

SI7636DP-T1-E3_SO8

3.65K_1206_1%

PR170
4.7_1206_5%~D
VO

1 2 PR172

SI7636DP-T1-E3_SO8

PR171
1 2 PU11 1_0402_5%~D
13

14

15

16

17

18

19

20

21

22

23

24

1 2
4

2
PC132 1000P_0402_50V7K~D G
4

2
29.1
ISEN1 G PC133 PR173 @ 0_0402_5%~D

S
S
S
ISEN2 680P_0603_50V8J~D 1 2

2
S
S
S
PR175 97.6K_0402_1%~D
PC134 470P_0402_50V7K~D 1 2 +5VS

3
2
1
1

1 2 2 1 VSUM PC135

3
2
1
1

PR174 1_0603_5%~D 1 2
PR176 PC136 @
B 1K_0402_1%~D 1U_0603_10V6K~D 0.22U_0603_16V7K~D B
1 2
2
2

PC137 220P_0402_50V7K~D VCC_PRM

ISEN2
PR178
PR177 PC138 1000P_0402_50V7K~D
1 2 1 2 1 2 +CPU_B+
1

255_0402_1%~D
1 2 PC139 10_0603_5%~D
0.1U_0603_25V7K~D
2

PR179 1K_0402_1%~D
PC140 0.022U_0603_25V7K
5 VCCSENSE 1 2 1 2
VSUM
1

PR180 0_0402_5%~D
1

2.61K_0402_1%~D

PC141 PC142
PR182

@0.022U_0603_25V7K 0.022U_0603_25V7K
2

1 2
5 VSSSENSE PR183 0_0402_5%~D
2
1

11K_0402_1%~D

PC143 180P_0402_50V8J~D
PR185

1 2
2

1 2 1 2 PH3
2

PR186 1K_0402_1%~D PR187 3.57K_0402_1%~D 10KB_0603_ERTJ1VR103J

PC144 0.068U_0603_50V7K~N
1

VCC_PRM 1 2

A
PC146 0.22U_0603_10V7K~D A
PC145 2 1 2 1
0.22U_0603_16V7K~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JAL30 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 46 of 51
5 4 3 2 1
 5 4 3 2 1

+3VALWP

DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D
3

2
PD12

PD13

PD14

PD15
@

D BATT+ @ D
BATT++

Battery Connect/OTP

1
@ @
BATT+

PL28
HCB4532KF-800T90_1812
1 2 BATT++
+3VALWP

1
100P_0402_50V8J~D

1000P_0402_50V7K~D

100P_0402_50V8J~D
1

1
PC279
PC278
PC309

PC310
2

2
0.01U_0402_25V7K~D
2

2
PR324 Place clsoe to EC pin
47K_0402_5%~D
1 2 BATT_TEMP
BATT_TEMP 28

1
PR325

2
1K_0402_5%~D
PC280
PJPB1 battery connector .1U_0402_16V7K~D

1
PJP19
SMART

@
1 PR326
1
Battery: 2
2
3 3cell/4cell# 1K_0402_5%~D
3 3cell/4cell# 40
4 4 2 1
1.BAT+ 5
5 1 2 +3VALWP
6
2.BAT+ 6
7 PR327
7
3.ID 10
GND 8
8 6.49K_0402_1%~D
11 9
4.B/I GND 9

5.TS SUYIN_200275MR009G186ZL 1 2
C
EC_SMB_DA1 28 C
6.SMD @ PR328
100_0402_5%~D
7.SMC
8.GND CPU
9.GND 1 2 EC_SMB_CK1 28 PH1 under CPU botten side :
PR329
100_0402_5%~D
CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VL VS
BATT+
1

2
PR330

1
453K_0402_1%~D PC281
0.1U_0603_25V7K~D
CPU

1
VS
2

PR331
10.7K_0402_1%~D VL

2
1

PR333
0.01U_0402_25V7K~D

PR332 147K_0402_1%~D

2
499K_0402_1%~D 1 2
1

PR334
PC282

B 205K_0402_1%~D B
2
2

PR335

1
8
61.9K_0402_1%~D
1 2 3 PD11

P
+
8

LM358ADR_SO8 1 1 2
0 MAINPWON 41
5 1 2 2
P

+ VL -

G
7 1SS355_SOD323-2
0 PR336 PU22A
6

4
-
G

1
28 BATT_OVP 150K_0402_1%~D LM358ADR_SO8
1

PH4
4

1
PU22B 100K_0603_1%_TH11-4H104FT

1
PR337
86.6K_0402_1% PC283 PR338

2
1000P_0402_50V7K~D 150K_0402_1%~D
2

2
2
PC284
1U_0603_10V6K~D

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/1 Deciphered Date 2007/05/30 Title
BATTERY CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JAL30 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 47 of 51
5 4 3 2 1

GRATIS - FOR FREE

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 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/1

Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
1 41 +3VALWP/+5VALWP 07/11/19 COMPAL When in the DC-mode , shut down the system ,5valwp output not turn off ADD PQ76 to turn off 5VALWP wehn shut down the system in the DC-mode

D 2 40 Charge 07/11/25 COMPAL Change RTC circuitry part del PD16 PC285 PL29 JRTC1 D

3 40 Charge 07/11/25 COMPAL change charge voltage can to adjust ADD PR53 PR54

4 40 Charge 07/11/25 COMPAL increase Coin RTC battery circuitry ADD PD2 PR1 PC1

5 40 Charge 07/11/25 COMPAL increase BQ24751 Vin Detector function increase PR232

6 40 Charge 07/12/26 COMPAL change charge voltage can to adjust Change PR53 from 15K to 4.3K

7 42 1.5VSP/+VCCPP 07/12/26 COMPAL adjust 1.5VSP/+VCCPP OCP set Change PR271 PR276 PR278 PR282 from 9.09K to 12.1K

8 43 1.8VP 07/12/26 COMPAL adjust 1.8VP OCP set Change PR347 from 12.1K to 16.5K

9 44 VGA_CORE 07/12/26 COMPAL adjust VGA_CORE OCP set Change PR358 from 12.1K to 16.5K

10 41 +3VALWP/+5VALWP 07/12/26 COMPAL The schematic location doesn't correspond to PCBA Change location from PQ76 to PQ74

11 43 1.8VP 07/12/26 COMPAL delete resistor 0ohm for HW request DEL PR342

12 44 VGA_CORE 07/12/26 COMPAL delete resistor 0ohm for HW request DEL PR354
C C
13 46 CPU_CORE 07/12/26 COMPAL modify MOS type SO8 to Power Pack for height limit DEL PQ44 PQ48

14 43 1.8VP 08/01/04 COMPAL In order to replace IC for system request ADD PU23 PR342

15 44 VGA_CORE 08/01/04 COMPAL In order to replace IC for system request ADD PU24 PR354

16 41 +3VALWP/+5VALWP 08/01/04 COMPAL When in the DC-mode , shut down the system ,5valwp output not turn off ADD PD16 to turn off 5VALWP wehn shut down the system in the DC-mode

17 40 Charge 08/01/04 COMPAL adjust battery charge voltage set CHANGE PR53 from 15K to 4.3K

18 40 Charge 08/01/04 COMPAL VIN Detector has the same function DEL PR230 PQ62

19

20
08/01/04 COMPAL Increase Resistor on charge boot for EMI request CHANGE PR220 PR286from 0 to 2.2 ohm
21
08/01/04 COMPAL Increase Capacitor on charge boot for EMI request ADD PC123 PC133 PC231 PC237 PC309 PC310 PC311 PC313 PC312 PC314 PC293
22
08/01/04 COMPAL Increase Resistor on charge boot for EMI request ADD PR158 PR168 PR285 PR281 PR346

B 23 08/01/04 COMPAL Increase Bead on charge boot for EMI request ADD PL17 PL28 B

24

25

26

27

28

29

30

31

32

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PW PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3682P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 48 of 51
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) Page 1/1

Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
1 25 OZ129_Card Reader/1394 07/10/30 compal CardBus vendor change CardBus R5C833 change to OZ129 0.3

D 2 28 EC KB926/REED SW/TPM1.2 07/10/30 compal Change pull up resistance Change EC pin17,18 pull up to 4.7Kohm 0.3 D

3 28 EC KB926/REED SW/TPM1.2 07/10/30 compal Need pull up NET MIC_DIAG pull up R to 10Kohm 3VS 0.3

4 13,14 DDR2 SODIMM-I,II Socket 07/10/30 compal Change Capacitance Change C84,C189 to SGA00002680 330U 0.3

5 28 EC KB926/REED SW/TPM1.2 07/10/30 compal EC update rev EC change to 926C 0.3

6 31 DC/DC Interface 07/10/30 compal Need pull down SYSON pull down 10K ohm 0.3

7 31 DC/DC Interface 07/11/12 compal Delete Remove SIM card connector 0.3

8 15 CRT Conn.& LCD Conn. 07/11/16 compal Add LCD control pin Add LCD control pin LCD_DET# & LCD_TST & LCD_VCC_TEST_EN 0.3

9 30 USB/ BT/ FP/ Felica/Camera 07/11/22 compal support wake up by USB key change U32, U33 from 3VS to 3VALW 0.3

10 28 EC KB926/REED SW/TPM1.2 08/01/07 compal Change for quick-set function ADD W_DISABLE#, WL_DIS#, BT_DIS# 0.4

11 29 PWR_OK/ BTN/ KB / TouchPad 08/01/08 compal Add Bead for EMI from function board ADD L93, L94 FOR ESB_DAT, ESB_CLK 1.0

12 25 OZ129_Card Reader/1394 08/02/25 compal For MS can't access after reboot ADD Q82, R932, DELETE C335 FOR CARD READER 1.0
C C
13 27 Mini Card/WLAN/WWAN/Robson 08/02/27 customer remove Robson & felica function Delete JMINI3 & JFE1 1.0

14

15

16

17

18

19

20

21

22

B 23 B

24

25

26

27

28

29

30

31

32

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EE PIR-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4231P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, March 17, 2008 Sheet 49 of 51
5 4 3 2 1

GRATIS - FOR FREE

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 5 4 3 2 1

JAL30 Power Bock

RTC Charger
Page 35

D D

Battery OVP CPU OTP

Page 35 Page 42
+CHGRTC
Vin Detector
Page 35
Turn Off Turn Off

Input B+
DC IN Switch Page 36 +3VALWP: OCP:6A OVP:107%~115%
+5VALWP: OCP:9.4A OVP:107%~115%
(TPS51120RHBR) Page 37
Always

C C
CHARGER
CC:0.6A~3.3A
CV:12.6V +1.5VSP
(ISL6251AHAZ-T) Thermal protection: 160 degree C
Page 36
+1.8V (G2992F) Page 40
SUSP

+1.8VP: OCP:11.77A OVP:110%~115% +1.8VP:SYSON

+1.5VSP: OCP:9.55A OVP:110%~115%
(ISL6227) Page 38
+1.5VSP:SUSP#

Battery
+1.5V +1.25VSP
Thermal protection: 160 degree C
B B
(G2992F) Page 40
SUSP#

CPU CORE
OCP:54A
OVP:2V
(ISL6262)
VR_ON +VCCPP:OCP:13.32A OVP:115%
Page 41
(ISL6268CAZ-T)
Page 39
SUSP#

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Block
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 50 of 51
5 4 3 2 1
 5 4 3 2 1

ACIN/BATT-IN

+5VALW/+3VALW

EC_ON

D D

ON/OFF

STB_SB (Control +3V_SB)

+3V_SB

RSMRST# T1>20ms

WOL_EN(Control +3VLAN)

+3VLAN

SYSON(Control +3V/+1.8V)

+3V/1.8V
C C

T2=40ms

PWRBTN_OUT#

T3<110ms
SLP_S5#

SLP_S4#

SLP_S3#

SUSP# T4=20ms

+5VS>3VS>1.5VS>1.25VS>+1.2VS>VCCP>0.9VS

VR_ON#/VGA_ON T5>30ms

B
+CPU_CORE B

T6= ~7ms
VGATE(IMVP to SB for VRMPWRGD/to EC for CPUCORE PWRGD)

CK_PWRGD(SB to CLK-GEN; Local AND of VRMPWRGD and S3 ) 100ns>T7>0ns

T8>99ms
T9>3ms
PM_PWROK(EC to SB/NB) T10>70ms

H_PWRGOOD(SB to CPU; Local AND of VRMPWRGD and PWROK)

PLTRST#(SB to NB/Device) 41RTCCLK>T11>34RTCCLK

H_RESET#(NB to CPU) T12>1ms

VGA_ON T13>30ms

A A

+VGA_CORE

VGA_PWGOD(Turn on 1.8VS for VRAM/VGA) T14= ~7ms

+1.8VS

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/1/15 Deciphered Date 2008/1/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power On Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-4121P
Date: Monday, March 17, 2008 Sheet 51 of 51
5 4 3 2 1

GRATIS - FOR FREE

hexainf@hotmail.com