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VHDL Math Tricks of

the Trade
by
Jim Lewis
Director of Training, SynthWorks Design Inc
Jim@SynthWorks.com

http://www.SynthWorks.com

Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003

SynthWorks
VHDL Math Tricks of the Trade
VHDL is a strongly typed language. Success in VHDL
depends on understanding the types and overloaded
operators provided by the standard and numeric
packages.

The paper gives a short tutorial on:


• VHDL Types & Packages
• Strong Typing Rules
• Converting between Std_logic_vector, unsigned &
signed
• Ambiguous Expressions
• Arithmetic Coding Considerations
• Math Tricks

Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P2
SynthWorks
Common VHDL Types
TYPE Value Origin
std_ulogic 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-' std_logic_1164
std_ulogic_vector array of std_ulogic std_logic_1164
std_logic resolved std_ulogic std_logic_1164
std_logic_vector array of std_logic std_logic_1164
unsigned array of std_logic numeric_std,
std_logic_arith
signed array of std_logic numeric_std,
std_logic_arith
boolean true, false standard
character 191 / 256 characters standard
string array of character standard
integer -(231 -1) to (231 - 1) standard
real -1.0E38 to 1.0E38 standard
time 1 fs to 1 hr standard

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SynthWorks
Packages for Numeric Operations
● numeric_std -- IEEE standard
● Defines types signed, unsigned

● Defines arithmetic, comparison, and logic operators for these types

● std_logic_arith -- Synopsys, a defacto industry standard


● Defines types signed, unsigned

● Defines arithmetic, and comparison operators for these types

● std_logic_unsigned -- Synopsys, a defacto industry standard


● Defines arithmetic and comparison operators for std_logic_vector

Recommendation:
Use numeric_std for new designs
Ok to use std_logic_unsigned with numeric_std*
* Currently, IEEE 1076.3 plans to have a numeric package that permits
unsigned math with std_logic_vector
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SynthWorks
Packages for Numeric Operations
● Using IEEE Numeric_Std Recommendation:
Recommendation:
Use
Use numeric_std
numeric_std for
for new
new designs
designs
library
library ieee
ieee ;;
use
use ieee.std_logic_1164.all
ieee.std_logic_1164.all ;;
use
use ieee.numeric_std.all
numeric_std
ieee.numeric_std.all ;; Use
Use numeric_std
numeric_std oror
std_logic_arith,
std_logic_arith, but
but
never
never both
both
● Using Synopsys Std_Logic_Arith
library
library ieee
ieee ;;
use
use ieee.std_logic_1164.all ;;
ieee.std_logic_1164.all
use
use ieee.std_logic_arith.all
std_logic_arith
ieee.std_logic_arith.all ;;
use
use ieee.std_logic_unsigned.all
ieee.std_logic_unsigned.all ;;

Recommendation,
Recommendation, ifif you
you use
use Synopsys
Synopsys Packages:
Packages:
Use
Use std_logic_arith
std_logic_arith for
for numeric
numeric operations
operations
Use
Use std_logic_unsigned
std_logic_unsigned only
only for
for counters
counters and
and testbenches
testbenches
Don't
Don't use
use the
the package
package std_logic_signed.
std_logic_signed.
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SynthWorks
Unsigned and Signed Types
● Used to represent numeric values:
TYPE Value Notes
unsigned 0 to 2NN - 1
signed - 2(N-1)
(N-1) to 2(N-1)
(N-1) - 1 2's Complement number

● Usage similar to std_logic_vector:


signal A_unsigned : unsigned(3 downto 0) ;
signal B_signed : signed (3 downto 0) ;
signal C_slv : std_logic_vector (3 downto 0) ;
. . .
A_unsigned <= "1111" ; == 15
15 decimal
decimal

B_signed <= "1111" ; == -1


-1 decimal
decimal

== 15
15 decimal
decimal only
only ifif using
using
C_slv <= "1111" ; std_logic_unsigned
std_logic_unsigned

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SynthWorks
Unsigned and Signed Types
● Type definitions identical to std_logic_vector
type UNSIGNED is array (natural range <>) of std_logic;
type SIGNED is array (natural range <>) of std_logic;

● How are the types distinguished from each other?


● How do these generate unsigned and signed arithmetic?
● For each operator, a unique function is called
function "+" (L, R: signed) return signed;
function "+" (L, R: unsigned) return unsigned ;

● This feature is called Operator Overloading:


● An operator symbol or subprogram name can be used

more than once as long as calls are differentiable.


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SynthWorks
Overloading Basics
● Simplified view of overloading provided by VHDL packages
Operator
Operator Left
Left Right
Right Result
Result
Logic
Logic TypeA
TypeA TypeA
TypeA TypeA
TypeA
Numeric Array Array Array1
Array Integer Array1
Integer Array Array1
Notes:
Notes:
Array
Array == unsigned,
unsigned, signed, std_logic_vector22
signed, std_logic_vector
TypeA
TypeA == boolean,
boolean, std_logic,
std_logic, std_ulogic,
std_ulogic, bit_vector
bit_vector
std_logic_vector, std_ulogic_vector,
std_logic_vector, std_ulogic_vector,
signed33,, unsigned
signed unsigned33
Array
Array and
and TypeA
TypeA types
types used
used in
in an
an expression
expression must
must be
be the
the same.
same.
1) for comparison operators the result is boolean
2) only for std_logic_unsigned.
3) only for numeric_std and not std_logic_arith

● For a detailed view of VHDL's overloading, get the VHDL Types and
Operators Quick Reference card at: http://www.SynthWorks.com/papers
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SynthWorks
Overloading Examples
Signal
Signal A_uv,
A_uv, B_uv,
B_uv, C_uv,
C_uv, D_uv,
D_uv, E_uv
E_uv :: unsigned(7
unsigned(7 downto
downto 0)
0) ;;
Signal
Signal R_sv,
R_sv, S_sv,
S_sv, T_sv,
T_sv, U_sv,
U_sv, V_sv
V_sv :: signed(7
signed(7 downto
downto 0)0) ;;
Signal
Signal J_slv,
J_slv, K_slv,
K_slv, L_slv
L_slv :: std_logic_vector(7
std_logic_vector(7 downto
downto 0)
0) ;;
signal
signal Y_sv
Y_sv :: signed(8
signed(8 downto
downto 0)
0) ;;
.. .. ..

--
-- Permitted
Permitted
A_uv
A_uv <=
<= B_uv
B_uv ++ C_uv
C_uv ;; --
-- Unsigned
Unsigned ++ Unsigned
Unsigned == Unsigned
Unsigned
D_uv
D_uv <=
<= B_uv
B_uv ++ 11 ;; --
-- Unsigned
Unsigned ++ Integer
Integer == Unsigned
Unsigned
E_uv
E_uv <=
<= 11 ++ C_uv;
C_uv; --
-- Integer
Integer ++ Unsigned
Unsigned == Unsigned
Unsigned

R_sv
R_sv <=
<= S_sv
S_sv ++ T_sv
T_sv ;; --
-- Signed
Signed ++ Signed
Signed == Signed
Signed
U_sv
U_sv <=
<= S_sv
S_sv + 1 ;;
+ 1 --
-- Signed
Signed ++ Integer
Integer == Signed
Signed
V_sv
V_sv <=
<= 11 ++ T_sv;
T_sv; --
-- Integer
Integer ++ Signed
Signed == Signed
Signed

J_slv
J_slv <=
<= K_slv
K_slv ++ L_slv
L_slv ;; --
-- if
if using
using std_logic_unsigned
std_logic_unsigned

--
-- Illegal
Illegal Cannot
Cannot mix
mix different
different array
array types
types
--
-- Solution persented later in type conversions
Solution persented later in type conversions
--
-- Y_sv
Y_sv <=
<= A_uv
A_uv -- B_uv
B_uv ;; --
-- want
want signed
signed result
result

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SynthWorks
Strong Typing Implications
● Size and type of target (left) = size and type of expression (right)
● Each operation returns a result that has a specific size based on
rules of the operation. The table below summarizes these rules.
Operation Size of Y = Size of Expression
Y <= "10101010" ; number of digits in literal
Y <= X"AA" ; 4 * (number of digits)
Y <= A ; A'Length = Length of array A
Y <= A and B ; A'Length = B'Length
W <= A > B ; Boolean
Y <= A + B ; Maximum (A'Length, B'Length)
Y <= A + 10 ; A'Length
V <= A * B ; A'Length + B'Length

Some think VHDL is difficult because of strong typing


Master the above simple rules and it is easy
Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P10
SynthWorks
Strong Typing Implications
signal A8, B8, Result8 : unsigned(7 downto 0) ;
signal Result9 : unsigned(8 downto 0) ;
signal Result7 : unsigned(6 downto 0) ;
. . .
-- Simple Addition, no carry out
Result8 <= A8 + B8 ;
-- Carry Out in result
Result9 <= ('0' & A8) + ('0' & B8) ;
-- For smaller result, slice input arrays
Result7 <= A8(6 downto 0) + B8(6 downto 0) ;

Strong Typing = Strong Error Checking Built into the Compiler


This means less debugging.
Without VHDL, you better have a good testbench and
lots of time to catch your errors.
Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P11

SynthWorks
Type Conversions
● VHDL is dependent on overloaded operators and conversions
● What conversion functions are needed?
● Signed & Unsigned (elements) <=> Std_Logic
● Signed & Unsigned <=> Std_Logic_Vector
● Signed & Unsigned <=> Integer
● Std_Logic_vector <=> Integer
● VHDL Built-In Conversions
● Automatic Type Conversion
● Conversion by Type Casting
● Conversion functions located in Numeric_Std

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SynthWorks
Automatic Type Conversion:
Unsigned, Signed <=> Std_Logic
● Two types convert automatically when both are subtypes of the same type.
subtype
subtype std_logic
std_logic is
is resolved
resolved std_ulogic
std_ulogic ;;

● Converting between std_ulogic and std_logic is automatic

● Elements of Signed, Unsigned, and std_logic_vector = std_logic


● Elements of these types convert automatically to std_ulogic or std_logic

Legal A_sl
A_sl <=
<= J_uv(0)
J_uv(0) ;;
Assignments B_sul <= K_sv(7) ;
L_uv(0) <= C_sl ;
M_slv(2) <= N_sv(2) ;

Implication: Y_sl
Y_sl <=
<= A_sl
A_sl and
and B_sul
B_sul and
and
J_uv(2)
J_uv(2) and
and K_sv(7)
K_sv(7) and
and M_slv(2);
M_slv(2);

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SynthWorks
Type Casting:
Unsigned, Signed <=> Std_Logic_Vector
● Use type casting to convert equal sized arrays when:
● Elements have a common base type (i.e. std_logic)
● Indices have a common base type (i.e. Integer)

● Unsigned, Signed < => Std_Logic_Vector


A_slv
A_slv <=
<= std_logic_vector(
std_logic_vector( B_uv
B_uv )) ;;
C_slv
C_slv <=
<= std_logic_vector(
std_logic_vector( D_sv
D_sv )) ;;
G_uv <= unsigned( H_slv ) ;
J_sv <= signed( K_slv ) ;

● Motivation, Unsigned - Unsigned = Signed?


signal
signal X_uv,
X_uv, Y_uv
Y_uv :: unsigned
unsigned (6
(6 downto
downto 0)
0) ;;
signal
signal Z_sv
Z_sv :: signed
signed (7
(7 downto
downto 0)
0) ;;
.. .. ..
Z_sv
Z_sv <=<= signed('0'
signed('0' && X_uv)
X_uv) -- signed('0'
signed('0' && Y_uv)
Y_uv) ;;

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SynthWorks
Numeric_Std Conversions:
Unsigned, Signed <=> Integer
● Converting to and from integer requires a conversion function.
● Unsigned, Signed => Integer

Unsigned_int
Unsigned_int <=
<= TO_INTEGER
TO_INTEGER (( A_uv
A_uv )) ;;
Signed_int
Signed_int <=
<= TO_INTEGER
TO_INTEGER (( B_sv
B_sv )) ;;

● Integer => Unsigned, Signed


Array
Array
C_uv
C_uv <=
<= TO_UNSIGNED
TO_UNSIGNED (( Unsigned_int,
Unsigned_int, 88 )) ;; width
width == 88
D_sv
D_sv <=
<= TO_SIGNED
TO_SIGNED ( Signed_int, 88 )) ;;
( Signed_int,

● Motivation (indexing an array of an array):


Data_slv
Data_slv <=
<= ROM(
ROM( TO_INTEGER(
TO_INTEGER( Addr_uv)
Addr_uv) )) ;;

signal
signal A_uv,
A_uv, C_uv
C_uv :: unsigned
unsigned (7
(7 downto
downto 0)
0) ;;
signal
signal Unsigned_int
Unsigned_int :: integer
integer range
range 00 to
to 255
255 ;;
signal
signal B_sv,
B_sv, D_sv
D_sv :: signed(
signed( 77 downto
downto 0)
0) ;;
signal
signal Signed_int
Signed_int :: integer
integer range
range -128
-128 to
to 127;
127;

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SynthWorks
Std_Logic_Arith Conversions:
Unsigned, Signed <=> Integer
● Converting to and from integer requires a conversion function.
● Unsigned, Signed => Integer

Unsigned_int
Unsigned_int <=
<= Conv_INTEGER
Conv_INTEGER (( A_uv
A_uv )) ;;
Signed_int
Signed_int <=
<= Conv_INTEGER
Conv_INTEGER (( B_sv
B_sv )) ;;

● Integer => Unsigned, Signed


Array
Array
C_uv
C_uv <=
<= Conv_UNSIGNED
Conv_UNSIGNED (( Unsigned_int,
Unsigned_int, 88 )) ;; width
width == 88
D_sv
D_sv <=
<= Conv_SIGNED ( Signed_int, 88 )) ;;
Conv_SIGNED ( Signed_int,

● Motivation (indexing an array of an array):


Data_slv
Data_slv <=
<= ROM(
ROM( Conv_INTEGER(
Conv_INTEGER( Addr_uv)
Addr_uv) )) ;;

signal
signal A_uv,
A_uv, C_uv
C_uv :: unsigned
unsigned (7
(7 downto
downto 0)
0) ;;
signal
signal Unsigned_int
Unsigned_int :: integer
integer range
range 00 to
to 255
255 ;;
signal
signal B_sv,
B_sv, D_sv
D_sv :: signed(
signed( 77 downto
downto 0)
0) ;;
signal
signal Signed_int
Signed_int :: integer
integer range
range -128
-128 to
to 127;
127;

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SynthWorks
Std_Logic_Vector <=> Integer
● Converting between std_logic_vector and integer is a two step process:

● Numeric_Std: Std_Logic_Vector => Integer


Unsigned_int
Unsigned_int <=
<= to_integer(
to_integer( unsigned(
unsigned( A_slv
A_slv ));
));
Signed_int
Signed_int <=
<= to_integer(
to_integer( signed(
signed( B_slv
B_slv ));
));

● Numeric_Std: Integer => Std_Logic_Vector


C_slv
C_slv <=
<= std_logic_vector(
std_logic_vector( to_unsigned(
to_unsigned( Unsigned_int,
Unsigned_int, 88 ));
));
D_slv
D_slv <=
<= std_logic_vector(
std_logic_vector( to_signed(
to_signed( Signed_int,
Signed_int, 88 ));
));

signal
signal A_slv,
A_slv, C_slv
C_slv :: std_logic_vector
std_logic_vector (7
(7 downto
downto 0)
0) ;;
signal
signal Unsigned_int
Unsigned_int :: integer
integer range
range 00 to
to 255
255 ;;
signal
signal B_slv,
B_slv, D_slv
D_slv :: std_logic_vector(
std_logic_vector( 77 downto
downto 0)
0) ;;
signal
signal Signed_int
Signed_int :: integer
integer range
range -128
-128 to
to 127;
127;

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SynthWorks
Ambiguous Expressions
● An expression / statement is ambiguous if more than one operator
symbol or subprogram can match its arguments.

● Std_Logic_Arith defines the following two functions:


function
function "+"
"+" (L,
(L, R:
R: SIGNED)
SIGNED) return
return SIGNED;
SIGNED;
function
function "+" (L: SIGNED; R: UNSIGNED) return
"+" (L: SIGNED; R: UNSIGNED) return SIGNED;
SIGNED;

● The following expression is ambiguous and an error:


Z_sv
Z_sv <=
<= A_sv
A_sv ++ "1010"
"1010" ;; Is
Is "1010"
"1010" Signed
Signed or
or Unsigned
Unsigned
"1010" = -6 or 10

● Issues typically only arise when using literals.

● How do we solve this problem?

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SynthWorks
Std_Logic_Arith:
Ambiguous Expressions
● VHDL type qualifier (type_name') is a mechanism that specifies the type
of an operand or return value of a subprogram (or operator).
Z_sv
Z_sv <=
<= A_sv
A_sv ++ signed'("1010")
signed'("1010") ;; Effects
Effects all
all numeric
numeric
operators
operators inin
● Leaving out the ' is an error: std_logic_arith
std_logic_arith
--
-- Z_sv
Z_sv <=
<= A_sv
A_sv ++ signed("1010")
signed("1010") ;;

● Without ', it is type casting. Use type casting for:


Z_sv
Z_sv <=
<= A_sv
A_sv ++ signed(B_slv)
signed(B_slv) ;;

● Recommended solution, use integer:


Z_sv
Z_sv <=
<= A_sv
A_sv -- 66 ;;

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SynthWorks
Addition Operators
Addition Operators: + -

● Arrays with Arrays:


Add_uv
Add_uv <=
<= A_uv
A_uv ++ B_uv
B_uv ;; •• Size
Size of
of result
result ==
Sub_uv
Sub_uv <=
<= C_uv
C_uv -- D_uv
D_uv ;; •• Size
Size of
of largest
largest array
array operand
operand
•• Size
Size of Add = maximum(A, B)
of Add = maximum(A, B)
•• Shorter
Shorter array
array gets
gets extended.
extended.

● Arrays with Integers:


Inc_uv
Inc_uv <=
<= Base_uv
Base_uv ++ 11 ;; •• Caution:
Caution: Integers
Integers must
must fit
fit into
into an
an
Y_uv
Y_uv <=
<= A_uv
A_uv ++ 45
45 ;; array the same size as the result.
array the same size as the result.
•• Extra
Extra MSB
MSB digits
digits are
are lost
lost
•• A
A must
must be
be at
at least
least 66 bits
bits

By convention the left most bit is the MSB

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SynthWorks
Use Integers with Care
● Synthesis tools create a 32-bit wide resources for unconstrained integers
signal
signal Y_int,
Y_int, A_int,
A_int, B_int
B_int :: integer
integer ;;
.. .. ..
Y_int
Y_int <=<= A_int
A_int ++ B_int
B_int ;;

● Do not use unconstrained integers for synthesis

● Specify a range with integers:


signal
signal A_int,
A_int, B_int:
B_int: integer
integer range
range -8
-8 to
to 7;
7;
signal
signal Y_int
Y_int :: integer
integer range
range -16
-16 to
to 15
15 ;;
.. .. ..
Y_int
Y_int <=<= A_int
A_int ++ B_int
B_int ;;

● Recommendation: Use integers only as constants or literals


Y_uv
Y_uv <=
<= A_uv
A_uv ++ 17
17 ;;

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SynthWorks
Comparison Operators
Comparison Operators: = /= > >= < <=

● Comparison operators return type boolean

● Std_Logic is our basic type for design.


● How do we convert from boolean to std_logic?

● Arrays with Arrays:


AGeB
AGeB <=
<= '1'
'1' when
when (A_uv
(A_uv >=
>= B_uv)
B_uv) else
else '0';
'0';
AEq15
AEq15 <= '1' when (A_uv = "1111" ) else '0';
<= '1' when (A_uv = "1111" ) else '0';

● Arrays with Integers (special part of arithmetic packages):


DEq15
DEq15 <=
<= '1'
'1' when
when (D_uv
(D_uv == 15
15 )) else
else '0';
'0';

Result
Result == Boolean
Boolean Input
Input arrays
arrays are
are extended
extended to
to be
be the
the same
same length
length

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SynthWorks
Multiplication and Division
Multiplication Operators: * / mod rem

● Array Multiplication
signal
signal A_uv,
A_uv, B_uv
B_uv :: unsigned(
unsigned( 77 downto
downto 0) 0) ;;
signal
signal Z_uv
Z_uv :: unsigned(15
unsigned(15 downto
downto 0) 0) ;;
.. .. ..
Z_uv
Z_uv <=<= A_uv
A_uv ** B_uv;
B_uv; •• Size
Size of
of result
result ==
•• Sum
Sum ofof the
the two
two input
input arrays
arrays

● Array with Integer (only numeric_std)


Z_uv
Z_uv <=
<= A_uv
A_uv ** 22 ;; •• Size
Size of of result
result ==
•• 22 ** size
size of
of array
array input
input

Note:
Note: "/
"/ mod
mod rem"
rem" not
not well
well supported
supported by
by synthesis
synthesis tools.
tools.

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SynthWorks
Adder with Carry Out

Unsigned Algorithm: Unsigned Code:

'0',
'0', A(3:0)
A(3:0) Y5
Y5 <=
<=
++ '0',
'0', B(3:0)
B(3:0) ('0'
('0' && A)
A) ++ ('0'
('0' && B);
B);
-------------------
-------------------
CarryOut,
CarryOut, Result(3:0)
Result(3:0) YY <=
<= Y5(3
Y5(3 downto
downto 0)
0) ;;
Co
Co <=
<= Y5(4)
Y5(4) ;;

signal
signal A,
A, B,
B, YY :: unsigned(3
unsigned(3 downto
downto 0);
0);
signal
signal Y5
Y5 :: unsigned(4
unsigned(4 downto
downto 0)
0) ;;
signal
signal Co
Co : std_logic
: std_logic ;;

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SynthWorks
Adder with Carry In
signal
signal A,
A, B,
B, YY :: unsigned(3
unsigned(3 downto
downto 0);
0);
signal
signal Y5
Y5 :: unsigned(4
unsigned(4 downto
downto 0)
0) ;;
signal
signal CarryIn
CarryIn :: std_logic
std_logic ;;

Desired Result: Algorithm


A(3:0)
A(3:0) ++ B(3:0)
B(3:0) ++ CarryIn
CarryIn A(3:0),
A(3:0), '1'
'1'
++ B(3:0),
B(3:0), CarryIn
CarryIn
-------------------
-------------------
Result(4:1),
Result(4:1), Unused
Unused

Example: Carry = 0 Carry = 1


0010,
0010, 11 0010,
0010, 11
0001,
0001, 00 0001,
0001, 11
--------
-------- --------
--------
0011,
0011, 11 0100,
0100, 00
Result
Result

Code:
Y5
Y5 <=
<= (A
(A && '1')
'1') ++ (B
(B && CarryIn);
CarryIn);
YY <=
<= Y5(4
Y5(4 downto
downto 1)
1) ;;
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SynthWorks
ALU Functions
● ALU1: ● Three implementations

OpSel Function ● Tool Driven Resource Sharing


00 A+B ● Code Driven Resource Sharing
01 C+D ● Defeating Resource Sharing
10 E+F
11 G+H

● Since OpSel can select only one


addition at a time, the operators
are mutually exclusive.

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SynthWorks
Possible Solutions to ALU 1
As Specified: Optimal results:
A A i0
C i1
B i2 o
E
C G i3
i0 sel
D i1
O Z OpSel Z
E i2
i3
F sel B i0
G D i1
F i2 o
H OpSel i3
H
sel

OpSel

● This transformation of operators is called Resource Sharing

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SynthWorks
ALU 1: Tool Driven
ToolDrvnProc
ToolDrvnProc :: process
process (OpSel,A,B,C,D,E,F,G,H)
(OpSel,A,B,C,D,E,F,G,H)
begin
begin
case
case OpSel
OpSel is
is
when
when "00"
"00" =>
=> ZZ <=
<= AA ++ BB ;;
when
when "01"
"01" =>
=> ZZ <=
<= CC ++ DD ;;
when "10"
when "10" =>=> ZZ <= EE ++ FF ;;
<=
when
when "11"
"11" =>
=> ZZ <=
<= GG ++ HH ;;
when others
when others =>=> ZZ <= (others
<= (others => => 'X')
'X') ;;
end
end case
case ;;
end
end process
process ;; ---- ToolDrvnProc
ToolDrvnProc

● Important: to ensure resource sharing, operators must be coded in the


same process, and same code (case or if) structure.

● Any potential issues with this?

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SynthWorks
ALU 1: Code Driven
XX <=
<= Mux4(OpSel,
Mux4(OpSel, A,
A, C,
C, E,
E, G)
G) ;;
YY <=
<= Mux4(OpSel,
Mux4(OpSel, B,
B, D,
D, F,
F, H)
H) ;;

ZZ <=
<= XX ++ YY ;;

● Best Synthesis, use for:


● Sharing arithmetic operators

● Sharing comparison operators

● Sharing complex function calls

● Resource sharing often is not possible when using third party


arithmetic logic.

Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P29

SynthWorks
ALU 1:
Defeating Resource Sharing *
● Bad Code will defeat Resource Sharing.
BadAluProc:
BadAluProc: process
process (OpSel,
(OpSel, A,
A, B,
B, C,
C, D,
D, E,
E, F,
F, G,
G, H)
H)
begin
begin
if
if (OpSel
(OpSel == "00")
"00") then
then ZZ <=
<= AA ++ B;
B; end
end if;
if;
if
if (OpSel
(OpSel == "01")
"01") then
then ZZ <=
<= CC ++ D;
D; end
end if;
if;
if (OpSel
if (OpSel == "10")
"10") then
then ZZ <=
<= EE ++ F;
F; end
end if;
if;
if
if (OpSel
(OpSel == "11")
"11") then
then ZZ <=
<= GG ++ H;
H; end
end if;
if;
end
end process
process ;;

Uses
Uses "end
"end if",
if", rather
rather than
than "elsif"
"elsif"

● * Not Recommended,
synthesis tool may create a separate resource for each adder.

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SynthWorks
Defeating Resource Sharing
● When does this happen? ● Separate statemachines and
resources
case
case StateReg
StateReg is is
when
when S1S1 =>=> Statemach
Statemach :: process(...)
process(...)
if
if (in1
(in1 == '1')
'1') then
then begin
begin
ZZ <=
<= AA ++ BB ;; --
-- generate
generate function
function
.. .. .. --
-- select
select logic
logic (OpSel)
(OpSel)
end
end ifif ;; end
end process
process ;;
when
when S2S2 =>=>
if
if (in2
(in2 == '1')
'1') then
then
ZZ <=
<= CC ++ DD ;; Resources
Resources :: process(...)
process(...)
.. .. .. begin
begin
end
end ifif ;; --
-- code:
code:
.. .. .. --
-- arithmetic operators
arithmetic operators
when
when SnSn =>=> --
-- comparison
comparison operators
operators
.. .. .. end
end process
process ;;
when
when others
others => =>

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SynthWorks
More Information
There is work in progress to extend VHDL's math capability.
For more information see the following IEEE working groups
websites:

Group Website
IEEE 1164 http://www.eda.org/vhdl-std-logic
IEEE 1076.3/numeric std http://www.eda.org/vhdlsynth
IEEE 1076.3/floating point http://www.eda.org/fphdl

Also see the DVCon 2003 paper, "Enhancements to VHDL's


Packages" which is available at:
http://www.synthworks.com/papers

Lewis Copyright © 2003 SynthWorks Design Inc. All Rights Reserved. MAPLD 2003 P32
SynthWorks
Author Biography
Jim Lewis, Director of Training, SynthWorks Design Inc.

Jim Lewis, the founder of SynthWorks, has seventeen years of


design, teaching, and problem solving experience. In addition
to working as a Principal Trainer for SynthWorks, Mr. Lewis
does ASIC and FPGA design, custom model development,
and consulting. Mr. Lewis is an active member of IEEE
Standards groups including, VHDL (IEEE 1076), RTL
Synthesis (IEEE 1076.6), Std_Logic (IEEE 1164), and
Numeric_Std (IEEE 1076.3). Mr. Lewis can be reached at
jim@SynthWorks.com, (503) 590-4787, or
http://www.SynthWorks.com

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SynthWorks
SynthWorks VHDL Training
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http://www.synthworks.com/comprehensive_vhdl_introduction.htm
A design and verification engineers introduction to VHDL syntax,
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Our designer focus ensures that your engineers will be productive
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For additional courses see: http://www.synthworks.com

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