‘t 27 825318254 Programmable Interval Timer

n
Every programmer is sometimes confronted with the problem of implementing certain delays
into a prcgram, for example to move a point slowly on-screen. Often, wdummyn loops of the
e
following form are employed:
t.
5,
But such delay loops have a significant disadvantage: they rely on the processor speed. The
,I
delay time can therefore be very different on a 50 MHz i486 and on the ancestor 4.77 MHz 8083
!,
: (namely by a factor of 100). Old computer games in particular make use of such loops, and the
result is well known: while it is possible to xflys on a FC with a 4.77 MHz 8088 with a flight
sbnulator with no problems, the plane has crashed on a 50 MHz i486 before the pilot can operate
a single key.
But the problem of generating exactly defined time intervals also occurs in the system itself.
DOS, for example, provides the time and date for every file, and the control of electric motors
in floppy drives requires exactly defined signals. In bath cakes, time intervals defined by means
of program loops are not suitable. Thus, the PC’s designers have implemented one (PC/XT and
’ most ATs) or sometimes two (some new ATs or EISA) pmgmmmable interval timers (PITS).

27.1 Structure and Functioning of the PIT 825318254

The PIT generates programmable time intervals from an external clock signal of a crystal osci-
i Iator that are defined independently from the CPU. The 8253/8254 is a very flexible PIT and has
: six operation modes in all. Figure 27.1 shows a block diagram of the 8253/8254’s internal
i structure.
i The 8253/8254 comprises three independently and separately pmgrammable counters O-2, each
r of which is 16 bits wide. Every counter is supplied with its own clock signal (CLKO-CLK2),
which serves as the time base for each counter. In the_originaI PC a 14 317 180 Hz crystal
’ provided the base clock which was divided by three to generate the 4.77 MHz clock signal for
’ the processor. Further d&ding by four leads to a signal with about 1.193 180 MHz, which is
z applied to the three inputs CLKO-CLK2 of the 8253/8254 as the dock signal. In the PC, each of
r the three independent counters therefore runs with the same time base of 0.838 )IS. Also today’s
T PCs with processor clock frequencies between 4.77 MHz and 66 MHz have an oscillator that
“’ provides this 1.193 18 MHz for the FlT(s).
CT o enable or trigger (see the section about 82X+/8254 counting modes) a counter a gate signal
;~’ GATEO-GATE2 is applied. Depending upon the counting mode, the counter concerned is
p Wtivated by a transition low-high or a high level of the GATEx signal. Via the correqwnding
oUtpu$ OUTO-OUT2 the counter outputs a signal. Also, the shape of the output signals depends
;,‘“‘,thecountefs mode.
i The data bus buffer together with the control/write logic reads and writes data from and to the
plT The control register loads the counters and controls the various operation modes. Certain
hme mtervals and signal shapes at outputs OUT&OUT2 can thus be set. The counters may be
I_
681
682 Chapter 27 82I

.
1
_
.
8253/8254 Programmable Interval Timer 683 .

count registers CR, CQ. The 8254 additionally implements a status latch by means of which
(and the read-back command) the 8254 outputs status information. When the CPU writes count
values, the passed bytes are tmnsferred into the count registers CR, and CR, first. Afterwards,
the control logic transfers the two bytes simultaneously into the E-bit counting element.

27.2 825318254 Terminals and Signals

8253 and 8254 coincide in their pin assignments and the meaning of the applied and output
signals. The only difference between them is that the 8254 implements an additional command
for reading the prczgramred status (read-back command). Pigwe 27.3 shows the pin assignment
far the 8253/8254.

, AO, Al (I)
Pins 19, 20

<The signals at these address pins indicate the number of the counter or the control register that
the CPU accesses for data reading or writing. A0 and Al are usually connected to the address
bus of the system. The possible combinations of (Al, AO) have the following meanings:

r FLKO, CLKl, CLK2 (1, ,, 1)

i+l.9 9, 15, 18
;
bfieSe pins are supplied with the clock signals for the counters 0, 1 and 2, resp&tively.
j/
 684 Chapter 27

cs (I)
Pin 21

If this chip select Pin is on a low level, the CPU can read data from or write data to the internal
8233/8254 registers via the data bus D7-DO using the E and m signals. Thus the E signal
enables the PIT for read and write processes. For the counting operation and the signals sup-
plied by the PIT, a has no meaning.

D7-DO (I/O)
Pins 1-8

These eight connwtions form the bidirectional data bus tbmugh which the 8253/8254 receives
and pmvides data and instructions from or to the’CPU.

GATEO, GATEl, GATE2 (1, I, I)

Pins 11, 14, 16

These pins are supplied with the gate signals for the counters 0, 1 and 2, respetively, to enable
the cwunters.

OUTO, ou-rl, OUT2 (0.0, 0)

Pins 10, 13, I7

These connections supply the output signals of the counters 0, 1 and 2, respectively

wii (1)
Pill23

If the signal at this write pin is at a low level, the CPU writes data into the internal 8253/82%
registers via the data bus D7-W.

m (I)
Pin 22

If the signal at this read pin is at a low level, the CPU can read data from the internal 82531
8254 registers via the data bus D7-DO

,. VCC
Pin 24

l
. ‘*The
. supply voltage (usually +5 V) is applied to this pin.

GND
Pin 12

The ground potential (usually 0 Vl is applied to this pin.

 i
27 !53/8254 Programmable Interval Timer 685 .

7.3 Programming the 825318254

JU may program the 8253/8254 PIT by first writing one control word via port @43h into the
ntrol register, and then one or two data bytes via the port of the intended counter. If the
~ntml register is loaded once, the counters may be overwritten with other values without
,cessing the control register again. Counting mode and format remain the same. Table 27.1 lists
e port addresses of the various registers.

me 8253 control register is write-only; no data can be read. For the 8254 a new comma,,d is
uilable, the read-back command, with which certain control information can be determined.
vgramming one of the three 8253/8254 counters is begun by writing a control word via port
:3h (1st PITI or 04bh (2nd PIT). Figure 27.4 shows the control word format.
 686 Chapter 27

27.4 Writing Count Values

To start a canter or load it with new values, you must first output a control word in which you
detine the intended counter, number and type of the byte to write, the counting mode of the
counter cvncemed, and the counting format.
The SC bits determine the taunter to which the following entries refer. The combination SC = Ilb
is invalid on the 8253. On the 8254 this issues a read-back command for reading the control
register (see below). With RW bits you indicate which (low-order or high-order) and how many
counter bytes you are going to write. If you specify that only the low-order 01 high-&r byte
is to be written, then you can also only read the low-order or high-order counter byte in a later
read a-. But the 8253/8254 is, nevertheless, operating as a l&bit counter internally, that is,
a high-order counter byte 10 doesn’t mean a count value of 10 but 256.10 = 2560. The counter
latch command is important only for reading a counter. With the three mode bits you define the
counting mode of the counter selected via SC (details concerning the counting modes are given
in the next section). Finally, the BCD bit determines the counting format. With a set BCD bit the
counter operates with binary ceded decimals, thus ti& range of values from 0 to 9999 is avail-
able. lf BCD is equal to 0 then the counter performs a binary operation with 16 bits, and
the counting range is 0 (Oh) to 65 535 (ffffh). According to RW bits you need to write either the
low-xder, the high-order, or both into the counter after passing the control word. With the
combination RW = Olb (write low-order byte only) you provide the low-order byte via the pat
of the corresponding wunter.
According to the control word, the contml logic wognizes that only the low-order byte will be
passed and sets the high-order byte in CR, automatically to 0. The same applies to the combination
RW = lob (write high-order byte only). In this case, the control logic sets the low-order byte in
CR. automatically to 0. If RW = Ilb, then you first need to write the low-onier byte and then the
high-order byte by means of two OUT instructions. The control logic transfers the byte received
tist into the Cq register and that received second into the CR, register. For small counting
values or counting values that are a multiple of 256, it is therefore sufficient to pass the low-
order or high-order counter byte. You can then save-one OUT instruction. This is important if
you are generating ROM code, as here the available storage capacity is usually rather limited.

w al, 119 I Icad. la-oraer bYt* ot Co”x.Ci”. value fax. accumaaror

* Ilh, .1 . / “rire Eou”fira value lnro 2nd PIT
?he maximum loadable count value is not ffffh (binary counting) or 999 (BCD counting), but 0.
Upon the next CLK pulse the counter concerned jumps to ffffh or 9999, respectively, without
resulting in any action. Once the value is decreased to 0 again, it outputs a signal according to
the programmed mode at the OUTx pin. Thus the value 0 corresponds to 2” for binary counting
and I@ for counting with BCDs
 825318254 Proqrammable Interval Timer 687

27.5 Reading Count Values

Two options for reading a counter are available on the 8253, and three on the 8254:

- direct &ding by means of one or two IN instructions;

- counter latch command;
- read-back command (82% only).

When reading a counter you should not use the first option but transfer the current state of the
counting element (CE) into the output latches Ol, and OL, and latch there using the counter
latch or read-back command. Latch OL then holds the high-order byte, and latch Ol. the low-
order byte of the counting element. One or two successive. IN instructions for the port address
of the counter conceme.i then read these latches. If only the loworder (RW = Olb) or high-order
byte (RW = lob) was written when the counter was loaded with the initial counting value, then
read the current counting value of the initially written byte by a single IN inshuction. A suc-
ceeding IN instruction fetches the non-latched value of the low-order or high-order counter byte
at the time of the IN instruction and not the correspondixq semnd byte of the &bit counting
element. This is only possible if you have previously written the low-order as well as the high-
order counter byte. In this case you need to read the current counter value by means of two IN
inst~ctions. The PIT returns the Low-order byte of the %-bit counter with the first IN instnx-
tion, and then the high-order byte with the second IN instruction.
The processor doesn’t access the counting element (CE) directly, only the output latches. If the ,
cmtent of CE has been transferred once by a counter latch command into the output latches, ’
j! then this value is held there until the PU executes one or two IN instrwtions, or until the *
i corresponding wunter is repmgrammed. Successive counter latch commands are ignored if the
’ output latches haven’t been read before. The counting element, however, also continues to aunt
:_ after a counter latch command; the counter latch makes only a *snapshot* of the counting .
element CE. If you read the counter in the mode RW = CQb directly without the counter latch
!, command by means of two IN inshuctions, then the munter value may have changed already
when you issue the second IN instruction. Thus the high-&x byte of the counting element CE
t read second doesn’t fit the low-order byte read first. The determined values do not coincide
p with the actual values. A;an intermpt or a memory refresh may occur between two successive
1 IN instmctions, for example, the period between the execution of two IN instructions is not
predictable. Therefore, you should always issue a counter latch command or determine the
munter value by means of a read-back command. Figure 27.5 shows the format of the control
word for the counter latch command.
 .
688 Chapter 27

To determine the current counter value you have to output a counter latch command for the
counter to read via ports 043h or 04bh. According to the programmed mode, you issue one or
two IN instructions for the counter concerned afterwards. But ensure that in all cases the coun-
ter has been pmgrmuned with one or two bytes before. The read Shit or X-bit value then
indicates the current counter value at the time of the counter latch command in the programmed
counting mode (binary or BCD). If the thus determined 8-bit value is the high-order counter
byte, then you need to multiply it (at least in your head) by 256 to get the weal. value that the
counting element CE in the PIT uses.
Example: rmLelli.m .al”a Of cour.ar 3‘ rha cc”aarez ha. iniri.llY bur 1- *itb la-or&r
and hLlh-onl0.r byte*.
lmv .1. lOOOOOOOb I load counter hrch v tar aoullter 3 into a1
OUT 4%. .I , arrpur. cc.unt~r l.Wh copynd to ccmrm1 redstAr
In 0. 4% , read lox-0rd.r SGumr.r wt. ir.to -1
TP ah. 4Ih , rua hi@h-ord.r -t.r byt. into ah
i thus u-ah. a1 ccmrain, the NIT*nf IS-hit co”rser value
The tlrst I” insrrucrion ?.r~*ac. ma laro*r tyte ot t_b counung el-r
vx,, *hi& i. h.M by the latch CL. into til. ha.t .iymi*car.L byte a1 of. the
.C-l.t.r~ *I fhe aecocd 1” In.truction l_ the hish-oder byte heId In tb
I.kCh cz, illto thm m2.t .ior.iEcar.r ac-lator bYt. ah. Thu., ax contain. the
16-bif CnunLer value after the wo In..
Unfortunately, there is no possibility of determinin g the initial value of a counter directly. This
would be useful, for example, for investigating the refresh rate of counter 1. The only option
is to read the counter concerned often, and to regard the maximum read value as the initial
value. Another disadvantage is that on the 8253 the pmgmmmed counting made cannot be
determined. However, the interpretation of the read counter value is very different depending
upon whether the wunter operates with binary or BCD numbers. Further, it cannot be deter-
mined whether the munter has been loaded with a lowader and a high-order byte or only
with one of them. This is necessary, though, to determine the counting rate of a PIT that is
programmed in an unknown way. Without knowing the counting mode you can only spxulate
when interpreting the read values.
The newer PIT model, the 82.54 (used first with the AT), implements the possibility of also
reading the counMs mode by means of a read-back command as a significant advance. Addi-
tionally, with the read-back command you can determine the current counter value. You issue
the read-back command via the control register (ports 43h or 04bh). Figure 27.6 shows the
format of this new 8254 command.
I_ The two nwst significant bits define the read-back command with their value Ilb (compare with
Figure 27.4). m indicates that the value and 3 that the counting mode of a counter is to be
determined. Note that m and $? are complementary signals, which issue the intended action
. if you set the bit concerned to 0, and not I as usual. The bits C&C2 define the counter whose
S <a& or mode is to be determined.

With the read-back command you can issue several counter latch commands in parallel by indicat-
ing several counters simultaneously with the bits CO-CZ. The 8254 then behaves as if you had
issued several counter latch commands (Figure 27.5) individually, andtransfers the individual
8253i8254 Programmable Interval Timer 689

..
is also possible to determine the value as well as the mode of a counter by meam of the mad-
ck command. If you only want to determine the value of a counter then set TT = 0 and 57 = I.
this case the read-back command is equivalent to one (if you set only one single G = I; x = 0,
2) or more counter latch commands (if you set several Cx= 1). For the number and interpre
ion of the IN instructions the same applies as for a normal counter latch m-ild.
however, you want to determine the programmed mode of a certain counter, then set 3 = o
d m = 1. Also, in this case, it is possible to select several countem simultaneously. YOU o”ly
ed to set several Cx to 1. The read-back command latches the current mode and supplis a
tus byte at the port address of the counter(s) concerned. You can fetch this status byte with
IN inst~ction. If you issue a new read-back command to de&e the mode without
ving read out the counter concerned in advance, then this second command is ignored. The
ches further contain the mode at the time of issuing the first command. Figure 27.7 shows the
tus byte format.

!e pin bit indicates the current status of the concerned counter’s OuTx pin. if pin = 1 then the
unter provides a high-level signal (+5 V), otherwise it supplies a low-level signal (0 V). The bit
D shows whether the last written counter value has already been transferred to the counting
 690 Chapter 27

element CE by latches CR. and CR* Depending upon the programmed counting mode, this may
last some time. Not before zero = 0 is it meaningful to read back the wunter value. Before this
the PIT returns a value that further reflects the old state. The remaining six bits RW, mode and
BCD return the values with which they have been loaded for the counter concerned during the
last write of the control register (Figure 27.4). Thus you can determine, for example, whether
you need to read the low-order or high-order byte with a single IN instruction only, or whether
you must issue two IN instructions to get the current value of a counter.
Example: mrarmina aSr.Linp tic of cmlr&** 0.
Mov al, 1T100010b i load as-laror ritb reaa-hlck ma ior med.; E-1. Es0
OUT 43h. a1 / arrpur read-tack - to control reL.i*ter
IN al, (Oh , gef mc.a *ia sort Of counter 0
It is assumed that the status byte in the accumulator al has the value 00110100b. Thus the OUT
pin is on a 0 V level, the counter has been already loaded with the latest passed value, the low-
order and high-order bytes are used, the axmting mode is equal to 2, and the counting proceeds
in a binary fashion with 16 bits. This mode is used, for example, to issue the interrupt 08h that
updates the internal system clock.
In the read-back command you may also combine the detem?ination of counter mode and value.
set m as well as 3 to 0 in this case. All counters specified by means of C&C2 then return
information concerning the counting mode and the current count value. With the first IN in-
struction referring to a selwted counter you get the status byte; with the second or second and
third IN instructions, the PIT returns the low-order and/or high-order byte of the currently
latched counter value. All further IN instructions pass non-latched counter values as they are
taken from the counting element (CEl but no more status bytes. Ensure that all counters selwted
with bits C&C2 are read completely by means of two or three IN b&nxtions; otherwise.
further counter latch or read-back commands may be ignored.
If you output a counter latch command and later a &d-back command to determine the count-
ing mode without having read the counter value before, then the PIT first supplia the statuS
byte with the first IF instructions and only afterwards the byte(s) that indicate the county
value. Thus the order of passing latched bytes is always the sane. If you have read the counting
value in advance of the read-back command, then the IN instruction after the read-back corn-
mand of course returns the latched status byte.

27.6 825318254 Counting Modes

The 8253/8254 recognizes six different counting modes in all. Further, the PIT can count in
* b&q or in bin&y coded decimals. Figure 27.8 shows the signals that are supplied by the OlJTx
conn&ion in each mode, as well as the meaning of the trigger signals at the GATEx input.
In the following the various operation modes are briefly explained. In all modes the PIT x%unts
from initial count values down to lower values. If you newly write the control register, then the
control logic is immediately reset and the output OUT of the counter’concemed is reset to a
defined initial state.
 8253/8254 Programmable Interval Timer 691

You may write new counting values into one of the counters at any time, but you have to
observe the last programmed mode Oow-order and/or high-order counter byte, etc.). The new
values, however, become effective at different times in the various modes. If a counter has
reached the value 0, then it does not stop to count in the non-periodical modes 0, I, 4 and 5,
i
but continue with ffft% @CD = 0) or 9999 @CD = Il. The OUT pin, however, is not reset, and
the counting operation only orm~s internally without any external consequences.
In some modes the GATE signal executes the counting operation: if GATE = 1 then the 8253/
8254 continws countin& otherwise it keeps the currentValue without any change. In other
modes a low-high transition or a high level at the GATE input starts the counting opeation; the
GATE pulse acts as a trigger. Even if GATE then returns to a low level, the counter continues
to work. The entity N in the following description names the initial counter value.

Mode 0 (Interrupt on Terminal Count)

After the control register and the initial count value have been written, the counter is loaded
Upon the next CLK pulse. The OUT pin is on a low level (0 V) at the start of counting. If the
Countq reaches the value 0, then OUT risff and remains on a high level (+5 Vl until a new count
MIue_W a new control word for mode 0 is written. If GATE = 1 the counter concerned counts
..-._

a new count value is written into a counter it is loaded upon the next CLK pulse, and the
5 Counter continua the counting operation with the newly loaded value. Also, if GATE=0 the
$Z muter can be loaded, but the counting operation doesn’t start until GATE rises to a high
p level.
 692 Chapter 27 8

Mode 0 is mostly used to issue a hardware interrupt after the elapse of a certain time period. P
The MI uses mode 2 for the periodic timer interrupt as mode is not periodic. k
tt
Mode 1 (Programmable Monotlopl c<
”
After writing the control register and the initial count value, the output OUT is on a high level
(+S V) for the moment. A trigger (transition low-high) at the GATE input loads the counter. A
Upon the next CLK pulse, OUT drops to a low level (0 W and remains at that level until the a
counter has reached the value 0. Then OUT rises to a high level. Not until one CLK pulse after
T
the next trigger does OUT fall again to a low level. Thus, in mode 1 the PIT generates a triggered
d
one-shot pulse with a duration of N CLK cycles and a low level.
b
If another trigger pulse appears during the course of‘s count operation (that is, while OUT is at h
a low level), the PIT reloads the counter with the initial value. Thus the OUT pin is at a low level b
N CLK cycles after the last trigger pulse. Unlike mode 0, the PIT can be triggered in this mode. d
si
If you write a new count value while the PIT is o+ing in mode 1, the new value is not
i!
effective for the current process. Not until the next irigger pulse at the GATE input is the new
a
count value transferred to the counter. The trigger pulse can occur, of course, when the PlT has
not yet completed the current counting operation. The single pulse with a low level lasts in this
case until the PIT has counted the new count value down to 0.

Mode 2 (Rate Generator)

After the control word and the initial count value N have been loaded, the PIT starts counting
upon the next CLK pulse. As soon as the counter reaches the value 1, OUT drops to a low level
for one CLK cycle Thus the 8W/82% generates a short peak pulse. Afterwards, the initial
count value is autotnatically reloaded and the PIT restarts the same counting operation again;
mode 2 is therefore periodic. The distance of two OUT pulses is N CLK cycles long.
A signal GATE = l enables (and a signal GATE = 0 disables) the counter. If GATE drops to a IOW
level during the counting operation and rises to a high level later, the PIT loads the initial count
value at the rise a”$ starts counting. Thus the 82S3/82S4 can be biggered by a hardware pulse
in mode 2. On the other hand, the PIT starts immediately after writing the last data byte. With
an active GATE the PIT can therefore also be triggered by software, that is, by the last write acce%
Mode 2 is used for counter 2 in the PC for the periodic timer intempt. The low-high transition
during the rise of signal CLKO issues a hardware interrupt IRQO corresponding to lNT 08h via
: the 8259A PIC. The count value must not bpequal to I.

Mode 3 (Square-wave Generator1

‘_
L ’ {Mode 3 gem&es a periodic square-wave signal with a period of N CLK cycles, Initially, OUT
is at a high level. If half of the N CLK cycles have elapsed, then OUT drops to a low level. After
the counter has reached the value 0, OUT again rises to a high level, and the initial value N is
reloaded into the counter. Mode 3 is therefore periodically like mode 2. But unlike mode 2, the
low phase of the OUT pin lasts N/2 CLK cycles, not only a single CLK cycle. If GATE = 1 the
counter is operating; if GATE = 0 it is stopped. A drop of GATE to a‘low level while the OUT
7 I 8253/82X Programmable Interval Timer 693

1. pin is also on a low level immediately raises OUT to a high level. A rise from a low to a high
level at the GATE input (bigger pulse) loads the counter with the initial count value and starts
the counting operation. Thus the PIT can be synchmnized by hardware in mode 2. After the
control nzgister and the initial count value have been written, the 8253/8254 lwds the counter
upon the next CLK pulse. Thus, the PIT can also be synchronized by software.
A new count value supplied during the course of an active counting operation doesn’t affect the
current process. At the end of the current half cycle the PIT loads the new value.
The length of the low and high states differs for odd and even values of N. As a CLK cyde
defines the smallest possible time resolution, no time periods with half the CLK cycle length can
be generated. With an odd N the OUT pin is initially at a high level. The PIT loads the value
N - 1 (that is, an even number) into the counter, and begins fo decrement this value (in steps)
by two. Once the CLK pulse after the counter has reached a value of 0, the potential at OUT
drops to a low level and the counter is reloaded with N - 1. Thfs value is decremented (again in
steps) by two. If the value of 0 is reached, then OUT rises to a high level and the whole pmcess
is repeated. Thus the signal at the OUT pin is at a high level.for (N + I)/2 CLK cycles and at
a low level for (N - 1)/2 CLK cycles, that is, the signal is low somewhat longer than it is high.
With even N values, N is loaded unaltered into the counter and dwemented in steps by two.
Jf the value 0 is reached, then OUT drops to a low level and the initial value N is reloaded
immediately. After the counter has counted downwards in steps of two, OUT r&s again to a
high level and the whole pmcw h repeated. Thus, even with N values, the phases with high
and low levels are equal in time. In both cases, the period of the squar~wave signal lasts N CLK
cycles. The initial value must be at least equal to 2.
The generated square-wave signal can be wed, for example, to transmit data via serial inter-
faces. The Pm then operatff as a baud rate generator. In the PC, counters 1 and 2 are operated
in mode 3 to drive the memory refresh and the speaker, respectively.

Mode 4 @,fhwe-trfggered Pulse)

Initially, OUT is at a high level. If the counter has reached the-u&x 0, then OUT drops to a low
level for one CLK cycle and rjses again to a high level afterwards. If GATE is at a high level the
counter is operating; if GATE = 0 it is disabled. Thus the triggering is carried out by software
as the PIT starts counting after the control register and initial count values are written. Because
the counter is loaded upon the first CLK pulse after writing and doesn’t start counting until the
next CLK cycle, OUT drops (if GATE = I) to a low level N + 1 CLK cycles after the write process.
Unlike mode 2, the PIT doesn’t operate periodically in mode 4. Only a newly written count
Value triggers the counter again.
If you write a new count value while a counting operation is active, the PIT loads the new value
Upon the’next CLK cycle and continues counting, starting with the new initial value. Thus the
8253/8ti is retriggerable in mode 4 by means of software.

’ Mode 5 (Hardware-triggered Pulse)

The pulse form at the OUT pin coincides with that in mode 4. But the trigger+ is carried out
with a low-high transition of GATE. By means of this, the PIT loads the initial count value into
694 Chapter 27

the counter upon the next CLK cycle, and the counting process starts. If the value 0 is reached,
OUT drops for a single CLK cycle to a low level, and immediately afterwards rises to a high
level again. Thus, OUT drops to a low level N + 1 CLK cycles after a trigger pulse at the GATE
input. If a trigger pulse occurs during a counting operation, the PIT reloads the initial value into
the counter and continues counting with the initial value. Thus in mode 5 the 8283/82!% can be
triggemd by hardware.
If you write a new count value during the course of an active counting operation then this OP”
ation is not affwted. Only after the next trigger pulse does the PIT load the new initial value.
In the following sections the application of the various counten in the PC are discussed.

27.7 System Clock

DOS and other operating systems use a system clock for the internal management of date and
time. Using this system, the clock date and the lime df the last change of directories and files
are determined, alarms are issued at a certain time, etc. Besides this system clock, most PCs also
have a x-called real-time clock. Unlike the PITS and the connected system clock, the real-time
clock runs even if the computer is switched off. The PC queries the clock during the boot
process, so you no longer need to input the date and lime at power-up. Details on the real-time
clock and the allocated CMOS RAM are discussed in Section 29.4.
All progmmming languages available for the PC implement functions to read this internal
system clock. The instructions are, for example, TIMER in BASIC, _dosgetthne in C, or the
direct call of lNT Zlh, function Zch. This system clock is realized by counter 0 of the first (or
only) 8253/8254 PlT, the 8259A PIC and the handler rcutinff for the interrupts 08h and Ich.
Pigwe 27.9 shows a scheme for this.

Main Memory
-

The output OUT0 of counter 0 in the 825318254 PIT is connected to the‘lnput FRO (correspond-
ing to IRQOl of the first (or only) 8259A PIG. The counter 0 operates in mode 2 (rate generator)
void di..hYfir,roid,
t#tNcf aostiret tima,
ior ,i,)S
_do._g.ttir WYi~~‘ /war Lima *,
,. d*mplay Lil in the fO_f hourl linur., sacad* lwrh sr0r.d .,
_~*rbxtsa.*C*.m (1, 1,. prinrt~‘%i:\f:U:.i .,
rim.hour, LiEe.minute. Cba.*ecd, tiu.h~cond,‘
it c&hit,)> , ,* retvIm on keyboard hit *,
r.teh, ) i
re”r.3,

,
,
,

seer mu outme Of conwc.~ word OOllOlODb r*a pare ox,3 t.2 the cDnr?cd rwi.t.r i. rat
*.ol”r*ly n.c..sary *s the a*ad d. rued nor be altare& it is s.J**cient to mw.QlY as
hml-or&r d hi*bora.r eou?Aeer bytes via port 0x40.

Instead of mode 2, the PIT counter 0 may also be operated in mode 3, because in this case the
transition from low to high of the square-wave &al also issues a hardware interrupt via
the 8259A PIC. In this case, the control word WllOIMlb has to be changed to 001101lOb. As the
other 8253/8254 mcx& 0, I, 4 and 5 are not periodic, the internal clock stops if you operate
the PIT in one of these modes. Try it if you like. Later, after a boot process by means of Ctrl-
Ah-Del, the BIOS sets up the original mode again.

27.8 Memory Refresh

Besides the periodic activation of the hardware interrupt IRQO, the PIT is also used in the PC
for refreshing dynamic main memcny regularly. For this purpose, lT designers have reserved
counter I, which instructs all I8 CLK cycles on a DMA chip to carry out a dummy read cycle.
In the course of this dummy cycle, data is read from memory onto the data bus and the address
buffers, and address decoders and sense amplifiers in the memory chips are activated to refresh
one memory cell row. But the data is not taken off the data bus by a peripheral. Upon the next
bus cycle it disapp&rs. Details concerning the refreshing of dynamic memory chips (DRAMS)
are discussed in Se&on 19.1.4. Here 1 want to explain the use of counter 1 in the 8253/8254 PIT.
Figure 27.10 shows the principal connection of timer and DMA chip for memory refresh.
Counter I is operated in mode 3 (square-wave generator) with a count value of I8 (12h). Only
the low-order counter byte is loaded (RW = Olb), that is, the PIT generates a square-wave signal
with a frequency of 1.193 I8 MHz/I8 = 66 288 Hz. Thus, counter I issues a dummy read cycle
every I5 ps by means of the rising edge of the generated square-wave signal. The read cycle
.refreshes the memory. By means of the read-back and/or counter latch command, you may
&termine the-refresh rate of your IT. Usually, you should obtain the same value as indicated
above, but as the memory refreh is wry hardware-dependent, other values are also possible,
System designers usually lay out the memory refresh rather carefully, that is, the memoW I5
refrrshed more often than is really necessary. The so-called refresh owrhwd (that is, the prOpOre
tion of memory accesses which are caused by the refresh) can reach 10% and more. Modern and
27 825318254 Programmable Interval Timer

the
“ia
the
ate
WI-

PC
ied
:lt-
ess
:sh
ext
dSl
‘IT.
698 Chapter 27

/* Sef II- re*rea r*Ce *,

ours.tox43, 0X56), /*0*010110b, outpur 0r.w WB *,
0urp~ox.l. count>, ,* n*r* r%?r*a counar “al”* *,
Drinrt,.\n\luSal rawenh -*I”* %a .sr. \n\n’. count.,‘
Uit,0,i
1
The example program Listed loads only the low-order byte of counter 1. The counter values
are therefore limited to the range between 2 and 255. You are, of course, free to program
an extension with which you can also set higher initial values. For this pupae, however,
you must also use the high-order byte and load the control register with the value OlOlOllOb
instead of 0111011Ob, and then pass the low-order as, well as the high-order byte. With high-
quality chips, refresh count values of up to 1000 can be achieved without the occurrence of
parity erxlrs.

You are really free to experiment; set various refresh values and check their effects on computer
performance using benchmark programs. The effect is not very significant, but you get some
feeling for the *buttons* to turn to in a computer so that the performance is enhanced. After all,
ten times 5% is 50%! But for permanent operation you should proceed carefully. What’s the gain
of 0.1% p&omunce enhancement if your PC crashes when you are editing an important text
or pmgram? And this danger is always present while doing such experiments.

27.9 The Speaker

Counter 2 of the tirst (or only) PIT is dedicated to the tone frequency generation for the installed
speaker. You may generate various frequendes with it. How this is carried out and which points
you must observe are described in Section 29.1.

27.10 Failsafe Timer

Some newer ATs incorporate a second 8254 PIT, but only counter 0 of this PIT is used, the others
usually being free. The counter’s output OUT0 is connected to the NM1 input of the processor
via some circuitry. (See Figure 27.11 on this subject.)

A signal rise from low to high at the OUT0 pin generates a non-ma&able intermpt. This is
useful if all hardware interrupts are intentionally blocked, or because of a program error which
leads to an incorrect CL1 instruction or interrupt masking in the PICs, and the computer is
looping. Then the PC responds neither to a keyboard hit nor to another external request, except
d &dware resef - the computer hangs. Only the NM1 issued by the second PIT can *<free* the
CPU, hence the name failsafe timer. Especially for multitasking systems such as OS/2 or UNIX.
such a last resort is useful if, despite all the care taken and the use of protected mode, a program
error hangs up the computer and all other tasks are affected. While developing an operating
system this happens frrquently, and the system programmer will certainly be very thankful for
the presence of such a failsafe device.
8253/8254 Programmable Interval Timer 699

c
The NMI handler (interrupt 2) CM, of course, determine whether the source of the interrupt is
counter 0 of the second PIT or a parity error when data is read from a memory chip. In the latter . *-
case, a serious hardware malfunction has wanred. The PC mwt be shut down immediately, or
at least as quickly as possible to avoid extensive data loss or damage.