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OBJECTIVE PAPER-II
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
Key: (C) From the figure (b), we can say that, the fall
Sol: Slots=36, P=4, 3 phase, n=3. in terminal voltage is because of
1. Armature Resistance Ra
sin mn 2. Field Current.
2 no.of slots per pole
Kd m If ‘Ra’ increases, then Vt= (Eg–IaRa) falls.
msin n Phase
2 If field current (If) Reduces, then flux
36 reduces and “Eg’ reduces finally results in
sin 3 3 20
2 4 3 reduction in Vt . Vt E g I f .
3sin 3 20 3
2 Note: Inter poles are used to improve the
180 commutation and also to reduce the armature
K d 0.666 0.67 20o
36 reaction.
4
9. A dc motor develops an electromagnetic
8. Consider the following factors for a dc
torque of 150 N-m in a certain operating
machine:
condition. Form this operating condition, a
1. Interpole
10% reduction in field flux and 50% increase
2. Armature resistance
in armature current is made. What will be new
3. Reduction in field current
value of electromagnetic torque?
Which of the above factors are responsible for
(A) 225 N m (B)
decrease in terminal voltage of a shunt
202.5 N m
generator?
(A) 1 and 2 only (B) 2 and 3 only (C) 22.5 N m (D) 20.25 N m
(C) 1 and 3 only (D) 1, 2 and 3 Key: (B)
Key: (B) Sol: We know that Tem I a
Sol: Electrical Equivalent circuit of D.C. shunt Tem2 Tem1
Generator. 2 Ia 2 1Ia1
0.91 1.5Ia1 1Ia1
1.351Ia1 1Ia1
L
G O 35%
A
D As flux reduced by 10% and Ia increased by
50%, we can say that Tem will increase.
Figure a i.e., Tem, increased by 35%
35
i.e., 150 52.5 N m
Ish I L 100
The new Tem 150 52.5
R
a Ia
L
202.5 N m
R sh O
A L
V or Vt
Eg D
10. A dc machine, having a symmetrical closed-
circuit armature winding and a sinusoidal air-
Figure b gap flux-density distribution, will have a
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
35. Stability of a power system can be improved by 38. The three sequence voltages at the point of
1. Using series compensators fault in a power system are found to be equal.
2. Using parallel transmission lines The nature of the fault is
3. Reducing voltage of transmission (A) L G (B) L L L
Which of the above statements are correct? (C) L L (D) L L G
(A) 1 only (B) 2 only Key: (D)
(C) 2 and 3 only (D) 1 and 2 Sol: For double line to ground fault
Key: (D) Va0 = Va1 = Va2 = Va3
Sol: Stability of a power system can be improved by Here phase b and c are shorted to ground.
(i) higher system voltage
(ii) use of parallel lines to reduce the series 39. A distance relay with inherent directional
reactance. property is known as
(iii) Use of high speed circuit breakers and (A) Buchholtz relay
auto-reclosing breakers. (B) Admittance relay
(iv) Reducing the series reactance thereby (C) Directional over current relay
increasing Pm and therefore increases the (D) Directional switched relay
transient stability limit of a system. Key: (B)
Sol: Its characteristic (Admittance relay) passes
36. Equal-Area criterion is employed to determine
through origin of R–X diagram and hence
(A) The steady state stability
directional.
(B) The transient stability
(C) The reactive power limit 40. Consider the following circuit breakers for
(D) The rating of a circuit breaker 220 kV substations:
Key: (B) 1. Air
2. SF6
37. Consider the following advantages with respect
to HVDC transmission: 3. Vacuum
1. Long distance transmission Which of the above circuit breakers can be
2. Low cost of transmission used in an indoor substation?
3. Higher efficiency (A) 1, 2 and 3 (B) 1 only
Which of the above advantages are correct? (C) 2 only (D) 3 only
(A) 1 and 2 only (B) 1 and 3 only Key: (C)
(C) 2 and 3 only (D) 1, 2 and 3 Sol: Air break circuit breaker : This type of circuit
Key: (D) breaker is employed in both a.c. and d.c. type
Sol: Advantages of HVDC systems: of circuits upto 12 KV. These are normally
(i) Economical for long distance bulk power indoor type and installed on vertical panels.
transmission by overhead lines. Vacuum and SF6 gas circuit breakers are
(ii) Greater power per conductor and simpler suitable for primary and secondary power
line construction. distribution networks upto 40.5KV, 3150A,
(iii) No skin effect 63KA. In particular, SF6 circuit breakers do
(iv) No reactive compensation is required. not generate operating over voltages and are
(v) Higher operating voltage is possible suitable for retrofitting, upgrading. Indoor
(vi) No stability problem. circuit breakers for secondary distribution
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
average and rms values of output voltage 49. In an amplifier with a gain of 1000 without
respectively, are feedback and cut-off frequencies at 2 kHz and
10 20 20 kHz, negative feedback of 1% is
(A) V and 5V (B) V and 10V
employed. The cut-off frequencies with
20 10 feedback would be
(C) V and 5V (D) V and 10V (A) 220 Hz and 22 kHz
Key: (B) (B) 182 Hz and 220 kHz
Sol: Vi 20sin t; Vm 20V (C) 220 kHz and 220 kHz
(D) 182 Hz and 22 kHz
Vm 20
Vave V Key: (B)
Sol: Given A = 1000; fL=2 kHz; fH=20 kHz
Vm 20
Vrms 10V 0.01; f Lf ____; f Hf ____
2 2
fL 2000
f Lf 182 Hz
1 A 1 1000 0.01
47. For a BJT, IC 5 mA, IB=50 A and I CBO 0.5
3
f Hf 1 A f H 1 1000 0.01 20 10
A, then the value of is
220 kHz
(A) 99 (B) 91 (C) 79 (D) 61
Key: (A)
Sol: Given 50. Consider the following circuits:
I c 5mA; I B 50A; I CBO 0.5A; ____ 1. Oscillator
2. Emitter follower
Ic I B 1 ICBO
3. Power amplifier
5 103 50 106 1 0.5 106 Which of the above circuits employ feedback?
99 (A) 1 and 2 only (B) 2 and 3 only
(C) 1 and 3 only (D) 1, 2 and 3
48. Which of the following conditions must be Key: (A)
satisfied for a transistor to be in saturation?
1. Its collector to base junction should be 51. Three identical amplifiers each having a
under forward bias voltage gain of 50 are cascaded. The open
2. Its collector to base junction should be loop voltage gain of the combined amplifier is
under reverse bias (A) 71 dB (B) 82 dB (C) 91 dB (D) 102 dB
3. Its emitter to base junction should be Key: (D)
under reverse bias Sol: Av = Voltage gain of each amplifier = 50
4. Its emitter to base junction should be Open loop gain of the combined amplifier =
under forward bias 3
20log10 50 102dB
Which of the above conditions are true?
(A) 1 and 3 (B) 2 and 3
52. A clamper circuit
(C) 2 and 4 (D) 1 and 4
1. Adds or subtracts a dc voltage to or from
Key: (D) a waveform
Sol: For a transistor to be in saturation region its 2. Does not change the shape of the waveform
emitter-base junction and collector-base junction Which of the above statements is/are correct?
must be forward biased.
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ESE-2016 |EE| Objective Paper-II
(A) 1 only (B) 2 only 55. An operational amplifier has a slew rate of
(C) Both 1 and 2 (D) Neither 1 nor 2 2V / sec. If the peak output is 12 V, what
Key: (C) will be the power bandwidth?
(A) 36.5 kHz (B) 26.5 kHz
53. (C) 22.5 kHz (D) 12.5 kHz
o Key: (B)
o o
Sol: Given S slew rate 2 V
1 0 sec
Vpeak 12V
o o o f max power bandwidth ___
Maximum slew rate = 2 f max Vpeak
s 2 106
The operational amplifier circuit shown in f max 26.5 kHz
2Vpeak 2 12
figure having a voltage gain of unity has
(A) High input impedance and high output
56. A voltage follower is used as
impedance
1. An isolation amplifier
(B) High input impedance and low output
2. A buffer amplifier
impedance
Which of the above statements is/are correct?
(C) Low input impedance and low output
(A) 1 only (B) 2 only
impedance
(C) Both 1 and 2 (D) Neither 1 nor 2
(D) Low input impedance and high output
Key: (C)
impedance
Key: (B)
57. If a, b, c are 3-input variable, then Boolean
function y ab bc ca represents
54. Consider the following statements:
1. Race-around condition occurs in a JK flip- 1. A 3-input majority gate
flop when the inputs are 1, 1 2. A 3-input minority gate
2. A flip-flop is used to store one bit of 3. Carry output of a full adder
information 4. Product circuit for a, b, and c
3. A transparent latch consists of D-type Which of the above statements are correct?
flip-flops (A) 2 and 3 (B) 2 and 4
4. Master-slave configuration is used in a (C) 1 and 3 (D) 1 and 4
flip-flop to store two bits of information. Key: (C)
Which of the above statements are correct? Sol: In the given input combination if the majority
(A) 1, 2 and 3 only (B) 1,2 and 4 only of inputs are 1, then the Boolean (SOP)
(C) 3 and 4 only (D) 1, 2,3 and 4 function gives a majority gate
Key: (A) In the given 3-input a,b,c if atleast two inputs
Sol: Race around condition is avoided using are ‘1’ then the Boolean function
master-slave configuration .It does not store y ab bc ca represent majority gate.
two bits of information. Remaining statements Consider the truth table of full adder.
are correct.
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
70. Which one of the following statements is Sol: When microprocessor works in I/O mode then
correct regarding the instruction CMP A? data transfer takes place between accumulator
(A) Compare accumulator with register A register of micro processor and I/O device.
(B) Compare accumulator with memory
(C) Compare accumulator with register H 74. While execution of IN/OUT instruction takes
(D) This instruction does not exist place, the 8-bit address of the port is placed
Key: (A) on
Sol: CMP A → Compare the content of accumulator (A) Lower address bus
with register A. (B) Higher address bus
(C) Data bus
71. The instruction RET executes with the (D) Lower as well as higher order address bus
following series of machine cycle Key: (D)
(A) Fetch, read, write Sol: While execution of IN/OUT instruction, the
(B) Fetch, write, write 8-bit port address is placed on lower address
(C) Fetch, read, read bus as well as higher address bus.
(D) Fetch, read
Key: (C) 75. The port C of 8255 can be configured to work in
Sol: RET will execute in the order of Fetch cycle, (A) mode 0, mode 1, mode 2 and BSR
read cycle and read cycle (B) mode 0, mode 1 and mode 2
(C) mode 2 and BSR
72. Consider the following circuits: (D) BSR mode only
1. Full adder Key: (A)
2. Half adder Sol: Port C of 8255 can be configured to work in
3. JK flip-flop mode 0, mode 1, mode 2 and BSR (Bit
4. Counter set/Reset)
Which of the above circuits are classified as
sequential logic circuits? 76. Consider the following statements:
(A) 1 and 2 (B) 3 and 4 1. Semiconductor memories are organized as
(C) 2 and 3 (D) 1 and 4 linear array of memory locations
3. 8086 can address 1,048,576 addresses
73. When a peripheral is connected to the 4. Memory for an 8086 is set up as two
Microprocessor in Input Output mode, the banks to make it possible to read or write
data transfer takes place between a word with one machine cycle.
(A) Any register and I/O device Which of the above statements are correct?
(B) Memory and I/O device (A) 1, 2 and 3 only (B) 1,2 and 4 only
(C) Accumulator and I/O device
(C) 3 and 4 only (D) 1, 2,3 and 4
(D) HL register and I/O device
Key: (C)
Key: (C)
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
2 2 2 Key: (C)
0.67 67%
2m 2
2 1 3
83. An FM signal is represented by 86. The four basic elements in a PPL are loop
8
12sin(6 10 t 5sin1250 t) . The carrier filter, loop amplifier, VCO and
(A) Up converter
frequency f c and frequency deviation ,
(B) Down converter
respectively, are (C) Phase converter
(A) 191 MHz and 665 Hz (D) Frequency multiplier
(B) 95.5 MHz and 995 Hz Key: (C)
(C) 191 MHz and 995 Hz
(D) 95.5 MHz and 665 Hz 87. In a frequency modulated (FM) system, when
Key: (B) the audio frequency is 500 Hz and audio
Sol: V=12 sin (6×108 t + 5sin1250t) frequency voltage is 2.4 V, the frequency
Comparing with standard FM signal deviation is 4.8 kHz. If the audio frequency
s t A c sin w c t sin w m t voltage is now increased to 7.2 V then what is
w c 6 108 the new value of deviation?
(A) 0.6 kHz (B) 3.6 kHz
w c 2f c
(C) 12.4 kHz (D) 14.4 kHz
6 108 Key: (D)
fc 95.54 MHz
2 Sol: f m 500Hz, Am 2.4V, 4.8 kHz
5; m 1250 frequency deviation, K f .A m
1250 4.8
fm 199 Hz. Kf 103 Hz / V
2 A m 2.4
frequency division
2 103 Hz / V
messagefrequency f m
'
Now A 7.2Vm
f m 5 199 995Hz
' K f .A 'm
84. When the modulating frequency is doubled ' 2 103 7.2 14.4 kHz.
the modulation index is halved and the
modulating voltage remains constant. This 88. Modulation is used to
happens when the modulating system is 1. Separate different transmissions
(A) AM (B) PM 2. Reduce the bandwidth requirement
(C) FM (D) Delta Modulation 3. Allow the use of practicable antennas
Key: (C) 4. Ensure that intelligence may be transmitted
over long distances
85. Asin c t msin m t is the expression Which of the above statements are correct?
(A) 1, 2 and 3 only (B) 1,3 and 4 only
for
(A) Amplitude modulated signal (C) 2 and 4 only (D) 1, 2,3 and 4
(B) Frequency modulated signal Key: (B)
(C) Phase modulated signal
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ESE-2016 |EE| Objective Paper-II
(A) B 2 DW (B) B 2 D 1 W iv. Speed of rotor should be greater than
critical speed.
(C) B 2 D 1 W (D) B 2 DW
93. In an IGBT cell the collector and emitter are
Key: (B)
90. Consider the following features of FM vis-a- respectively
vis AM: (A) n and p (B) n and p
1. Better noise immunity is provided (C) p and n (D) p and n
2. Lower bandwidth is required Key: (D)
3. The transmitted power is better utilized
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ESE-2016 |EE| Objective Paper-II
Sol: Any Boolean expression (or) any logic circuit 1
T 500sec
can be realized with ‘NAND’ & ‘NOR’ gates. f
Thus the gates are called universal Gates. Vs 230V
97. If a medium transmission line is represented V0 170V
by nominal T, the value of B of ABCD
V0 D.VS
constant is
V0 170
1 D 0.7391
(A) Z (B) Y 1 YZ Vs 230
4
t on D.T 369.56sec 0.369 msec
1 1
(C) Z 1 YZ (D) 1 YZ t off T t on 130.43sec 0.131m sec
4 2
Key: (C) 100. A switched-capacitor network is/are
yz yz 1. Time variant sample data network
1 z 1
A B 2 4 2. Non linear network
Sol:
C D y yz 3. Linear time invariant network
1
4 (A) 1 only (B) 2 only
AD (C) 3 only (D) 1 and 2
CY Key: (A)
98. To turn-off a GTO what is required at the 101. A transformer may have negative voltage
gate? regulation if the load power factor (p.f.) is
(A) A high amplitude (but low energy) (A) Leading for some values of p.f.
negative current (B) Unity p.f.
(B) A low amplitude negative current (C) Lagging but not zero p.f.
(C) A high amplitude negative voltage (D) Only zero p.f. lag
(D) A low amplitude negative voltage Key: (A)
Key: (A) Sol: Voltage Regulation Graph.
Re g
99. A chopper circuit is operating on TRC control
mode at a frequency of 2 kHz on a 230 V dc Zero Re g Ve Re gulation
supply. For output voltage of 170 V, the
conduction and blocking periods of a thyristor Lead p.f lagg P.f
0 0.2 0.4 0.6 0.8 1 0.8 0.6 0.4 0.2 0
in each cycle are respectively.
(A) 0.386 ms and 0.114 ms
(B) 0.369 ms and 0.131 ms Ve Regulation
(C) 0.390 ms and 0.110 ms
(D) 0.131 ms and 0.369 ms Reg
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
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ESE-2016 |EE| Objective Paper-II
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