1. a.

Given a four variable expression, simplify using Entered Variable Map

(EVM) and realize the simplified logic using 8:1 MUX.
E.g., Simplify the function using MEV technique

f(a,b,c,d)=∑m(2,3,4,5,13,15)+dc(8,9,10,11)

Components used: IC 74 LS151, patch chords, power chords, trainer kit.

Theory
The term multiplex means “many to one”. A multiplexer (MUX) has n inputs. Each line is used to shift
digital data serially. There is a single output line.

Pin diagram of IC 74LS151

Decimal LSB f MEV map entry

0}0 0000 0 0------Do
1 0001 0
1}2 0010 1 1------D1
3 0011 1
2}4 0100 1 1-----D2
5 0101 1
3}6 0110 0 0-----D3
7 0111 0
4}8 1000 X X-----D4
9 1001 X
5}10 1010 X X-----D5
11 1011 X
6}12 1100 0 d----D6
13 1101 1
7}14 1110 0 d----D7
15 1111 1 ( Solution is given
below)
D—Map Entered Variable

ABC
D

000 001 010 011 100 101 110 111

0000 0010 0100 0110 1000 1010 1100 1110
0
0 1 1 0 X X 0 0

0001 0011 0101 0111 1001 1011 1101 1111

1
0 1 1 0 X X 1 1

D0=0 D1=1 D2=1 D3=0 D4=X D5=X D6=d D7=d

Circuit Diagram

0 04 D0 Vcc 16

03 D1 GND 8
1
02 D2

01 D3

15 D4
O/p
14 D5 Y5

` 13 D6

D
12 D7

9 10 11
7 STROBE S2 S1 S0
Low

A B C
Procedure:
1. Verify all components & patch chords whether they are in good condition or not.
2. Make connections as shown in the circuit diagram.
3. Give supply to the trainer kit.
4. Provide input data to circuit via switches.
5. Verify truth table sequence & observe outputs.
2. a. Realize a full adder using 3-8 decoder IC and 4 input NAND.

Components used: IC 74 LS138, IC 74LS20, patch chords, power chords, trainer kit.

Pin diagram of ICs used:

Theory:
The simplest Binary adder is a half adder. It has 2 inputs and 2 output bits. One is the sum and the other
is carry.
A half adder has no provision to add carry of lower order bits when binary numbers are added. When two
input bits and a carry are to be added, the number of input bits become 3 and input combination increases
to 8. For this a full adder is used. Like half adder, it has 2 outputs. One is sum and the other is carry. New
carry generated is denoted as Cn and carry generated from addition of previous lower order bits is denoted
as Cn-1

Function table

A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Circuit Diagram

Procedure:
1. Verify all components & patch chords whether they are in good condition or not.
2. Make connections as shown in the circuit diagram.
4. Give supply to the trainer kit.
3. Provide input data to circuit via switches.
4. Verify truth table sequence & observe outputs.
VHDL
VHDL stands for Very High Speed Integrated Circuit Hardware Description Language. It describes
the behavior of an electronic circuit or system, from which the physical circuit or system can then be
implemented

VHDL was originally intended to serve 2 main purposes-

• It was used as a documentation language for describing the structure of complex digital circuits.
• VHDL provides features for modeling the behavior of a digital circuit.

General Features of VHDL

• The language can be used as an exchange medium between chip vendors and CAD tool user and can
be used as communication medium between CAD and CAE tools.

• It supports hierarchy.

• It is not a case sensitive language.

• It is strongly type checked language.

• It provides design portability and flexible design methodologies: top down, bottom up or mixed

• It supports both synchronous and asynchronous timing models.

• Nominal Propagation delays, min-max delays, setup and hold timing constraint and spike detection can
be described in this language.

Usage of the Tool

It is one of most popular software tool used to synthesize VHDL code. This tool includes many steps. To
make user feel comfortable with the tool the steps are given below:-
 Select NEW PROJECT in FILE MENU.
Enter following details as per your convenience
Project name : sample (should be same as the entity name in
your VHDL code
Project location : C:\example( As per convenience use default
Top level module : HDL
 In NEW PROJECT dropdown Dialog box, Choose your appropriate device specification. Example is
given below:
Device family : cyclone
Device : EP1C6Q240
Package : PQFP
Pincount : 240
Speed grade :8
On File Drop down menu choose new Vhdl file
Type the Vhdl code
Under the Processing Drop down menu choose Start compilation
If there are errors go back to the VHDL code and correct it. Once the compilation is successful
 Under the processing drop down box select simulator tool select the simulator mode to functional and
click on generate functional simulation netlist. we Get the success message.
 Under simulator tool click on open. In the empty location right click . Click on insert on NODE or BUS.
Then click on NODE finder. In the window opened select pins to unassigned. Click on List. IT will list all
the Net list select all and click ok.
 The input and output appears give appropriate input.
 On the simulator tool click on start simulation. Simulation success message will be prompted
 On simulator tool click on report to see the output.

Create a new project for every new VHDL code

The primary data type std_ulogic (standard unresolved logic) consists of nine character literals in the following
order:

'U' - uninitialized

'X' - strong drive, unknown logic value

'0' - strong drive, logic zero

'1' - strong drive, logic one

'Z' - high impedance

'W' - weak drive, unknown logic value

'L' - weak drive, logic zero

'H' - weak drive, logic one

'-' - don't care

1. b. Write the verilog /VHDL code for 8:1 MULTIPLEXER. Simulate and verify its
working.

MULTIPLEXER
I 8 TO 1 Zout
8

TruthTable
INPUTS
SEL (2) SEL (1)
0 0
0 0
0 1
0 1
1 0
1 0
0 1
1 1
3
SEL OUTPUTS
SEL (0) Zout
0 I(0)
1 I(1)
0 I(2)
1 I(3)
0 I(4)
1 I(5)
1 I(6)
1 I(7)

VHDL code for 8 to 1 mux (Behavioral modeling).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux1 is
Port ( I : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0);
zout : out std_logic);
end mux1;
architecture Behavioral of mux1 is

begin
zout<= I(0) when sel="000" else
I(1) when sel="001" else
I(2) when sel="010" else
I(3) when sel="011" else
I(4) when sel="100" else
I(5) when sel="101" else
I(6) when sel="110" else
I(7);

end Behavioral;
2. b. Write the verilog/ VHDL code for FULL ADDER. Simulate and verify its
working.

X
S
FULL
Y
ADDER
Cout
Z

Truth Table
INPUTS OUTPUTS

X Y Z SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1

1 1 0 0 1
1 1 1 1 1

Expression: Sum(S)=X  Y  Z
Carry(Cout) = XY +YZ + ZX
VHDL code for Full adder using data flow

library IEEE;
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY fa IS
Port (X, Y, Z : in STD_LOGIC;
Cout, S : out STD_LOGIC);
End fa;

ARCHITECTURE df OF fa IS
Begin
Cout<= ((X and Y) OR (y AND z) or (z and x);
S<= (X XOR Y) XOR Z;
End df;