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AXI Protocol
Introduction

AXI, the third generation of AMBA interface AMBA 3 specification, is targeted at high performance, high clock frequency
system designs and suitable for high speed sub-micrometer interconnect:
separate address/control and data phases
support for unaligned data transfers using byte strobes
burst based transactions with only start address issued & issuing of multiple outstanding addresses
easy addition of register stages to provide timing closure
AXI consist of five different channels:
Read Address Channel
Write Address Channel
Read Data Channel
Write Data Channel
Write Response Channel

[https://2.bp.blogspot.com/-CbsnQP8muCs/WMg5e3kWx2I
/AAAAAAAABiU/HxDWCSTvp5Mal5Wga1AEDlRmjPV4iEaXwCEw/s1600/AXI%2BChannels%2BMaster%2BSlave.png]

AXI Read operation architecture:

[https://4.bp.blogspot.com/-OTZhf3n1dx4/WNgpmmrccVI
/AAAAAAAABow/Q8oWiTk53MYD0I_4EvVGvmV9wP5q2_IXACLcB/s1600/AXI%2BFigure%2B00.png]

AXI Write operation architecture:

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[https://4.bp.blogspot.com/-LEy_UUkrRYg/WNgpm8S0ISI
/AAAAAAAABo0/Uw8gx0ahXaAWPY3TphOU2gB5HfjKw3d2wCEw/s1600/AXI%2BFigure%2B01.png]

Transaction channel handshake pairs:

[https://2.bp.blogspot.com/-Ofo3OzrEsj0/WMg5tMNhgXI
/AAAAAAAABjk/YDV7t3Ekvesl0-b7wC75SsQDhi0x8UIVwCEw/s1600/Transaction%2BChannel%2BHandshake%2BPairs.png]

Handshake process:

All five channels use the same VALID/READY handshake to transfer data and control information. This two-way flow
control mechanism enables both the master and slave to control the rate at which the data and control information
moves. The source generates the VALID signal to indicate when the data or control information is available. The
destination generates the READY signal to indicate that it accepts the data or control information. Transfer occurs only
when both the VALID and READY signals are HIGH.

There are three scenarios when the transfer happens as shown below:

[https://4.bp.blogspot.com/-dAnBSv2oy0Q/WMg5e20RigI/AAAAAAAABjs
/CQQY08lWbBQoTN7a61e-Zqz5YEaf0QvJwCEw/s1600/AXI%2BFigure%2B1.png]

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/LxalbNHa2D4rjfc3BIOxJp2pQsCbwXUFACEw/s1600/AXI%2BFigure%2B2.png]

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/kT_3kDTgwgMWo7mwu168gGUwQlObdGh5wCEw/s1600/AXI%2BFigure%2B3.png]

Signal Description:

[https://1.bp.blogspot.com/-fqeERr9Xhds/WMg5jep968I
/AAAAAAAABjs/Hz-fHUGmWxwG4z6P1_6jV1ZAzy-3Je7KQCEw/s1600/AXI%2BSignals%2BPage%2B1.png]

[https://4.bp.blogspot.com/-cC3MXfrux90/WMg5jz9_BDI
/AAAAAAAABjs/Dt2qkVj_44UyKOm5BOfKwMHoDGOUGq5zQCEw/s1600/AXI%2BSignals%2BPage%2B2.png]

Master Slave configuration connected via interface through interconnect:

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/AXI%2BFigure%2B02.png]

There are different encoding techniques used in AXI for burst length, busrt size, burst type, cache encoding, protection,
atomic access, response,

[https://1.bp.blogspot.com/-wwhcuo8QzBU/WMg5gzFEFdI/AAAAAAAABjs/4-
VCpgLKNjwd53zuReUH-_-MmclhsMn5ACEw/s1600/AXI%2BFigure%2B4.png]

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/Jqn4k1UN1I8BpZDg5VgAEtX3zd9Yc8_bACEw/s1600/AXI%2BFigure%2B5.png]

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/AXI%2BFigure%2B6.png]

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/-qJ-cN21W_KY/WMg5hx2L4dI/AAAAAAAABjs/L-xlaAkldlAh_6tjU9QTy6VcaPVH0PnsACEw/s1600/AXI%2BFigure%2B7.png]

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[https://2.bp.blogspot.com/-F2x54n-32Gg/WMg5ioPfd7I/AAAAAAAABjs
/bEhuDz_8C2wIk5MLLYJ0e4wINVZHu_REACEw/s1600/AXI%2BFigure%2B9.png]

[https://2.bp.blogspot.com/-o3KYJr_L4i4/WMg5fLtE7hI/AAAAAAAABjs/99Sv_jpcnWEgkWPur8MuhSDCGB2n8Q_DQCEw/s1600
/AXI%2BFigure%2B10.png]

Timing Diagrams for read burst, overlapping read burst and write burst:

[https://3.bp.blogspot.com/-FsS0aw7RI5I/WNgpn1aeP8I/AAAAAAAABpI/10LYrRM9TWwn3aABcpCaMMW0B_rDJxCagCEw/s1600
/AXI%2BFigure%2B03.png]

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/AXI%2BFigure%2B04.png]

[https://4.bp.blogspot.com/-jmreyV1095k/WNgpoh3Si4I/AAAAAAAABpI/rFq30qYMBActrTdBEiGe2xb4vjqdn6k4gCEw/s1600
/AXI%2BFigure%2B05.png]

Low-power interface signals:

[https://1.bp.blogspot.com/-qJtRAQzQQvY/WMg5kI0VmOI/AAAAAAAABjs/PmjGj6jSvaUh7hWeHKkLAsVF5yLagTxVACEw/s1600
/AXI%2BSignals%2BPage%2B3.png]

[https://2.bp.blogspot.com/-b9zscDtYXkw/WMg5fwLPq8I/AAAAAAAABjs/-96-0K5RJLsrKqrQ71gXjHXHOVQUstlsgCEw/s1600
/AXI%2BFigure%2B11.png]

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/AXI%2BFigure%2B12.png]
Difference between Exclusive access and Locked access:

The basic process for an exclusive access is:


A master performs an exclusive read from an address location
At some later time, the master attempts to complete the exclusive operation by performing an exclusive write to the
same address location
The exclusive write access of the master is signalled as:
Successful if no other master has written to that location between the read and write accesses
Failed if another master has written to that location between the read and write accesses. In this case the
address location is not updated
Locked access:

When the ARLOCK[1:0] or AWLOCK[1:0] signals for a transaction show that it is a locked transfer then the interconnect
must ensure that only that master is allowed access to the slave region until an unlocked transfer from the same master
completes signalling the release of the locked trasnfer. The arbiter within the interconenct is used to enforce this
restriction.

Burst operation:

In AXI channel, the number of data transfers in a single burst are called as beats.

[https://3.bp.blogspot.com/-FLDUcV46DmU/WMlt2ZfeplI
/AAAAAAAABkI/Afozv9RUpvkdi6FQs_-t6gzu5TyaMv6UgCLcB/s1600/Burst%2Boperation.png]

Burst Transfer Type:

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[https://3.bp.blogspot.com/-KOPpulZ6LUc/WMlt2RRFIHI
/AAAAAAAABkE/TFOwaCPO2Ak1J-_yKBoEmcFNWb9O8L1DQCEw/s1600/Burst%2BTransfer%2BType.png]
Normal/Privileged access:

Normal/Privileged is used by some masters to indicate their processing mode. A privileged processing mode typically has
a greater lever of access within a system.

[https://4.bp.blogspot.com/-q92g0Nj2GQI/WMlvXbxmyII
/AAAAAAAABkU/U5ZEkvQ5stoOxWRoIlqxtzbPkwrU0QJJACLcB/s1600/AXI%2Baccess.png]
Different kinds of burst type:

Fixed burst: In a fixed burst, the address remains the same for every transfer in the burst. This burst type is for repeated
accesses to the same location such as when loading or emptying a peripheral FIFO.

Incrementing burst: In an incrementing burst, the address for each transfer in the burst is an increment of the previous
transfer address. The increment value depends on the size of the transfer. For example, the address for each transfer in
a burst with a size of four bytes is the previous address plus four.

Wrapping burst: A weapping burst is similar to an incrementing burst, in that the address for each transfer in the burst is
an increment of the previous transfer address. However, in a wrapping burst the address wraps around to a lower
address when a wrap boundary is reached. The wrap boundary is the size of each transfer in the burst multiplied by the
total number of transfers in the burst. There are two restrictions for wrapping bursts: the start address must be aligned to
the size of the transfer and the length of the burst must be 2, 4, 8, or 16.

AXI Benefits:
Faster testbench development and more complete verification of AMBA AXI 3.0/4.0 designs
Easy to use command interface simplifies testbench control and configuration of master and slave
Simplifies results analysis
Runs in every major simulation environment
Drawbacks of AXI:
The AMBA AXI4 has limitations with respect to the burst data and beats of information to be transferred
The burst must not cross the 4k boundary. Bursts longer than 16 beats are only supported for the INCR burst type
Both WRAP and FIXED burst types remain constrained to a maximum burst length of 16 beats. These are the
drawbacks of AMBA AXI system which need to be overcome
AXI features:
AMBA AXI 3.0/4.0 Verification IP provides a smart way to verify the AMBA AXI 3.0/4.0 component of a SOC or a
ASIC
AMBA AXI 3.0/4.0 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC,
VERA, Specman E and non-standard verification environment
Summary of AXI:
Productivity—By standardizing on the AXI interface, developers need to learn only single protocol for IP
Flexibility

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A robust collection of third-party AXI tool vendors is available that provide a variety of verification, system
development, and performance characterization tools

Comparison betweenAMBA AHB and AMBA AXI Bus System Modeling:

[https://3.bp.blogspot.com/-SHoxxdjnkIc/WMg5lL5bKhI
/AAAAAAAABjs/8R1MCnwCYXwMjClg81KZbEN0Sxb-DFAygCEw/s1600
/Comparing%2BAMBA%2BAHB%2Bto%2BAXI%2BBus%2BSystem%2BModeling.png]

Simulation study between AMBA AHB and AMBA AXI Results:

[https://3.bp.blogspot.com/-FbIvcZmuYYo/WMg5lK3KgHI
/AAAAAAAABjs/-MjQMBu0NPga6VvNlBQmfJq4bBTNEVF8gCEw/s1600
/Simulation%2Bstudy%2Bbetween%2BAMBA%2BAXI%2Band%2BAMBA%2BAHB%2BResults.png]
Throughput:
Throughput or network throughput is the average rate of successful message delivery over a communication
channel
It is closely related to the channel capacity of the system, and is the maximum possible quantity of data that can be
transmitted under ideal circumstances
The throughput is usually measured in bits per second (bit/s or bps), data packets per second or data packets per
time slot
AXI protocol notes and Interview Questions:

AMBA AXI is targeted at high performance , suitable for high-speed submicron connect .

Features:
separate address/control and data phases
support for unaligned data transfer using byte strobes
its backward compatibel with existing AHB and APB interface
Architecture-wise features:
AXI protocol is burst based
Every transaction has address and control information on the address channel
Total 5 channels
Independently acknowledged address and data channels
Out-of-order completion of bursts
Write data interleaving
Exclusive access (atomic transaction)
Access security support
System level cache support
Unaligned address & byte strobe
Static burst, which allows bursts to FIFO memory
Low power mode

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2. AXI3 supports write interleaving. AXI4 does NOT support write interleaving
3. AXI3 supports locked transfers, AXI4 does NOT support locked transfers
4. AXI4 supports QoS, AXI3 does NOT suppor QoS.

I have seen many IP providers e.g. Synopsys supporting burst lengths up to 256 beats in AXI3
I have also seen many IP providers e.g. Synopsys NOT supporting write interleaving in AXI3.

Looks like the industry norm is to use AXI3 with burst lenghts up to 256 beats without support for write Interleaving.

2. why there is no separate response channel for read burst ?


I would guess it is because the VALID/READY handshake mechanism only allows for traffic flow in one direction, so for
read transactions the traffic flow is slave to master for both data and response, sharing a VALID/READY handshake,
whereas for write transactions the data is master to slave, but the response is slave to master, hence the response
needing a separate channel to support the required VALID/READY controls.

Questions and Answers:

1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response for each beat in
a Read burst?

All of the AXI channels pass information in only 1 direction (only the xREADY signal goes against the channel direction),
so for a slave to give a response back to the master for a write transaction, would need a separate channel.
I guess this channel could have been defined to include a BRESP for each write data item, but this would increase the
bandwidth requirement for this channel, and as in most applications you will just repeat the complete transaction for a
non-OKAY response, few applications would make use of the additional detail of which transfer in a write burst caused a
failure.
You do give a RRESP response for each read data item because the higher bandwidth channel is already there,

2) How to terminate A read/write burst? Specification says we can not stop bursts intermittantly.

Simple answer, you cannot.


As soon as the AXI master indicates that it will perform X number of transfers in a transaction, it must complete X
transfers. There is no "Early Burst Termination" concept like there was in AHB.
For write transactions the master could complete the burst, but driving the WSTRB bits all to logic '0' (dummy accesses)
so that no data is actually being transferred to the slave, but for read transactions there is no equivalent, and so "real"
read accesses will be completed.

In AHB Bursts can be early terminated either as a result of the Arbiter removing the HGRANT to a master part way
through a burst, or after a slave returns a non-OKAY response to any beat of a burst. Note however that a master cannot
decide to terminate a defined length burst unless prompted to do so by the Arbiter or Slave responses.
All AHB Masters, Slaves and Arbiters must be designed to support Early Burst Termination.

3) Can A master can give WLAST in middle of a burst transfer?

No. WLAST can only be asserted while WVALID is high when the final WDATA of a burst is being transferred. Indicating
WLAST (and WVALID) too early in a burst would be a protocol violation.
Also, many slave designs will not use the WLAST input, and will simply count data items coming in, so this would not be
a safe (or legal) method of terminating a burst.

4) in the same way if slave assersts RLAST before the completion of a busrt read?

If the slave drives RLAST (and RVALID) too early, this too is a protocol violation, and just as for the WLAST signal, some
masters might not be monitoring RLAST, so this illegal use could be missed anyway.

5) If WLAST and RLAST can not do the above cases, then what is the special use of WLAST and RLAST because we
are getting individual beat responses anyway?

WLAST and RLAST can be used by masters and slaves that need to be told when the final data in a burst is being
transferred.
Most masters and slaves will count the data coming in against how many transfers were indicated on AWLEN and
ARLEN, so in these designs the xLAST inputs would not be required.
However to support all master and slave designs, masters must always drive WLAST when appropriate, and slaves must
drive RLAST.

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master), you want to make sure that you complete the READ/WRITE sequence without another master changing the
shared location.
If your master read the shared memory location, and it was changed by another master before your master could
complete the subsequent write to that location, the interim write from the other master would be lost, which could have an
impact on how your system works (control information lost).
So Exclusive Accesses are a hardware mechanism to support the software, indicating to the master when it did have
uninterrupted access to the shared location, meaning that no write accesses from other masters will be accidentally
overwritten.

7) Is there a possibility that A Read transaction can complete in One Cycle?

A default ARREADY value of LOW is possible but not recommended, because it implies that the transfer takes at least
two cycles, one to assert ARVALID and another to assert ARREADY.
No. It would take a minumum of 1 clock cycle to pass the address from the master to the slave (assumes ARREADY was
high when ARVALID was asserted), and then a minimum of 1 clock cycle to pass the data from the slave to the master
(assumes RREADY was high when RVALID was asserted). If ARREADY is initially low when an address is signaled on
ARVALID, it will take one clock cycle for the slave to sample this ARVALID and then assert ARREADY (if it can accept
the address), and the address handshake then completes on the next clock rising edge (when both ARREADY and
ARVALID are high).
So 2 clock cycles just to pass the address from master to slave if ARREADY defaults to LOW.
It would then take at least a further clock cycle before the read data could be returned to the master.

More questions:

Difference between AHB and AXI?

What is AXI Lite?

Name five special features of AXI?

Why streaming support,it's advantages?

Write an assertion on handshake signals - ready and valid, ready comes after 5 cycles from the start of valid high?

Explain AXI read transaction

What is the AXI capability of data interleaving?

Explain out-of-order transaction support on AXI?

Explain multiple outstanding address pending?

Any flow control mechanism in AXI?

How to ensure data integrity on AXI?

What is 'last' signal?

What is beat and burst length?

What are bursts and transfers?

Maximum size of a transfer?

Write response codes?

What is strobing in AXI?

Thank You!

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Posted 15th March 2017 by mitesh 1st January 2010 :)

1 View comments

HANKIPANKI April 8, 2018 at 2:10 AM


hello sir,
i want to query about the code for axi3 in system verilog. if you can help me out please drop your number on my mail
id. my mail id is tushar.chauhan3755@gmail.com
Thank you
Reply

Comment as:

Publish Notify me

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