Slides 15C PCI Express

PCI Express™ Basics &
Applications in Communication
Systems
Akber Kazmi
PLX Technology
Copyright © 2004, PCI-SIG, All Rights Reserved 2

Agenda
PCI Express Overview, Components &

Architecture
PCI Express Protocol Layers
Needs of Communication Systems & PCIe
PCI Express in Communication Systems
Summary
PCI-SIG Developers Conference Copyright © 2004, PCI-SIG, All Rights Reserved 3

PCI Express
High Level Overview
Chip/chip and fabric interconnect technology
High speed serial, packet based
Fully open and standardized
Complete compatibility with PCI & PCI-X
Cost driver: PCs/Graphics (economies of scale)
Advanced features: QoS, Flow Control, data
error detection
Applicable to wide variety of applications
9 Servers, Storage, Communications, embedded
Extensive industry support

PCI Express Features/Benefits
PCI Express Features Benefits
• PCI transparency • Smooth migration, SW re-use, simple validation
• TC/VC mechanism • QoS & isochrony
• High bandwidth • Peak traffic loads, support high throughput apps.
• Flow control • Buffer size flexibility, cost flexibility

• Reliable link layer • No dropped packets, simplified SW, high availability
• Robust link layer • Maintain communication for HA or diagnosis
• E-CRC • End-to-end data integrity
• Error reporting, fault • System management, serviceability, availability

isolation
• Hot-plug • Optimize density, support cold spares
• Power management • Reduced power consumption and emissions
• High Speed Serial • Reduced cost, pin count, PCB layers & area
PCI
PCIExpress
Expresscan
canbe
beused
usedin
inmany
manymarket
marketsegments
segments
Typical PCI Express System
Root Complex
Connects host CPU/memory
complex to PCI Express CPU CPU
hierarchy
Not limited to a single device
One or more downstream ports
Switch
Assembly of logical PCI-to-PCI bridges
One upstream port directed towards root
MEM Root Complex
complex
One or more downstream ports
Switches can be stacked Links
Peer to peer traffic allowed
Bridge
One upstream port
PCI Express PCI Express
directed towards root Bridge Switch
complex
One downstream to
other devices
PCI/ PCI-X This Switch
J2
Example: PCI or J1 J2 has 4 ports
PCI-X bus J1 J2
J1 PCI Express PCI Express
Switch End Point
Endpoints
Native PCI Express Endpoints
Examples:
USB, InfiniBand, E’net
FibreChannel, etc.
Configuration
1) The Host CPU enumerates
the PCI Express system CPU
2) Enumeration MUST flow
downstream
MEM Root Complex
3) Switches are enumerated
as a number of P2P bridges
4) Bridges are usually

enumerated as a P2P
bridge (Type 1 header)
Bridge Switch
PCI/ PCI-X
J2
J1 J2
J1 J2
J1
PCI Express
5) End points are
enumerated in the End Point
same manner as PCI
devices are. Type 0
header
Data Flow
1) Data can flow from the
CPU to an end point CPU
MEM Root Complex

3) Peer to Peer data flow
is also allowed

4) The virtual P2P bridges Bridge Switch
within the Switch route
PCI/ PCI-X
the data to the appropriate J2
port J1 J2
J1 J2
J1
PCI Express
End Point
2) Data can flow from an End
point to the CPU

PCI Express – Software Model
Host Host
Bus 0
Bus 0
P2P
P2P Bus 1
Bus 1
P2P P2P
Bus 3 Bus 2
End Point End Point End Point End Point
B1, D1, F0 B1, D0, F0 B3, D0, F0 B2, D0, F0
PCI System Equivalent PCI Express A switch looks like a

System collection of P2P
Where: B=bus, bridges. Bus 1 is a
D=device, virtual PCI bus
F=function

Data Routing
PCI Compatible Routing Methods
9 Address Routing
– Memory and I/O read/write
– Optional for messaging
9 ID Routing
– Configuration read write
– Completions
– Optional for messaging
PCI Express only routing methods
9 Implicit Routing
– Messaging
• packets are routed based on a sub-field in the packet header.
• Implicitly routed messages eliminates most of the sideband signals for
interrupts, error handling, and power management.

Address Routing Examples
Root Complex
Host/PCI
CPU
Bridge
Bus0
P2P Base=0 Base=7M P2P

6) 5.5M is within
3) 9M is not Device0 Limit=7M Limit=8M Device1
Port 6 base limit
within 0 to 7M so route
so forward Bus1 downstream
upstream Upstream
Base=0
P2P
Limit=7M
Port0
2) 9M is not
5) 5.5M is not
within 0 to 1M Bus2
within 6 to 7M
so forward
upstream so forward
upstream
Base=0 Base=1M Base=2M Base=3M Base=4M Base=5M Base=6M
Limit=1M Limit=2M Limit=3M Limit=4M Limit=5M Limit=6M Limit=7M
Down Down Down Down Down Down Down

P2P P2P P2P P2P P2P P2P P2P
1) This device Port1 Port2 Port3 Port4 Port5 Port6 Port7
writes data with 4) This device

address =9M
Bus3 Bus4 bus5 Bus6 Bus7 Bus8 Bus9 writes data with
address =5.5M
Base=0 Base=1M Base=2M Base=3M Base=4M Base=5M Base=6M
Size=1M Size=1M Size=1M Size=1M Size=1M Size=1M Size=1M

Type 1
ID Routing 1) Completions use the
Bus, Dev, Fun of the
Root Complex
configuration CPU
Bus=0
Sub=9
Host/PCI
Bridge
requester device to route
accesses are completion data.
Bus0
converted to Secondary and

P2P subordinate bus numbers
Pri=0 Pri=0
Type 0 P2P
Device0
Sec=1 Sec=10
Device1
accesses at
Sub=9 Sub=11 make routing easy.
the destination 2) Device 8,0,0
Bus1
bus. E.g. a requests read
Upstream Pri=1
Type 1 access P2P Sec=2 data from device
Port0 Sub=9
to a device with 9,0,0
bus number 1 Bus2
is converted to
a Type 0 3) Device 9,0,0
access here Pri=2 Pri=2 Pri=2 Pri=2 Pri=2 Pri=2 Pri=2 sends data
Sec=3 Sec=4 Sec=5 Sec=6 Sec=7 Sec=8 Sec=9
Sub=3 Sub=4 Sub=5 Sub=6 Sub=7 Sub=8 Sub=9 with Requester
Configuration Down Down Down Down Down Down Down ID of 8,0,0
and P2P
Port1
P2P
Port2
P2P
Port3
P2P
Port4
P2P
Port5
P2P
Port6
P2P
Port7
completions
Bus3 Bus4 Bus5 Bus6 Bus7 Bus8 Bus9
accesses use
Endpoint Endpoint Endpoint
Bus, Device, Bus 3
Endpoint Endpoint Endpoint Endpoint
Bus 8 Bus 9
Dev. 0 Dev 0 Dev 0
Function Fun. 0 Fun 0 Fun 0
numbers.
Reverse and Forward Bridging
Processor
SDRAM
GFX North Bridge
PCI
HDD South Bridge Ethernet SCSI

PCI/PCI Express
Reverse Bridge
PCI Express
USB I/O Endpoint
PCI Express
Endpoint
Forward
PCI
Bridge
End-point
PCI Express Switch

Non-Transparent Bridge
Provides isolation of host memory domains

Presents the whole Sub-system as a Type0
Endpoint to Host
Enables Inter-domain communication through
address translation and Requester ID translation
Provides Door-Bell and Scratch PAD register
mechanism for host communication

Non-Transparent Bridging
HOST
PCI Express
Link
Upstream
Port0 (T)
Internal PCI Bus
Virtual
Interface
NTB Port2 Down
Down Down
Port 1 Type0 Type1 Port 3 Port 7
Idle
Type0
Link
Interface
PCI Express PCI Express PCI Express PCI Express
Link Link Link Link
HOST/
Device Device Device
Fabric

Agenda

Architecture
Summary

Protocol Stack
Device Device
A B
Transaction Layer Transaction Layer
Data Link Layer Data Link Layer
Physical Layer Physical Layer
Link

Transaction Layer
Upper layer of PCI Express protocol
Responsible for;
9 Storing negotiated and programmed configuration
information
9 Managing link flow control
9 Enforcing ordering and Quality of Service
9 Power management control/status
9 Transaction Layer Packet processing
9 Assembly, disassembly, high-level error checking
Start Seq Header Payload ECRC LCRC End
Transaction Layer
Data Link Layer
Physical Layer
Transaction Layer
- Implementation
Packet Header for Address Routing is either 12 or 16
bytes
0 1 2 3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
T E
Byte 0 R Fmt Type R TC R D P Attr R Length
Byte 4 Request Specific
Byte 8 Address [63:32]
Byte 12 Address [31:2] R
0 1 2 3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
T E
Byte 0 R Fmt Type R TC R D P Attr R Length
Byte 4 Request Specific
Byte 8 Address [31:2] R

Data Link Layer Packets
Data Link Layer Functions
9 Integrity of Transaction layer packet (TLPs)
– Link-level error detection and re-transmission of bad TLP’s
9 Tracking state of link and passing link status to upper layers
9 Conveying power management state info.
9 Initialization and updates of credit based flow control
Classes of DLLPs
9 Transaction Layer Packet acknowledgements (Ack/Nak)
9 Power management
9 Flow Control (Flow Control packets)
9 Vendor specific DLLP
Create and terminate DLLPs for Link layer info
Start Seq Header Payload ECRC LCRC End
Transaction Layer
Data Link Layer

PCI-SIG Developers Conference Copyright © 2004, PCI-SIG,
Physical All Rights Reserved
Layer 20
DLL and TL Interaction
Transaction Layer
originates header, data and
digest, checks flow control PCIe Device A PCIe Device B
credits and forwards to DLL.
Device Core Device Core
DLL adds sequence
number (0-4095) and
CRC, stores transaction
HDR DATA Dgst Transaction Layer Transaction Layer
in Retry buffer and
forwards to Phy. Data Link Layer Data Link Layer
Retry
Seq Num HDR DATA Dgst CRC Error
Check
Buffer
Phy adds STP/END and
sends to Receiver of
device ‘B’. Physical Layer Physical Layer
STP Seq Num HDR DATA Dgst CRC END
CRC and sequence

number are checked. END CRC Ack/Nak SPD
Valid packets are
forwarded to ‘A’ checks if an ACK. TLP’s
Transaction Layer with sequence number <= A NAK is sent for
current one are removed bad & an ACK is
from buffer. If a NAK then sent for good TLP’s
all unacknowledged TLP’s
PCI-SIG Developers Conference
are resent
Copyright © 2004, PCI-SIG, All Rights Reserved 21
Physical Layer Function
Provides the physical connection
between devices PHY PHY
Logical Functions Tx Rx Tx Rx
9 Link training and status
Logical Logical
9 Packet framing, Data striping/Data
assembly
9 Data scramble, 8B/10B encode/decode
9 Symbol lock
Tx Rx Tx Rx
Electrical Functions Electrical Electrical
9 Receiver detect
9 Receive clock recovery Port Port
Link
9 Bit lock, Serialization/Deserialization
9 LVDS signaling

Agenda

Architecture
Summary

The Challenge
In general, too many interconnects
Goals
9Minimize the number of interconnects
– Reality: there will always be multiple interconnects
9Technically suitable and economically viable
– Relieve the need to create proprietary technologies
– Provide broad based industry acceptance & economies of
scale
9Interoperable multi-sourced switches, bridges & end-
points
High
HighSpeed
SpeedSerial
SerialInterface
Interfacewith
withEconomies
Economiesof
ofScale
Scale

Functional Needs
Connectivity, Bandwidth and Scalability

Data Integrity and Reliability
Serviceability and Availability
Quality of Service

Connectivity, Bandwidth &
Scalability
x1 Lane
Chip-to-chip, board-to-board, box-to-box Character7
9 Cable spec in development Character6
Combining multiple lanes in wider port Character5
(x1, x4, x8, x16, x32) Character4
9 Current spec supports 2.5GB/s per lane Character3
Character2
9 Gen-2 in definition Character1
Byte striping used for multiple lanes Character0
No sideband signals
9 8b/10b encoding used
Character4 Character5 Character6 Character7
Character0 Character1 Character2 Character3
x4 Lane
x4 Byte Striping
Data Integrity Support
Data Link Layer Mechanisms (Link/Local):
9 TLPs protected using 32bit CRC
9 DLLPs protected using 16bit CRC
9 TLP error recovery through Data Link-level retry
9 Supplemental coverage through 8b/10b
9 Loss of packets detected using Sequence Numbers
Transaction Layer Mechanisms (End-to-End):
9 Optional coverage using 32bit CRC
9 Data Poisoning capability
Unambiguous Explicit error forwarding

Framing with 8b/10b mechanism End-to-end 32b CRC coverage
STP Seq # Hdr Data ECRC LCRC END STP Seq # + 1
False/missed start Transaction Layer Packet protected False/missed

correction with 32b CRC termination correction
Link Data Integrity –
Retry Example
X √
P3P2
1. Three TLPs sent from P1
A to B
2. Packet 2 corrupted
3. B detects corruption and NAK P2
and
issues Nak DLLP
4. A resends Packet 2 and
A beyond B
following Packet
√
P3 √
P2
5. B acknowledges successful
receipt of Packets
ACK upto
P3

End-to-End Data Integrity - ECRC
Component internal errors are critical
Root
Complex
9 Header errors Æ TLP misrouting
9 Data corruption Æ application and
system failure
End Point
End-to-end data integrity using ECRC
9 Protecting from system-wide errors
Switch
X Packet 9 Enabling upper layers error recovery
corrupted ECRC basics:
Switch within a Switch
9 Optional Capability – additional 32bit field
(part of TLP)
9 Generated by the source component –
End Point End Point End Point applies to all invariant TLP fields
9 Switches must pass ECRC unchanged
9 Checked in the destination component –
resulting behavior is device specific

PCI Express Hot Plug
PCI Hot Plug enables add or remove of PCI add-in
device without interrupting normal system operation or
requiring a power down/system reset
9 Root ports and downstream ports of switches are the hot
pluggable ports in a PCI Express hierarchy
9 Elements of the Standard hot plug usage model derived from
SHPC
9 Hot plug registers are integral part of the PCI Express registers
– Do not require a separate set of memory mapped registers like
PCI SHPC
9 Native hot plug solution is specific to PCI Express
– SHPC continues to be the mechanism for parallel bus PCI
implementations
PCI
PCIExpress
ExpressEnables
EnablesHot
HotPlug
PlugCapability
Capabilityfor
forthe
theMainstream
Mainstream
Quality of Service
Traffic Classes (TC)
9 Software-controlled method to add traffic priority
9 Part of HEADER field in a TLP
Header Payload
Virtual Channels (VC)
9 Hardware method to provide separate data paths
9 Part of queue structure in switches and bridges
9 Hardware may have fewer than 8 VCs
TC0 VC0
Software TC1 VC1 Hardware
.
TC7
VCs and TCs
QoS though VC’s and TC’s
9 Software decides what TC a packet should use
9 VC’s allow multiple independent logical data flows over the link
9 TC’s are mapped into VC’s
9 Multiple TC’s may be mapped into one VC
9 TC/VC mappings can be configured per port
9 Ingress and egress payload credits are programmable per VC, port and
transaction type
VC Buffers
VC Buffers
Device A
Device B
TC[2:0] to VC0
TC/VC Mapping
VC0
Arbitration
TC[7:0] LINK TC[7:0]
VC1
TC[7:3] to VC1

Arbitration
9 TC’s are routed through switches with different priorities based
on arbitration policy
– Switches use Port arbitration and VC arbitration
– TC mapping, Port and VC arbitration schemes can be configured on
a per port basis – stored in PCI Express Extended Capability set.
– Arbitration schemes include;
• Hardware Fixed
• Weighted Round Robin (32)
• Timed weighted (128)
– Arbitration schemes are set up in VC Arbitration Tables and Port
Arbitration Tables

Port & VC Arbitration
Port Arbitration VC Arbitration
within a VC in Egress port of an Egress port
TC/VC
Mapping
0 of the ARB VC 0
Egress ARB 2
Port VC 1
Ingress ARB Egress
TC/VC
Ports Mapping
Ports
of the
1 Egress These structures are
3
Port replicated for each egress port
Port Arbitration:
9 Traffic targeting same VC/Egress Port
9 Fixed Round-Robin (RR), programmable Weighted RR,
programmable Time-based WRR
VC Arbitration:
9 Traffic from different VC competing for the Link
9 Fixed priority, RR, programmable WRR
Agenda

Architecture
Summary

PCI Express in
Communications
PCI Express meets the interconnect needs of the communications
industry
Suited for Metro, Edge, Mobile and Storage network equipment
NAS Storage & Focus of

SAS, SATA Servers Storage Networks PCI Express in
or FC SAS, SATA, Communication Systems
iSCSI, or FC
Fiber Channel
Fiber Channel
Core
Network
Metro Public
PCI, PCI Express Networks
Enterprise
Ethernet
SONET,
XAUI OIF standards
PCI, Backplane PCI Express
PCI Express
PCI-X, PCI Express

Single Host Interconnect
PCI Express best suited as a local interconnect
of single-host systems.
– Connects the host with the I/O subsystems
– Subsystems may be on same board, or separate I/O cards
– Serves the needs of both control and data traffic
Supports single board, mezzanine and bladed
systems
Communications needs of
9 Peer-to-peer transfers are supported thru switching
9 Multi-host can be supported with non-transparent
bridge implementation (same as PCI)
Reliable
ReliableLink
Linklayer
layerwith
withFlow
FlowControl
Control
Chassis-Based System
Passive Backplane
Host/ /System
Host System Line
Line Resource
Resource Switch
Switch
Controller Line
Line
Cards Resource
Cards Card(s)
Controller Line
Cards
Cards Cards
Cards Card(s)
Cards
Cards
•• Security,
Security, database,
database, storage,
storage,
protocols,
protocols, signalling, etc.
signalling, etc.
•• Line
Line speed
speed packet
packet •• Voice:
•• System
System level
level control
control & & Voice: codecs,
codecs, speech
speech
forwarding
forwarding synthesis
management
management synthesis && recognition,
recognition, echo
echo
•• Control
Control && management
management of
of cancel,
•• Config,
Config, provisioning,
provisioning, errors
errors cancel,
lines, devices, connections,
lines, devices, connections, •• Content:
&
& faults,
faults, stats,
stats, billing,
billing, Content: transcoding,
transcoding,
users
users etc.
etc. localization
•• Redundant
Redundant w w failover
failover localization
•• Protocol
Protocol processing
processing •• Standalone
•• Some
Some resource processing
resource processing Standalone appliances,
appliances, oror
common designs
common designs

PCI Express Backplanes
Analogous situation to PCI
Single host + I/O cards
Dual redundant hosting requires non-transparent
bridging
9 Non-transparent function may be embedded in switch
ports
Distributed processing moves to system fabric
9 Issues are scalability, system management, etc.
9 Replace a shared bus with switch fabric
9 May integrate host controller on the Switch Fabric
blade

Line Card Architecture (now)
Current implementations:
9 Fixed Configurations
NPU Coprocessor
9 Chips connected in
discrete daisy chain
fashion
Traffic
I/O
9 Optimized for particular (PHY &
Manager
& Fabric
applications
Control
MAC) CPU Interface
9 Devices must
pass/process traffic
NPU
destined for another Coprocessor
device

Line Card Architecture (future)
PCI Express Switch
based architecture NPU Coprocessor
9 more flexible
9 scalable Control
CPU
9 reusable architecture I/O Traffic

PCI Manager
9 fewer traces ->cheaper (PHY &
MAC)
Express
Switch
& Fabric
Interface
boards
9 no multi-drop issues Coprocessor
NPU

PCI Express in ATCA (3.4)
CPU CPU
Host A Host B
CPU CPU
To Fabric 2
RC MEM
Host B
Fabric Card 2 To Fabric 2
RC MEM (Redundant)
Fabric Card 1PCI Express
To Fabric 1
PCI Express Host A
To Fabric 1
LC 1 LC 3
CPU
LC 2 CPU
EP
CPU
PCIX
EP MCH MEM
PCIX MCH MEM
To Host B 1GE
PEx RC MEM
PEx 1GE1GE
To Fabric B
PEx
Switch To Host A 1GE
Switch
AdvancedTCA PEx Line Card/Server Blades

To Fabric A
PEx
Switch Fabric Card 1
Backplane Switch
Fabric Card 2
I/O Mezzanine Form Factors
PCI-X P-
PCI-X P--
Device
PCI-X P--
Device
PCI-X P--
Device
PICMG Express
AdvancedTCA
XMC Mezzanine Card
AMC Mezzanine Card

I/O Mezzanine Cards
Arbitrary mix of Follows I/O device
I/O Mezzanines
migration to PCI
Mezzanine
Mezzanine Express
I/O I/O I/O I/O I/O I/O I/O Supports multiple I/O
Mezz. Mezz. Mezz. mezzanines
Host CPU (root
complex) could be on
Fanout the baseboard or on a
Switch mezzanine card
(optional)
Processor mezzanine
Port(s)
Port Root interconnect is
Switch
Complex
electrically similar to a
mini backplane
To
Baseboard Other
components
Baseboard
* Other brands and names may be claimed as the property of others.

Low/Mid Range Systems
Traffic Line Card N
Manager Switch Fabric
Port 1
PCI Express
PCI Express
Switch
Switch (Data)
Co-
NPU Processor
Port 1
PCI Express
Switch (Control)
Traffic Line Card 1

Manager
Port 1
PCI Express
Switch
Host/CPU
Co-
NPU Processor
Port 1
Control Module
Control Plane Data Plane

Control Plane (Switch)
I/O CPU
CPU
Local Bus Bus
FGPA Bridge Bridge
I/O CPU
CPU
Bus
I/O
Bridge
I/O Bridge Non-transparent Port

Agenda

Architecture
Summary

Summary
Mature Specification (1.0a)

High speed serial interconnect technology
Packet based layered protocol
Full compatibility with PCI based software
Data integrity at link and transaction layers
Flow control for optimum bandwidth/buffer usage
Hot plug and power management for RAS
Traffic Classes and Virtual Connections for quality of service
(QoS) support
Valuable features for communication systems design
Serves control plane and low/mid range data plane
Leverage and re-use existing PCI software

Thank you for attending the
PCI-SIG Developers Conference 2004.
For more information please go to

www.pcisig.com


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PCI Express™ Basics &

Copyright © 2004, PCI-SIG, All Rights Reserved 2

 PCI Express Overview, Components &

PCI-SIG Developers Conference Copyright © 2004, PCI-SIG, All Rights Reserved 3

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• Flow control • Buffer size flexibility, cost flexibility

• Error reporting, fault • System management, serviceability, availability

4) Bridges are usually

MEM Root Complex

PCI Express PCI Express

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PCI System Equivalent PCI Express A switch looks like a

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P2P Base=0 Base=7M P2P

Down Down Down Down Down Down Down

writes data with 4) This device

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converted to Secondary and

HDD South Bridge Ethernet SCSI

PCI Express Switch

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 Provides isolation of host memory domains

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Internal PCI Bus

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 PCI Express Overview, Components &

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Transaction Layer Transaction Layer

Data Link Layer Data Link Layer

Physical Layer Physical Layer

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Data Link Layer

Byte 4 Request Specific

Byte 8 Address [63:32]

Byte 12 Address [31:2] R

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Data Link Layer

CRC and sequence

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 PCI Express Overview, Components &

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 Connectivity, Bandwidth and Scalability

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 Combining multiple lanes in wider port Character5

(x1, x4, x8, x16, x32) Character4

9 Current spec supports 2.5GB/s per lane Character3

 Byte striping used for multiple lanes Character0

Character0 Character1 Character2 Character3

Unambiguous Explicit error forwarding

STP Seq # Hdr Data ECRC LCRC END STP Seq # + 1

False/missed start Transaction Layer Packet protected False/missed

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TC[7:0] LINK TC[7:0]

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 PCI Express Overview, Components &

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NAS Storage & Focus of

PCI-X, PCI Express

PCI-SIG Developers Conference Copyright © 2004, PCI-SIG, All Rights Reserved 36

PCI-SIG Developers Conference Copyright © 2004, PCI-SIG, All Rights Reserved 38

PCI Express Overview, Components &

Provides isolation of host memory domains

PCI Express Overview, Components &

PCI Express Overview, Components &

Connectivity, Bandwidth and Scalability

Combining multiple lanes in wider port Character5

Byte striping used for multiple lanes Character0

PCI Express Overview, Components &

PCI Express Overview, Components &

Mature Specification (1.0a)