[10/29, 7:33 PM] Ishita Dopeshwar: 4:1 Mux draw

What us process?

Sensitivity list? What can be used instead?

What technology is used?

What is lambda?

Why TG? Its advantages

[10/29, 7:33 PM] Ishita Dopeshwar: Types of power dissipation

Types of delays

Pmos cmos nmos 2d figures... (source drain wala...)

Fpga technologies...

Fpga manufacturers. ..

Cpld fpga difference. ..

Which one better...

[10/29, 7:33 PM] Ishita Dopeshwar: 1.types of delays

2.distinguish between cpld nd fpga

Which one will u prefer

3.draw p Mos

4.design rules

5.fpga design technologies

[10/29, 7:33 PM] Ishita Dopeshwar: Synthesizable and non Synthesizable statements examples

Write a 2:1 MUX code using if..else statement (just architecture)

Advantages of CMOS inverter over other inverters

[10/29, 7:33 PM] Ishita Dopeshwar: Vhdl library,packages,data types.

Body effect

Cmos implementation of nand,nor

4:1mux using transmission gate

Programming technologies
Modeling types

[10/29, 7:33 PM] Ishita Dopeshwar: Also . Just check if you get same rise and fall times for with sizing
and without sizing of NAND gate.

Coz according to external NAND gate la sizing karun kahich farak padat nahi.

[10/29, 7:33 PM] Ishita Dopeshwar: Why others is used in case statement??

Draw NOR gate

What is Body effect?

In NOR, pmos or nmos shows body effect?

In which region CMOS acts as switch?

Why n well is used?

What are the dots which we see on microwind screen?

What is lambda?

[10/29, 7:33 PM] Ishita Dopeshwar: 2:1 mux vhdl code using when else statement.

Cpld Nd fpga difference.

Why the currents of pmos and nmos should be same ?

What is the value of delta delay, ps or ns ? Ans - ns

Relation between pmos Nd nmos width.

How did I do the sizing calculations?

How many times is the pull up ckt of pull down ckt in cmos NAND implementation?

What is Body effect ?

[10/29, 7:34 PM] Ishita Dopeshwar: Butterworth LPF -- 1.Diff. between lpf & Butterworth lpf. 2.real
time applications of image enhancement . 3.Equations of D0 & H(u,v). 4. Code explanation.

[10/29, 7:34 PM] Ishita Dopeshwar: Prac- SRAM

Explain the working of sram.

Waveform me rising n falling time ko circle kiya and asked what that is.

Why width of PMOS greater than width of NMOS? Why should it be 2.5 only(as in case of inverter
with sizing)

What is the exact value of the mobility.

Why PMOS is pulled up and NMOS is pulled down.

What type of CMOS you have used. Enhancement or depletion. What is meant by enhancement and
depletion type.

Can you write the equations of the current in the 3 regions.

What is technology scaling.

[10/29, 7:34 PM] Ishita Dopeshwar: ALU:

Op ala ka,simulate neat kela ka

Cmos inverter

Concurrent n sequential statements

Case statement is seq or concurrent

How Nwell region forms

[10/29, 7:34 PM] Ishita Dopeshwar: Hot electron effect,body effect,static and dynamic power
dissipation

[10/29, 7:34 PM] Ishita Dopeshwar: Pract :CMOS Inverter 😎

VLSI (External)

Written:

Full forms:BIST,JTAG,FPGA,CPLD,VHDL,ASIC,SOC

Differences:

FPGA & CPLD

Anitfuse vs SRAM

Variable vs signal

Function vs Procedure

Questions on written points

Dynamic power dissipation equation & meaning

RTOS( Gongane mam)

Foreground/Background system

Priority Inversion (Diagram from labrosse)

Priority Inheritance

Ceiling protocol

Atomic & Nonatomic process

Critical section of code

Non-preemtive & Preemptive kernel : Response time, Latency

[10/29, 7:34 PM] Ishita Dopeshwar: exp-edge detection using sobel and prewitt

oral q.-what,why and how you performed...what is significance of gx,gy and gxy.....why to use edge
detection.....how the mask is applies to image.....& other q.are mentioned above

[10/29, 7:35 PM] Ishita Dopeshwar: Experiment - Bit plane slicing and Digital Negative😂

What did you do?

How did you do?

Why did you do?

What is radiant?

How to determine frequency of components in matrix?

Difference between dft, z-transform and laplace transform.

What is digital filtering and its significance?

[10/29, 7:35 PM] Ishita Dopeshwar: Expt:rgb 2hsi conversion

●how does parasitic capacitances affect the performance of the circuit

●effect of parasitic capacitances on delay ani power dissipation

●what will be the effect on parasitic capacitance if frequency is increased or decreased

●difference between function n procedure

●modelling styles and types of statements used..sequential concurrent n all that

●equalisation n normalisation

●what is stegnography..which techniques r used other than bit plane slicing

●difference between encryption n stegnography....which is better

●edges r having high frequency....explain mathematically

●how to detect lower frequency components in an image

●Did u get the results ( o/p)

[10/29, 7:35 PM] Ishita Dopeshwar: Physical significance of convolution, why we are using cmos,img
vr noise add kraycha matrix che coeff,moore law,diff btw cpp and vhdl,limitation of vhdl

[10/29, 7:35 PM] Ishita Dopeshwar: dip- morphology dilation, erosion

written questions-what is dilation ,erosion?, what's morphology ? list different operations in

morphology

oral- dilation kya hota hai ? kyu karte hai morphology?why can't we use filter instead?what is
erosion? why do we take SE as (111,111,111) ...(222,222,222) nahi chalega kya ....kyu multiply karte
hai SE se? multiply hota hai ki convolution hota hai? aaani...barach kahi...ye kyu kiya ,woh kyu kiya,
aise kyu kiya, waise kyu nahi kiya