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Lab1: Introduction to the Digital Workflow with

Synopsys and Cadence using AMS HIT-Kit

Tutorial not supported anymore! This tutorial was used until 2017. It is currently not used anymore. Refer to the _gpdk version of the
tutorial!
Author: Michael Nydegger (HuCE-microLab)

Digital Workflow
The following tutorial for the fully digital workflow on the AMS C35 0.35um process aims to give an insight into the principal workflow
and tools used in digital ASIC design. By the end of the tutorial you will obtain a full chip layout for a black jack player (FSMD) depicted
in the following image:

For this tutorial it is required to have a working VHDL description of the “Black Jack Player” introduced in the lecture slides
“System-on-Chip Design: Finite-State-Machine Data-Path Model” from Prof. Dr. Marcel Jacomet. The slides can be found on the
web-page of the bachelor module "System on Chip Design".

The following diagram gives a rough overview of the workflow presented in this tutorial (yellow elements are not covered by the
tutorial):

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RTL Description
In this step, the system architecture (e.g. sketched system) is described on RTL level (register transfer level) in a VHDL or Verilog
representation, capable of being synthesized into hardware. During the description, iterative testing should be performed by the use of
a test-bench (see course slides) which can be re-used in any step throughout the design.

Developing and coding the target system in VHDL is not part of this tutorial, the section only shows essential steps in using the Cadence
digital simulator NCSim for the design verification. If you're already familiar with ModelSim from MentorGraphics you can test and
develop your netlist with ModelSim and perform a second check with NCSim.

Synthesis
The RTL description is then synthesized and translated into a so-called gate-level netlist by a state-of-the-art synthesis tool (in this
tutorial: Synopsys Design Compiler). The gate-level netlist has the same logical behaviour and IO ports as the RTL description. In
contrast to the RTL behavioral description, the gate-level netlist consists exclusively of basic logic functions whose implementation
(layout) is provided by the design kit for the chip in form of a gate-level library (standard digital cells).

Implementation
Placing and routing the standard cells according to the gate-level netlist leads to the layout of the chip incorporating the described
system architecture.

The routing of standard cells introduces additional delays which will be added to the logic gate delays by loaded them into the design.
Thus, the initial netlist might needed to be altered by a re-designing time-critical blocs.

Verification
Prior to the tape-out (sending the design to the manufacturer), essential layout rule violation checks (DRC) and netlist tests (LVS) are
required to ensure the correct functionality of the final chip.

DRC (Design Rule Check) is a process in which the layout is checked for violations such as clearance between metal layers, minimal
width of tracks, and so forth.
LVS (Layout Versus Schematic) is used to ensure a proper representation of a schematic (netlist) by the given layout. For this, the
netlist of the layout level is extracted and compared to the given netlist of the schematic level.

This tutorial only covers DRC and LVS. Usually, designers may want to simulate the whole chip behavior in a “Full-Chip Simulation”
based on SPICE. Depending on the complexity of the chip, this simulation may run up to several weeks. It is a common practice to start
full-chip simulations right after tape-out. In this way, the simulation results are available for debugging of the final chip whereas the
critical path of the development process is not delayed by the simulation.

Tape-Out
In this last step (which doesn't belong to the ASIC development process), the final layout of the chip is stored in a layout file and
shipped to the manufacturer. In addition to the layout file, a bonding diagram may be required, if the designer wants to have the chips
bonded in a common IC package such as DIP.

Prepare the Working Directory

Create a working directory somewhere in your home directory (in the tutorial, ”~/Tutorial_DigitalWorkflow” is used):

mkdir Tutorial_DigitalWorkflow

To enter the working directory type:

cd ~/Tutorial_DigitalWorkflow

Now enter the tools environment by typing:

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icenv_ams35

After preparation of the working directory, you can proceed to the Lab2: RTL Description.

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