Component value

PGA870

ADS62P49IRGCT
 THS4509

DAC3283

CDCE72010
MAX4567

WBC1-1TL
 Recommended Layout construction

1. Signal routing should be direct and as short as possible into and out of the device input
and output pins.
Routing the signal path between layers using vias should be avoided if possible.
2. The device PowerPAD should be connected to a solid ground plane with multiple vias.
The PowerPAD must be connected to electrical ground.
3. Ground or power planes should be removed from directly under the amplifier output
pins.
4. A 0.1-μF capacitor should be placed between the VMIDpin and ground near to the pin.
5. An output resistor is recommended in each output lead, placed as near to the output
pins as possible.
6. Two 0.1-μF power-supply decoupling capacitors should be placed as near to the power-
supply pins as possible.
7. Two 10-μF power-supply decoupling capacitors should be placed within 1 in (2,54 cm) of
the device.
8. The digital control pins use CMOS logic levels for high and low signals, but can tolerate
being pulled high to a +5-V power supply. The digital control pins do not have internal pull-
up resistors.

Grounding: A single ground plane is sufficient to give good performance, provided the
analog, digital, and clock sections of the board are cleanly partitioned.
Supply Decoupling: As ADS62Px9/x8 already includes internal decoupling, minimal
external decoupling can be used without loss in performance. Note that decoupling
capacitors can help filter external power supply noise, so the optimum number of
capacitors would depend on the actual application. The decoupling capacitors should be
placed very close to the converter supply pins.
Exposed Pad: In addition to providing a path for heat dissipation, the pad is also
electrically connected to digital ground internally. So, it is necessary to solder the exposed
pad to the ground plane for best thermal and electrical performance.
 1. Signal routing should be direct and as short as possible into and out of the op amp
circuit.
2. The feedback path should be short and direct; avoid vias.
3. Ground or power planes should be removed from directly under the amplifier input and
output pins.
4. An output resistor is recommended on each output, as near to the output pin as
possible.
5. Two 10-μF and two 0.1-μF power-supply decoupling capacitors should be placed as near
to the power-supply pins as possible.
6. Two 0.1-μF capacitors should be placed between the CM input pins and ground. This
configuration limits noise coupled into the pins. One each should be placed to ground near
pin 4 and pin 9.
7. It is recommended to split the ground panel on layer 2 (L2) as shown below and to use a
solid ground on layer 3 (L3). A single-point connection should be used between each split
section on L2 and L3.
8. A single-point connection to ground on L2 is recommended for the input termination
resistors R1 and R2. This configuration should be applied to the input gain resistors if
termination is not used.

Thermal Informtion: This package incorporates an exposed thermal pad that is designed
to be attached directly to an external heatsink. The thermal pad must be soldered dirctly
to the PCB. Apter solderin, the PCB can be used as a heatsink. In addition, through the use
of thermal vias, the thermal pad can be attached directly to the appropriate copper plane
shown in the electrical schematic or attached to a special heatsink structure designed into
the PCB

The CDCE72010 is a high performance device packaged in a QFN-64. The die has all
the ground pins bounded to the thermal PAD on the bottom of the package. Therefore it is
essential that the connection from the thermal PAD to the ground layers should be low
impedance. In addition, the thermal path in a QFN package is via the thermal PAD on the
bottom of the package. Therefore, the layout of the PAD is very important and it will affect
the thermal performance as well as the overall performance of the device. The illustration
shown provides optimal performance in terms of thermal issues, inductance and power
supply bypassing. The 10 X 10 Filled VIA pattern recommended allows for a low inductance
connection between the thermal ground pad and the ground plane of the board. This
pattern forms a low thermal resistive path for the heat generated by the die to get
dissipated through the ground plane and to the exposed bottom side ground pad. It is
recommended that solder mask not be used on this bottom side pad to maximize its
effectiveness as a thermal heat sink. The recommended layout drives the thermal
conductivity to 22.8 C/W in still air and 13.8 C/W in a 100LFM air flow if implemented on a
JEDEC compliant test thermal board.
 IC sockets degrade high-frequency performance and should not be used if signal
bandwidth exceeds 5MHz. Surface-mount parts, having shorter internal lead frames,
provide the best high-frequency performance. Keep all bypass capacitors close to the
device, and separate all signal leads with ground planes. Such grounds tend to be wedge-
shaped as they get closer to the device. Use vias to connect the ground planes on each
side of the board, and place the vias in the apex of the wedge-shaped grounds that
separate signal leads. Logic-level signal lead placement is not critical.

1. Impedance ratio is for the full primary winding to the full secondary winding.
2. Inductance measured at 100 kHz, 0.1 V, 0 Adc on an Agilent/HP 4192 or
equivalent.
3. DCR measured on a micro-ohmmeter.4. DC imbalance is the maximum difference in
current measured at pins 1
and 3 with the source at pin 2. Inductance drop is 15% at maximum
imbalance.
5. Electrical specifications at 25°C.