USB 3.

0 – The Next-Generation Interconnect

By Ashwini Govindaraman, Product Marketing Manager, Cypress Semiconductor Corp., and Sonia Gandhi, Senior
Applications Engineer, Cypress Semiconductor Corp.

Introduction
When was the last time you got impatient with technology not being fast enough? Here is a situation: your flight from San
Francisco to New York takes off in 3 hours and you are ready to head to the airport, but you really want to catch up with the all
new season of your favorite series “House” which you missed. A friend just sent you a message on Facebook about how much
he enjoyed a blockbuster movie he watched last night and you wish you could watch it on the long flight you are about to get
on. If I were you, I would be wondering “if only I had the time to simply get all the content I need right now”. Today, it would
take about 14 minutes to transfer an HD movie of 25GB and almost 9 minutes to transfer a TV Show of 16GB from a PC to
your handheld media device. Thankfully, technological innovations are happening at a pace that enables users to get the
content they want a lot faster. One such evolution is that of the most universal and ubiquitous interface – USB. USB 3.0
SuperSpeed is here and promises to be the panacea to such situations.

In this age of internet and communication revolution, enormous amount of content is being generated, processed and
consumed at a staggering rate; and in parallel, mass storage technologies are also undergoing significant innovation. Storage
is becoming inexpensive and densities are increasing, driving content sharing. Users no longer worry about conserving hard
drive space. The life of a photographer is a lot easier with several storage cards to freely click as many pictures and swap
cards out when full. These usage models are becoming increasingly popular not just in the enterprise and professional
context, but also in the consumer arena. Still cameras and camcorders are evolving towards higher resolution and better
quality pictures, creating a need for a faster interconnect to be able to consume the content. So strong is the need for
something faster, that several technology leaders have come together to solve this problem in an elegant and seamless
manner. The USB Implementers Forum recognized this urgent need for the next-generation interconnect technology and
officially ratified the USB 3.0 specification in November 2008.

History of USB
USB is by far the most successful interconnect defined and is broadly adopted in consumer electronics and PC peripherals.
Over 2.8 billion USB devices were shipped in 2008, and this number keeps growing exponentially. USB 2.0 specification was
released in 2000 and is now a mature interconnect that users are accustomed to. USB 3.0 is the next revolution of USB
technology. The primary goal of USB 3.0 is to keep the same ease of use, flexibility and hot-plug functionality but at a much
higher data rate. Another major goal of USB 3.0 is the power management. This is very important for “Sync & Go” applications
that need to tradeoff features for battery life.

USB 3.0 chipsets are expected to begin shipping in 2009, and broad deployment is expected in 2011. PCI Express (PCIe)
add-on cards and discrete host controller based PCs are being demonstrated at major industry events this year. USB 3.0
heralds an all new wave of application usage models and is expected to deliver actual throughput of over 3Gb/s (raw signaling
speed of 5Gb/s), which is over 10 times higher than that of Hi-Speed USB. USB 3.0 will be targeted initially at the PC market
and in devices requiring high rates and volumes of data transfer, such as external storage, consumer electronics, and
communications devices with increasing amounts of storage.

In this article, we will focus on the evolution of USB 3.0 from USB 2.0, with emphasis on the key advancements of USB 3.0
from earlier generations. We will also delve into some of the key aspects of the USB 3.0 specification that are relevant to end
users and developers, and review some of the advantages of USB 3.0 compared to other interfaces.

From Hi-Speed to SuperSpeed

The USB 3.0 interface consists of a physical SuperSpeed bus in addition to the physical USB 2.0 bus. The USB 3.0 standard
defines a dual simplex signaling mechanism at a rate of 5 Gb/s. This enables simultaneous transfer of data to and from the
device as opposed to the single duplex unidirectional USB 2.0 bus. The USB 3.0 bus architecture is designed to be electrically

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and mechanically backward compatible with USB 2.0, such that a USB 3.0 host would communicate with a device at the
fastest signaling rate supported by the device. Conversely, a USB 3.0 compliant device when plugged into a USB 2.0 host
would seamlessly function at the USB 2.0 signaling rate.

In addition to a 10x faster signaling rate than USB 2.0, USB 3.0 supports a significantly more efficient transfer model. For
instance, asynchronous notifications replace the polling model of USB 2.0. As an example, when the USB 3.0 host initiates a
transaction the device may respond with a Not Ready (NRDY) if data or buffer space is not available. Later, when the device is
able to honor the request, it will report an Endpoint Ready (ERDY) status to the host.

A USB 2.0 host broadcasts packets to all enabled downstream devices, forcing all devices to decode the address received
with every packet. In contrast, a USB 3.0 host unicasts packets only to the target device. This is achieved by embedding
routing information in transmitted packets, which is decoded by an intermediating hub. This model of unicast packets allows
inactive devices to remain in a low power state, and is just one of the several power saving techniques implemented by USB
3.0.

The USB 3.0 specification allows devices to draw up to 900mA when attached to a host, significantly higher than the 500mA
limit set by USB 2.0.

Table 1. Key differences between USB 2.0 and USB 3.0

Attribute USB 2.0 USB 3.0

Raw Data - 480Mbps (Hi-Speed) 5.0 Gbps (SuperSpeed)

Rate - 12MBps (Full-Speed)
- 1.5Mbps (Low-Speed)

Data Interface - Half-Duplex - Dual-Simplex

- Two Wire Differential Signaling - Four Wire Differential Signaling

Signal Count 4 signals: 8 Signals:

- 2 for USB 2.0 Data (D+,D-) - 4 for Superspeed Data

- 2 for VBUS and GND (SSRX+,SSRX, SSTX+, SSTX-)

- 2 for USB 2.0 Data (D+,D-)

- 2 for VBUS and GND
Transaction - Host directed - Host Directed
Protocol - Polled traffic flow - Asynchronous notifications
- Packets broadcast to all downstream - Packets routed only to target device
devices - Multiple data Streams possible for Bulk
- No multiplexing of data Streams transfers
Power Modes 2 Modes 4 Modes

- Active - Active (U0)

- Suspend - Idle, Fast Exit (U1)
- Idle, Slow Exit (U2)
- Suspend, Slow Exit (U3)
Current Draw - 100mA (max) for low power & un- - 150mA (max) for low power & un-configured
from VBUS configured devices devices
- 500mA (max) for high power devices - 900mA (max) for high power devices

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USB 3.0 Architecture:
USB 3.0 architecture is inspired by the layered PCIe architecture and the OSI model. As seen in Figure 1, USB 3.0 has a
physical layer, link layer and protocol later. The physical layer includes the PHY and the connection between a host and a
device or a hub and a device. Similar to the PCIe PHY, the USB 3.0 PHY includes 8b/10b encoding/ decoding, data
scrambling and descrambling, and serializing and deserializing functions. The link layer maintains link connectivity and
ensures data integrity between link partners by implementing error detection. Packets are created in the link layer and link
commands are issued. The protocol layer manages end to end data flow between a device and a host.

Like USB 2.0, the SuperSpeed bus carries data, address, status and control information. Four packet types are defined – two
of them, Transaction Packet (TP) and Data Packet (DP) remain the same as in USB 2.0. Two additional packet types –
Isochronous Timestamp Packet (ITP) and Link Management Packet (LMP) are newly introduced by USB 3.0.

Host Device
D+

D-

PHY
SIE
USB2.0
VBUS
Signals
GND
USB3.0

PROTOCOL
Additional SSTX+/-
Signals

LINK
PHY
SSRX+/-

Figure 1: USB 3.0 Electrical Interface and Layered Architecture

USB 3.0 Power Management

The USB 3.0 specification provides enhanced power management capabilities to address the needs of battery powered
portable applications.

Two “Idle” modes (denoted as U1 and U2) are defined in addition to the “Suspend” mode (denoted as U3) of the USB 2.0
standard. The U2 state provides higher power savings than U1 by allowing more analog circuitry (such as clock generation
circuits) to be quiesced. This results in a longer transition time from U2 to active state. The Suspend state (U3) consumes the
least power and again requires a longer time to wakeup.

The Idle modes may be entered due to inactivity on a downstream port for a programmable period of time or may be initiated
by the device, based on scheduling information received from the host. Such information is indicated by the host to the device
using the flags “Packet pending”, “End of burst” and “Last packet”. Based on these flags, the device may decide to enter an
Idle mode without having to wait for inactivity on the bus.

When a link is in one of the Idle states described above, communication may take place via Low Frequency Period Signaling
(LFPS), which consumes significantly lower power than SuperSpeed signaling. In fact the Idle mode is exited with an LFPS
transmission from either host or device.

The USB 3.0 standard also introduces the “Function Suspend” feature which enables power management of individual
functions of a composite device. This provides the flexibility of suspending certain functions of a composite device, while other
functions remain active.

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Additional power savings are achieved via a Latency Tolerance Messaging (LTM) mechanism implemented by USB 3.0. A
device may inform the host of the maximum delay it can tolerate from the time it reports an ERDY status to the time it receives
a response. The host may factor in this latency tolerance to manage system power.

Thus power efficiency is embedded into all levels of a USB 3.0 system, including the link layer, protocol layer and PHY layer.

Figure 2 shows a comparison of system power consumed during a SuperSpeed and a Hi-Speed data transfer. A USB 3.0
system requires more power while active, but due to its higher data rate and various power efficiency features, it remains
active for shorter periods. A SuperSpeed data transfer could cost up to 50% less power than a Hi-Speed transfer. This is
crucial to the battery life of mobile handset devices such as cellular phones.

PSS-ACTIVE
PHS-ACTIVE
System Power

PIDLE

Time

PIDLE – System Power when no data transfer taking place

PSS-ACTIVE – System power in Super Speed Mode
PHS-ACTIVE – System Power in High Speed Mode

Figure 2. System Power Consumption during SuperSpeed and Hi-Speed Data Transfers (Source: USB 3.0
Specification, Rev 1.0)

Streams and Mass Storage Access

The SuperSpeed raw data rate is supported by a new model of “Streams”. Multiple buffers of data may be set up and
organized as Streams to a single bulk endpoint. Up to 64k Streams may be multiplexed per endpoint. Streams are available on
both IN and OUT endpoints and each Stream is tagged with a Stream ID. Both the host and the device have the ability to
establish the “Current Stream” associated with an endpoint. The host or device may also truncate a Stream when necessary.
Figure 3 depicts an IN transfer using Streams.

Streams make it possible to realize an out of order execution model required for command queuing . Currently, the USB Mass
Storage Class (MSC) standard is the protocol of choice to communicate with storage devices.

However, the MSC protocol imposes certain limitations such as an MSC host being able to issue only one command at a time
and frequent intervention required by the host and device during command processing. These inherent restrictions lead to
significant bottlenecks in MSC transfers; they limit throughput in current USB 2.0 systems and would severely impair
throughput in future USB3.0 systems. The concept of Streams would enable more powerful mass storage protocols. A typical
communication link would consist of a command OUT pipe, an IN and OUT pipe (with multiple data streams) and a status
pipe. The host would be able to queue commands, i.e. issue a new command without waiting for completion of a prior one,
tagging each command with a Stream ID.

Thus Streams would be essential to alleviate the bottlenecks of MSC.

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 Figure 3. USB 3.0 IN transfer using Streams

Comparison with other Interfaces

Several other serial communication standards boast a data rate similar to that of USB 3.0. For example, PCIe Gen 2.0 has a
data rate of 5Gbps and Serial ATA (SATA) III has a data rate of 6Gbps.

Although the USB 3.0 PHY architecture is inspired from PCIe, several key distinctions exit. The USB 3.0 PHY must implement
an equalizer required to compensate for cable loss. This allows USB cables to be as long as three meters. The PCIe and
SATA PHYs do not have such an equalizer. The LFPS feature described earlier is also unique to the USB 3.0 PHY.

A PCIe link may consist of multiple lanes (i.e. pairs of transmit and receive differential lines) to increase bandwidth, whereas a
USB 3.0 link supports only a single lane.

Of these three interfaces, true plug and play is enabled only by USB. The SATA standard does support hot-plug, but
contingent on the SATA controller functioning in Advanced Host Controller Interface (AHCI) mode.

PCIe is typically used to connect peripheral function cards (such as graphic cards) directly onto the motherboard of a PC.
SATA is an interface of choice for mass storage devices such as hard disk drives and optical drives; hence most PCs integrate
a SATA host adapter. USB on the other hand serves as a general purpose SuperSpeed or Hi-Speed bridge between a host
and virtually any interface.

USB 3.0 also lends itself well to be an alternative interface for transferring video given the increased bandwidth. This could
herald some interesting applications in the digital living room – including TV, STB, monitors and gaming consoles. The key
advantage of USB versus video interfaces like VGA, DVI, DisplayPort and HDMI is the ubiquity of the interface. With HDCP
2.0 including USB as one of the interfaces, content protection can also be enabled by USB 3.0. Another benefit is the fact that
USB is royalty free.

USB Charging
Charging is a key feature that stands out when comparing USB to other interfaces. USB is now the charging interface of
choice in several countries. Charging over USB has inherent benefits compared to having discrete chargers for every device.

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Not only does it lower manufacturing cost by limiting vendor specific chargers, but also has significant impact on the
environment in the long run.

USB 3.0 hosts and hubs enable the battery charging schemes as defined by the USB Battery Charging Specification.

The USB Battery Charging Specification currently defines three types of usage modes for charging –

1. Host Charger – A host charger is a USB 2.0 host that provides up to 500mA to a downstream port and implements
charger detection. A Hi-Speed device may draw only up to 900mA from the host charger.
2. Hub Charger – A hub charger is a USB 2.0 hub that provides up to 500mA to a downstream port and supports charger
detection. The charging functionality is very similar to a host charger.
3. Dedicated Charger – A dedicated charger provides power over USB interface but does not enumerate the device. The
charging current is limited to 1.5A
The specification also provides for dead battery charging, allowing a dead or very weak battery to draw up to 100mA from a
host of hub until it is charged to a reasonable threshold.

The distinct advantage of being able to charge over USB will continue to be leveraged in USB 3.0 systems.

Conclusion:
USB 3.0 is anticipated to be the ubiquitous solution for many bandwidth hungry applications. Its evolution from the highly
successful USB 2.0 is fueled by increasing multimedia consumption demands and higher density storage technologies. USB
3.0 is definitely a technology trigger in the hype cycle, and will have to show that it can make it through the peak of inflated
expectations leading into mass market adoption. The day is fast approaching when you can get all the content you want on
your way to the airport, in less than a minute.

Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone: 408-943-2600
Fax: 408-943-4730
http://www.cypress.com

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