Timing

--------------------------------------------------------------------------------
13.2
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Design file:
C:\Users\Umar\Dropbox\ECE545_F11\Assignments\HW4\VHDL_v4\HW4_ISE_v4\hw4_proj\exam_t
op.ncd
Physical constraint file:
C:\Users\Umar\Dropbox\ECE545_F11\Assignments\HW4\VHDL_v4\HW4_ISE_v4\hw4_proj\exam_t
op.pcf
Device,package,speed: xc3s50,pq208,-5 (PRODUCTION 1.39 2011-06-20)
Report level: verbose report
unconstrained path report, limited to 1 item
Environment Variable Effect

-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2700 - Timing constraints ignored because advanced analysis with

offsets was specified.
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
================================================================================
Timing constraint: Default period analysis for net "clk_BUFGP"
1288 paths analyzed, 268 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 5.481ns.
--------------------------------------------------------------------------------
Delay (setup path): 5.481ns (data path - clock path skew + uncertainty)
Source: datapath_instance/iter_loop/reg_gen[3].reg_0/dout_2 (FF)
Destination: datapath_instance/iter_loop/reg_gen[3].reg_0/dout_4 (FF)
Data Path Delay: 5.481ns (Levels of Logic = 3)
Clock Path Skew: 0.000ns
Source Clock: clk_BUFGP rising
Destination Clock: clk_BUFGP rising
Clock Uncertainty: 0.000ns
Maximum Data Path: datapath_instance/iter_loop/reg_gen[3].reg_0/dout_2 to

datapath_instance/iter_loop/reg_gen[3].reg_0/dout_4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X17Y6.XQ Tcko 0.626
datapath_instance/iter_loop/reg_gen[3].reg_0/dout<2>
SLICE_X19Y6.G1 net (fanout=9) 0.638
SLICE_X19Y6.Y Tilo 0.479 N81
datapath_instance/iter_loop/ROM_gen[3].ROM_0/Mrom_dout_rom000031
SLICE_X6Y9.F4 net (fanout=6) 1.549
SLICE_X6Y9.X Tilo 0.529
datapath_instance/iter_loop/mux_shift<0><6>
datapath_instance/iter_loop/mux_shift_0_mux0000<6>1
SLICE_X18Y4.CLK Tfck 0.914
datapath_instance/iter_loop/a_in_3_mux0000<4>_G
datapath_instance/iter_loop/a_in_3_mux0000<4>
------------------------------------------------- ---------------------------
Total 5.481ns (2.548ns logic, 2.933ns

route)
(46.5% logic, 53.5% route)
--------------------------------------------------------------------------------

Logical Resource(s)
------------------------------------------------- -------------------
------------------------------------------------- ---------------------------
route)
(47.3% logic, 52.7% route)
--------------------------------------------------------------------------------

Logical Resource(s)
------------------------------------------------- -------------------
------------------------------------------------- ---------------------------

route)
(48.0% logic, 52.0% route)
--------------------------------------------------------------------------------
Hold Paths: Default period analysis for net "clk_BUFGP"
--------------------------------------------------------------------------------
Delay (hold path): 0.831ns (datapath - clock path skew - uncertainty)
Minimum Data Path: datapath_instance/iter_loop/reg_gen[4].reg_0/dout_5 to

Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X9Y9.CLK Tckg (-Th) -0.053
datapath_instance/iter_loop/k_in<6>1
------------------------------------------------- ---------------------------

route)
(66.7% logic, 33.3% route)
--------------------------------------------------------------------------------
Source: datapath_instance/counter_i/count_3 (FF)
Destination: datapath_instance/counter_i/count_3 (FF)
Minimum Data Path: datapath_instance/counter_i/count_3 to

datapath_instance/counter_i/count_3
Logical Resource(s)
------------------------------------------------- -------------------
datapath_instance/counter_i/count<3>
SLICE_X7Y3.CLK Tckf (-Th) -0.053
datapath_instance/counter_i/Mcount_count_xor<3>11
------------------------------------------------- ---------------------------

route)
(66.6% logic, 33.4% route)
--------------------------------------------------------------------------------
Clock Path Skew: -0.002ns (0.138 - 0.140)
Minimum Data Path: datapath_instance/iter_loop/reg_gen[4].reg_0/dout_4 to

Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X9Y8.YQ Tcko 0.501
------------------------------------------------- ---------------------------

route)
(74.4% logic, 25.6% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: Default OFFSET IN BEFORE analysis for clock "clk_BUFGP"
0 timing errors detected.
Minimum allowable offset is 4.292ns.
--------------------------------------------------------------------------------
Offset (setup paths): 4.292ns (data path - clock path + uncertainty)
Source: src_ready (PAD)
Clock Path Delay: 1.334ns (Levels of Logic = 2)
Maximum Data Path: src_ready to

Logical Resource(s)
------------------------------------------------- -------------------
P107.I Tiopi 0.722 src_ready
src_ready
src_ready_IBUF
SLICE_X12Y2.F2 net (fanout=10) 1.987 src_ready_IBUF
controller_instance/en0_or00001
SLICE_X21Y5.CE net (fanout=7) 1.864 en0
SLICE_X21Y5.CLK Tceck 0.524
------------------------------------------------- ---------------------------

route)
(31.5% logic, 68.5% route)
Minimum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_3

Logical Resource(s)
------------------------------------------------- -------------------
P79.I Tiopi 0.578 clk
clk
clk_BUFGP/IBUFG
BUFGMUX0.I0 net (fanout=1) 0.001 clk_BUFGP/IBUFG
BUFGMUX0.O Tgi0o 0.286 clk_BUFGP/BUFG
clk_BUFGP/BUFG.GCLKMUX
clk_BUFGP/BUFG
SLICE_X21Y5.CLK net (fanout=40) 0.469 clk_BUFGP
------------------------------------------------- ---------------------------

route)
(64.8% logic, 35.2% route)
--------------------------------------------------------------------------------

Logical Resource(s)
------------------------------------------------- -------------------
src_ready
src_ready_IBUF
------------------------------------------------- ---------------------------

route)
(33.3% logic, 66.7% route)

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(65.8% logic, 34.2% route)
--------------------------------------------------------------------------------

Logical Resource(s)
------------------------------------------------- -------------------
src_ready
src_ready_IBUF
------------------------------------------------- ---------------------------

route)
(33.3% logic, 66.7% route)

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(65.8% logic, 34.2% route)
--------------------------------------------------------------------------------
Hold Paths: Default OFFSET IN BEFORE analysis for clock "clk_BUFGP"
--------------------------------------------------------------------------------
Offset (hold paths): -0.860ns (data path - clock path + uncertainty)
Source: last_block (PAD)
Destination: datapath_instance/Last_block_gen/output (FF)
Minimum Data Path: last_block to datapath_instance/Last_block_gen/output

Logical Resource(s)
------------------------------------------------- -------------------
P78.I Tiopi 0.578 last_block
last_block
last_block_IBUF
SLICE_X11Y3.BY net (fanout=1) 0.436 last_block_IBUF
SLICE_X11Y3.CLK Tckdi (-Th) 0.205
datapath_instance/Last_block_gen/output
datapath_instance/Last_block_gen/output
------------------------------------------------- ---------------------------

route)
(46.1% logic, 53.9% route)
Maximum Clock Path: clk to datapath_instance/Last_block_gen/output

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(64.6% logic, 35.4% route)
--------------------------------------------------------------------------------
Destination: controller_instance/y_FSM_FFd2 (FF)
Minimum Data Path: src_ready to controller_instance/y_FSM_FFd2

Logical Resource(s)
------------------------------------------------- -------------------
src_ready
src_ready_IBUF
controller_instance/y_FSM_FFd2
controller_instance/y_FSM_FFd2-In1
controller_instance/y_FSM_FFd2-In_f5
------------------------------------------------- ---------------------------

route)
(61.5% logic, 38.5% route)
Maximum Clock Path: clk to controller_instance/y_FSM_FFd2

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(64.8% logic, 35.2% route)
--------------------------------------------------------------------------------
Minimum Data Path: src_ready to controller_instance/y_FSM_FFd2

Logical Resource(s)
------------------------------------------------- -------------------
src_ready
src_ready_IBUF
SLICE_X18Y3.G3 net (fanout=10) 0.591 src_ready_IBUF
SLICE_X18Y3.CLK Tckg (-Th) -0.344
controller_instance/y_FSM_FFd2-In2
controller_instance/y_FSM_FFd2-In_f5
------------------------------------------------- ---------------------------

route)
(60.9% logic, 39.1% route)

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(64.8% logic, 35.2% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: Default OFFSET OUT AFTER analysis for clock "clk_BUFGP"
0 timing errors detected.
Maximum allowable offset is 8.684ns.
--------------------------------------------------------------------------------
Offset (slowest paths): 8.684ns (clock path + data path + uncertainty)
Source: controller_instance/y_FSM_FFd2 (FF)
Destination: src_read (PAD)

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(64.8% logic, 35.2% route)
Maximum Data Path: controller_instance/y_FSM_FFd2 to src_read

Logical Resource(s)
------------------------------------------------- -------------------
controller_instance/sel0_and00001
P94.O1 net (fanout=12) 0.699 El
P94.PAD Tioop 4.463 src_read
src_read_OBUF
src_read
------------------------------------------------- ---------------------------

route)
(79.3% logic, 20.7% route)
--------------------------------------------------------------------------------
Destination: y<3> (PAD)
Maximum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_3

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(66.1% logic, 33.9% route)
Maximum Data Path: datapath_instance/iter_loop/reg_gen[0].reg_0/dout_3 to y<3>

Logical Resource(s)
------------------------------------------------- -------------------
P81.O1 net (fanout=6) 1.374
P81.PAD Tioop 4.463 y<3>
y_3_OBUF
y<3>
------------------------------------------------- ---------------------------

route)
(78.7% logic, 21.3% route)
--------------------------------------------------------------------------------
Maximum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_2

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(64.6% logic, 35.4% route)
Maximum Data Path: datapath_instance/iter_loop/reg_gen[0].reg_0/dout_2 to y<2>

Logical Resource(s)
------------------------------------------------- -------------------
P111.O1 net (fanout=7) 1.044
y_2_OBUF
y<2>
------------------------------------------------- ---------------------------

route)
(83.0% logic, 17.0% route)
--------------------------------------------------------------------------------
Fastest Paths: Default OFFSET OUT AFTER analysis for clock "clk_BUFGP"
--------------------------------------------------------------------------------
Offset (fastest paths): 6.176ns (clock path + data path - uncertainty)

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(65.8% logic, 34.2% route)
Minimum Data Path: datapath_instance/iter_loop/reg_gen[0].reg_0/dout_7 to y<7>

Logical Resource(s)
------------------------------------------------- -------------------
P116.O1 net (fanout=2) 0.287
y_7_OBUF
y<7>
------------------------------------------------- ---------------------------

route)
(94.1% logic, 5.9% route)
--------------------------------------------------------------------------------

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(65.8% logic, 34.2% route)

Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X22Y6.YQ Tcko 0.501
P117.O1 net (fanout=3) 0.306
y_6_OBUF
y<6>
------------------------------------------------- ---------------------------

route)
--------------------------------------------------------------------------------

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(63.8% logic, 36.2% route)

Logical Resource(s)
------------------------------------------------- -------------------
P113.O1 net (fanout=3) 0.287
y_4_OBUF
y<4>
------------------------------------------------- ---------------------------

route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: Default path analysis
0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 6.930ns.
--------------------------------------------------------------------------------
Delay (setup path): 6.930ns (data path)
Destination: src_read (PAD)
Maximum Data Path: src_ready to src_read

Logical Resource(s)
------------------------------------------------- -------------------
src_ready
src_ready_IBUF
SLICE_X23Y2.G1 net (fanout=10) 0.567 src_ready_IBUF
controller_instance/sel0_and00001
P94.O1 net (fanout=12) 0.699 El
P94.PAD Tioop 4.463 src_read
src_read_OBUF
src_read
------------------------------------------------- ---------------------------

route)
(81.7% logic, 18.3% route)
--------------------------------------------------------------------------------
Source: clk (PAD)
Destination: datapath_instance/counter_j/count_1 (FF)
Maximum Data Path: clk to datapath_instance/counter_j/count_1

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(64.4% logic, 35.6% route)
--------------------------------------------------------------------------------
Source: clk (PAD)
Maximum Data Path: clk to controller_instance/y_FSM_FFd1

Logical Resource(s)
------------------------------------------------- -------------------
clk
clk_BUFGP/IBUFG
clk_BUFGP/BUFG
------------------------------------------------- ---------------------------

route)
(64.4% logic, 35.6% route)
--------------------------------------------------------------------------------
All constraints were met.
Data Sheet report:

-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk

------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
last_block | 0.128(R)| 0.861(R)|clk_BUFGP | 0.000|
m<0> | 1.126(R)| 0.055(R)|clk_BUFGP | 0.000|
m<1> | 1.481(R)| -0.229(R)|clk_BUFGP | 0.000|
m<2> | 2.083(R)| -0.087(R)|clk_BUFGP | 0.000|
m<3> | 1.524(R)| -0.267(R)|clk_BUFGP | 0.000|
m<4> | 1.938(R)| -0.382(R)|clk_BUFGP | 0.000|
m<5> | 2.428(R)| -0.459(R)|clk_BUFGP | 0.000|
m<6> | 1.651(R)| -0.088(R)|clk_BUFGP | 0.000|
m<7> | 2.865(R)| -0.518(R)|clk_BUFGP | 0.000|
src_ready | 4.292(R)| 0.166(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad

------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
src_read | 8.684(R)|clk_BUFGP | 0.000|
y<0> | 7.707(R)|clk_BUFGP | 0.000|
y<1> | 7.780(R)|clk_BUFGP | 0.000|
y<2> | 7.804(R)|clk_BUFGP | 0.000|
y<3> | 8.095(R)|clk_BUFGP | 0.000|
y<4> | 7.104(R)|clk_BUFGP | 0.000|
y<5> | 7.403(R)|clk_BUFGP | 0.000|
y<6> | 7.078(R)|clk_BUFGP | 0.000|
y<7> | 7.055(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk

---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 5.481| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
src_ready |src_read | 6.930|
---------------+---------------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 1391 paths, 0 nets, and 639 connections
Design statistics:
Minimum period: 5.481ns{1} (Maximum frequency: 182.448MHz)
Maximum combinational path delay: 6.930ns
Minimum input required time before clock: 4.292ns
Maximum output delay after clock: 8.684ns
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Fri Dec 30 08:27:00 2011

--------------------------------------------------------------------------------
Timing Analyzer Settings:

-------------------------
Timing Analyzer Settings
analysis_name "Analysis 9"

analysis_type "auto-generated timing constraints"
analysis_speed -5
analysis_voltage 1.140000
analysis_temperature 85.000000
analyze_unconstrained_paths true
analzye_component_switching_limits true
report_datasheet true
report_timegroups false
report_constraints_interaction false
paths_per_constraint 3
Peak Memory Usage: 690 MB

Timing

Hochgeladen von

Dokumentinformationen

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Timing

Hochgeladen von

Copyright:

Verfügbare Formate

--------------------------------------------------------------------------------

Environment Variable Effect

INFO:Timing:2700 - Timing constraints ignored because advanced analysis with

Maximum Data Path: datapath_instance/iter_loop/reg_gen[3].reg_0/dout_2 to

Total 5.481ns (2.548ns logic, 2.933ns

Maximum Data Path: datapath_instance/iter_loop/reg_gen[3].reg_0/dout_0 to

Maximum Data Path: datapath_instance/iter_loop/reg_gen[3].reg_0/dout_1 to

Total 5.311ns (2.548ns logic, 2.763ns

Hold Paths: Default period analysis for net "clk_BUFGP"

Minimum Data Path: datapath_instance/iter_loop/reg_gen[4].reg_0/dout_5 to

Total 0.831ns (0.554ns logic, 0.277ns

Minimum Data Path: datapath_instance/counter_i/count_3 to

Total 0.832ns (0.554ns logic, 0.278ns

Minimum Data Path: datapath_instance/iter_loop/reg_gen[4].reg_0/dout_4 to

Total 1.082ns (0.805ns logic, 0.277ns

Maximum Data Path: src_ready to

Total 5.626ns (1.775ns logic, 3.851ns

Minimum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_3

Total 1.334ns (0.864ns logic, 0.470ns

Maximum Data Path: src_ready to

Total 5.335ns (1.775ns logic, 3.560ns

Minimum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_6

Total 1.313ns (0.864ns logic, 0.449ns

Maximum Data Path: src_ready to

Total 5.335ns (1.775ns logic, 3.560ns

Minimum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_7

Total 1.313ns (0.864ns logic, 0.449ns

Hold Paths: Default OFFSET IN BEFORE analysis for clock "clk_BUFGP"

Minimum Data Path: last_block to datapath_instance/Last_block_gen/output

Total 0.809ns (0.373ns logic, 0.436ns

Maximum Clock Path: clk to datapath_instance/Last_block_gen/output

Total 1.670ns (1.079ns logic, 0.591ns

Minimum Data Path: src_ready to controller_instance/y_FSM_FFd2

Total 1.499ns (0.922ns logic, 0.577ns

Maximum Clock Path: clk to controller_instance/y_FSM_FFd2

Total 1.665ns (1.079ns logic, 0.586ns

Minimum Data Path: src_ready to controller_instance/y_FSM_FFd2

Total 1.513ns (0.922ns logic, 0.591ns

Maximum Clock Path: clk to controller_instance/y_FSM_FFd2

Total 1.665ns (1.079ns logic, 0.586ns

Maximum Clock Path: clk to controller_instance/y_FSM_FFd2

Total 1.665ns (1.079ns logic, 0.586ns

Maximum Data Path: controller_instance/y_FSM_FFd2 to src_read

Total 7.019ns (5.568ns logic, 1.451ns

Maximum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_3

Total 1.632ns (1.079ns logic, 0.553ns

Maximum Data Path: datapath_instance/iter_loop/reg_gen[0].reg_0/dout_3 to y<3>

Total 6.463ns (5.089ns logic, 1.374ns

Maximum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_2

Total 1.671ns (1.079ns logic, 0.592ns

Maximum Data Path: datapath_instance/iter_loop/reg_gen[0].reg_0/dout_2 to y<2>

Total 6.133ns (5.089ns logic, 1.044ns

Minimum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_7

Total 1.313ns (0.864ns logic, 0.449ns

Minimum Data Path: datapath_instance/iter_loop/reg_gen[0].reg_0/dout_7 to y<7>

Total 4.863ns (4.576ns logic, 0.287ns

Minimum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_6

Total 1.313ns (0.864ns logic, 0.449ns

Minimum Data Path: datapath_instance/iter_loop/reg_gen[0].reg_0/dout_6 to y<6>

Total 4.882ns (4.576ns logic, 0.306ns

Minimum Clock Path: clk to datapath_instance/iter_loop/reg_gen[0].reg_0/dout_4

Total 1.354ns (0.864ns logic, 0.490ns

Minimum Data Path: datapath_instance/iter_loop/reg_gen[0].reg_0/dout_4 to y<4>