ANALOG VLSI NTUA COURSE 1

3.3V Fully Differential CMOS Operational

Amplifier
Konstantinos Kailas, National Technical University of Athens, School of Electrical and Computer Engineering,
kwstkailas@gmail.com

Abstract—This paper presents the design of a two stage 3.3V
fully differential operational amplifier in CMOS technology. The
achieved implementation delivers a DC gain over 85 dB with
unity gain frequency around 40 MHz and a fast large-signal step
response with a 0.1% settling time below 40 ns.
I. I NTRODUCTION
MOS operational amplifiers are one of the most im-
C portant blocks of modern integrated circuits design.
Being used in a variety of applications, the improvement of
their overall perfomance and specifications is paramount
in today’s scientific research and development.
We focus on the design of a CMOS operational am-
plifier. We resort to the classic two stage design model,
with the first stage providing hign gain and the second,
large swings. Thus, the folded cascode fully differential
topology is selected for the first stage followed by a sim-
ple common source output stage which completes the
basic design. Two continuous common mode feedback
networks provide the required voltage levels of the two
blocks mentioned above while all the required bias volt-
ages and currents are produced by a basic constant-
transconductance cell. In Table I. the proposed specifica-
tions for the realization are presented.
The rest of the paper is as follows: In Section II, the
complete opamp design is analyzed while Section III de-
tails the results that have been derived from the simulation.
Finally, a summary and an evaluation of the achieved
results are presented in Section IV.
II. T HE O PERATIONAL A MPLIFIER
A. The Folded−Cascode Core
The opamp’s first stage topology is illustrated in Fig. 1. It
consists of a P-channel input differential pair formed by M1
and M2 . The transistor M0 , acts as a tail current source,
and provides the sufficient current for M1 −M2 to operate.
The block of M7 −M10 forms P-channel cascode sources,
which are matched by their complementary M3 −M6 N-
channel transistors with M3 and M4 behaving as the
current sinks for the total bias current. Taking advantage
of the cascode setting at the output, we obtain a high
2
impedance at this node (in the order of gm rds ), acquiring
in this way a reasonable gain. The total gain of the first
stage then is given as:
Gma Rout
A= (1)
1 + sRout Cout
For mid-band and high frequencies the previous formula
can be simplified to:
Gma
A= (2)
sCout
where Gma = gm1 = gm2 , since M1 & M2 share the tail
current and have the same (W/L) ratios.

TABLE I
P ROPOSED S PECIFICATIONS

Parameter Proposed value

Power Supply Voltage +3.3 V (single)
Small-Signal DC Gain >70 dB
Unity-Gain Frequency >20 MHz
Phase Margin > 60◦
Gain Margin > 8 dB
Input Common−Mode Voltage Swing 0.8 V - 2.2 V
Swing Per Output 0.5 V - 2.5 V
DC Input−Output Function monotonic Fig. 1. The Folded Cascode Core
Settling Time to (0.1% Error) < 40ns (1pFk20kΩ load)
Current Consumption Minimum possible The selection of the pMOS topology allows us to sur-
CMRR (Single-Ended) > 50 dB (0 to 100kHz) pass the proposed lower limit, reaching the lowest possi-
PSRR (Single-Ended) > 50 dB (0 to 100kHz) ble voltage level. Achieving the upper limit of the proposed
Technology NCSU ami06 common mode voltage range requires the transistor M0
to operate at the minimum possible Vef f while M1 and
ANALOG VLSI NTUA COURSE 2

TABLE II In contrast to Miller compensation, where an additional

T RANSISTOR S IZING & B IAS VOLTAGES signal path between the two outputs is created though
Transistor W/L (µm) Bias Voltages Obtained Value
an RC network, in this case the compensation current
M0 1000.05/1.2 Vbias0 2.341 V is fed back to a low impedance internal node of the first
M1 -M2 315/1.2 Vbias1 0.973 V stage. By avoiding connecting the compensation capacitor
M3 -M6 150/1.2 Vbias2 1.533 V directly to the output of the first stage, the effects of (RHP)
M7 -M10 250.05/1.2 Vbias3 1.293 V zero are cancelled . Furthermore, the first pole’s frequency
- - Vctrl1 2.028 V - 2.035 V ω−3dB is moving at a higher frequency, improving opamp’s
bandwidth.

M2 have to be sized in such way that ensures that M0 TABLE III

is not driven into triode mode. The rest of the transistors T RANSISTOR /C OMPONENT S IZING & B IAS VOLTAGES
are operating at a higher Vef f , although close in value Transistor W/L (µm) Bias Voltages Obtained Value
between them, allowing maximum swings at the output. M11 − M12 49.95/1.2 Vctrl2 2.004 V− 2.009 V
M13 − M14 150/1.2 - -
Component Value - -
C1 − C2 3.1pF - -
B. Common−Source Output Stage
The need for acquiring additional gain and large swings
This results in much less layout area, since no nulling
imposes the existance of a common−source stage at
resistors are used and compensation capacitors are sig-
the output . For the present design a simple N-channel
nificantly smaller. Also opamp’s speed and slew rate are
topology (Fig. 2) is selected. The transistors M11 -M12 form
improved.
the gain stage while M13 -M14 act as their current sources.
All transistors (both N-channel and P-channel) are sized
properly to operate in tightly close Vef f values. The output C. Common−Mode Feedback Networks
voltage level is set at half of the supply voltage by driving Determining the output common mode voltage of a fully
the output nodes through a continuous common mode differential operational amplifier is proven to be a very
feedback network. In this way, maximum and symmetrical tough task, since any matching error between transistors
swings at the output are achieved. results in the fluctuation of the voltage level. To resolve
The gain of this stage, since we are dealing with the this, we implement the control of the output common mode
basic amplifing cell, can be computed as: voltage of each stage with a CMFB network.
A = −gmN (rdsN ||rdsP ) (3) The feedback networks are two continuous-time differ-
ential difference amplifiers. Since the bias voltages of both
whereas the total output resistance also determines the stages are P-channel current sources, we end up using
driving capability of the opamp. two N-channel CMFB (Fig. 3) networks.

Fig. 3. The Common−Mode Feedback Networks

Fig. 2. The Output Common-Source Stage
Designing a two stage operational amplifier implies that
frequency compensation is realized. In this work, the in-
direct feedack compensation technique is approached.
Every network consists of two differential pairs, which
are formed by M15 , M17 − M18 , M16 and M23 , M25 −
M26 , M24 . These two pairs of each network receive the
output voltage and compare it each time with a reference
voltage, producing a voltage across the diode-conneted
ANALOG VLSI NTUA COURSE 3

transistors M21 , M29 . This applied voltage is the result of TABLE V

negative feedback configuration, striving to prevent volt- T RANSISTOR /C OMPONENT S IZING
age fluctuation at each stage’s output. Transistor W/L (µm) Transistor W/L (µm)
M31 19.8/1.2 M41 24.45/1.2
TABLE IV M32 ,M47 -M48 16.5/1.2 M42 ,M49 25.65/1.2
T RANSISTOR S IZING & B IAS VOLTAGES M46 ,M33 -M34 6.15/1.2 M43 36.15/1.2
M35 -M36 25.05/1.2 M55 ,M44 -M45 4.95/1.2
Transistor W/L (µm) Bias Voltages Obtained Value
M37 6.6/1.2 M50 6.3/1.2
M15 − M20 19.995/1.2 Vbias4 0.850 V
M38 10.05/1.2 M51 -M52 24.45/1.2
M21 − M22 10.05/1.2 Vref 1 1.093 V
M39 40.05/1.2 M53 27.45/1.2
M23 − M28 19.95/1.2 Vref 2 1.646 V
M40 9.75/1.2 M54 49.95/1.2
M29 − M30 10.05/1.2 - -
Resistor Value (kΩ) - -
R0 1.02 - -
The transistors M19 − M20 and M27 − M28 serve as tail
current sources while the diode-connected transistors M22
and M30 facilitate voltage level drops. The common mode
voltage level of the first stage is selected so the common- III. S IMULATION , P ERFOMANCE & R ESULTS
source stage can be properly biased. Then, the output
voltage is fixed at half of the supply rail. This operational amplifier was designed and tested in
NCSU ami06 CMOS technology. The complete schematic
is depicted in Fig. 5. The opamp has been tested in two
scenarios concerning the input common mode voltage.
D. Biasing Circuit In Table VI (Scenario I), the worst results across the
achieved input common mode voltage range are listed.In
Establishing a constant voltage or current, which is Scenario II, an 1.65 V input common mode voltage was
insensitive to Process-Voltage-Temperatures variations, is applied to test opamp’s perfomance, leading to the results
the main goal behind the design of a bias circuit. This is ac- mentioned in Table VII. At this point it should be noted
complished by using the basic constant-transconductance that a different design approach may be adopted. In order
cell. to achieve this wide Input Common Mode Range, we
had to make some compromises concering the unity gain
frequency, the gain margin and the settling time of the
opamp. Indicatively for C1 = C2 = 2.8pF and a shorter, yet
valid input common mode range (0.8 V- 2.22V), we have
the following results, which are illustrated in Table VIII.
Depending on the application and desired specifications,
either design option may be selected.
Finally, DC input-output transfer function, Open-Loop
Gain and Phase Bode plots are depicted in Fig. 6, Fig.7,
Fig. 4. The Biasing Circuit and Fig. 8 respectively.

It consists of the transistors M31 − M36 plus the resistor

R0 . Sizing M35 − M36 in a way to have equal currents in TABLE VI
both branches it can be shown that: P ERFOMANCE TABLE & C OMPARISON WITH P ROPOSED S PECIFICATIONS
(W ORST-C ASE S CENARIO ACROSS ACHIEVED I NPUT C OMMON R ANGE )

q Parameter Proposed value Achieved Value

(W/L)32 Power Supply Voltage +3.3 V (single) +3.3 V (single)
2[1 − (W/L)31 ]
gm32 = (4) Small-Signal DC Gain >70 dB > 85.1 dB
R0 Unity-Gain Frequency >20 MHz >34.78 MHz
Phase Margin > 60◦ > 75.37◦
Thus M32 ’s transconductance is insensitive to Process- Gain Margin > 8 dB > 7.99 dB
Voltages-Temperatures variations and is depended only ICMR Swing 0.8 V - 2.2 V 0 V- 2.22 V
(to a first order effect) on resistor R0 and the geometry of Swing Per Output 0.5 V - 2.5 V 0.3 V- 3 V
M31 − M32 . Since gm32 is stabilized, every needed voltage DC Input−Output Function monotonic monotonic
can be acquired. This is achieved by building addiotional Settling Time to (0.1% Error) < 40ns 39.53 ns
current mirror blocks followed by diode-connected tran- Current Consumption Minimum possible <2.066 mA
sistors, properly sized. These blocks are formed by the CMRR (Single-Ended) > 50 dB >116.91 dB
transistors M37 −M55 , whose (W/L) ratios are listed below PSRR (Single-Ended) > 50 dB >81.52 dB
in Table V. Technology NCSU ami06 NCSU ami06
ANALOG VLSI NTUA COURSE 4

Fig. 5. Complete Schematic of Operational Amplifier

TABLE VII
P ERFOMANCE TABLE & C OMPARISON WITH P ROPOSED S PECIFICATIONS
(1.65 V I NPUT C OMMON -M ODE VOLTAGE )

Parameter Proposed value Achieved Value

Power Supply Voltage +3.3 V (single) +3.3 V (single)
Small-Signal DC Gain >70 dB 86.28 dB
Unity-Gain Frequency >20 MHz 39.79 MHz
Phase Margin > 60◦ 77.07◦
Gain Margin > 8 dB 9.19 dB
Swing Per Output 0.5 V - 2.5 V 0.3 V- 3 V
DC Input-Output Function monotonic monotonic
Fig. 6. DC Input-Output Function
Settling Time to (0.1% Error) < 40ns 39.53 ns
Current Consumption Minimum possible 2.054 mA
CMRR (Single-Ended) > 50 dB 137.62 dB
PSRR (Single-Ended) > 50 dB 84.08 dB
Technology NCSU ami06 NCSU ami06

TABLE VIII
S HORT P ERFOMANCE TABLE FOR A LTERNATIVE D ESIGN A PPROACH
(F OR VARIOUS I CMR A PPLIANCES )
Fig. 7. Open Loop Gain
Parameter ICMR=1.65 V ICMR (0.8 V-2.22 V)
Small-Signal DC Gain 86.28 dB > 85.1 dB
Unity-Gain Frequency 44.18 MHz >38.58 MHz
Phase Margin 75.48◦ > 72.91◦
Gain Margin 8.78 dB >8.09 dB
DC Input−Output Function monotonic monotonic
Settling Time to (0.1% Error) 33.77ns 33.77 ns
CMRR (Single-Ended) 137.6 dB > 116.89 dB
PSRR (Single-Ended) 84.07 dB > 81.52 dB

Fig. 8. Open Loop Phase

The settling time measurement was obtained by

applying an 1 V amplitude step signal split between the
inputs in unity feedback configuration with 1.65 V input
common mode voltage and a 1pFk20kΩ load. We have
imposed a delay of 10ns to the input step signal. The
large step response is illustrated in Fig. 9.

Fig. 9. Opamp’s Step Response

ANALOG VLSI NTUA COURSE
IV. C ONCLUSION
With this design we managed to achieve all technical
specifications that have been proposed. The overall perfo-
mance of the operational amplifier demonstrated notable
robustness and flexibility for various demands. Although
future redesigns of specific parts may improve its perfo-
mance for more specialized applications.
5
R EFERENCES
[1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill
International Edition
[2] P. R. Grey, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and
Design of Analog Integrated Circuits, 5th Edition, John Wiley & Sons,
Inc., 2009.
[3] T. Chan Carusone, D. A. Johns, K. W. Martin, Analog Integrated
Circuit Design, 2nd Edition, John Wiley & Sons, Inc., 2012.
[4] Adel S. Sedra, Kenneth C. Smith, Microelectronic Circuits, 7th
Edition, Oxford University Press, Inc.,2015
[5] P. R. Grey and R. G. Meyer, ”MOS Operational Amplifier Design - A
Tutorial Overview”, IEEE Journal Of Solid-State Circuits., vol. sc-17,
no. 6, December 1982.
[6] Vishal Saxena and R. Jacob Baker, Indirect Feedback Compensa-
tion of CMOS Op-Amps.
Konstantinos Kailas was born in Athens, Greece, in 1993 and is
currently an undergraduate student in School of Electrical and Computer
Engineering, National Technical University of Athens.