University of Pune

S.E. I.T.
Subject code: 214447

Processor Architecture and

Interfacing
Part 02: Assembly Language Programming
With 8086
Tushar B Kute,
Sandip Institute of Technology
and Research Centre, Nashik
tbkute@gmail.com
 Program Development
• Assembly Language Program Development
DATA SEGMENT ;Data segment declaration
MULTIPLICAND DW 341AH
MULTIPLIER DW 20F4H
PRODUCT DW 2 DUP(0)
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS:DATA
START: MOV AX, DATA
MOV DS, AX
Example Code
MOV AX, MULTIPLICAND
MUL MULTIPLIER
MOV PRODUCT, AX
MOV PRODUCT+2, DX
INT 3
CODE ENDS
END START
 8086 Instructions
• Data transfer
• Arithmetic
• Bit manipulation
• String
• Program execution transfer
• Processor control
 Data Transfer Instructions
General
• MOV
• PUSH
• POP
• PUSHA
• POPA
• XCHG
• XLAT
 MOV Destination, Source
• MOV CX, 045FH
• MOV BL, [43E4H]
• MOV AX, DX
• MOV DH, [BX]
• MOV DS, BX
• MOV RESULTS[BP], AX
PUSH Source
• PUSH BX
• PUSH DS
• PUSH TABLE[BX]

POP Destination
• POP BX
• POP DS
• POP TABLE[BX]
• PUSHA
• POPA
• XLAT / XLATB

XCHG Destination, Source

• XCHG AX, BX
• XCHG AL, CH
• XCHG AL, PRICES[BX]
 Data Transfer Instructions
• IN
Simple IO port transfer
• OUT

• LEA
Special address transfer
• LDS
• LES

• LAHF
• SAHF Flag transfer
• PUSHF
• POPF
IN Accumulator, Port
• IN AL, 0C4H
• IN AX, 34H

OUT Port, Accumulator

• OUT 3BH, AL
• OUT 2CH, AX
LES Register, Memory addr of first word
• LES BX, [789AH]
• LES DI, [BX]

LEA Register, Source

• LEA BX, PRICES
• LEA BP, SS:STACK_TOP
• LEA CX, [BX][DI]
LDS Register, Memory addr of first word
• LDS BX, [789AH]
• LDS DI, [BX]
 Flag Transfer Instructions
• LAHF [Load AH With Flags]
• SAHF [Store AH in Flags]
• PUSHF [Push flags on stack]
• POPF [Pop stack top to flags]
 Arithmetic Instructions
• ADD • AAS
• ADC • DAS
• INC • MUL
• AAA • IMUL
• DAA • AAM
• SBB • DIV
• SUB • IDIV
• DEC • AAD
• NEG
• CBW
• CMP
• CDW
 ADD Destination, Source
• ADD AL, 74H
• ADD CL, BL
• ADD DX, BX
• ADD DX, [SI]
ADC Destination, Source
• ADC AL, 74H
• ADC CL, BL
• ADC DX, BX
• ADC DX, [SI]
 INC Destination
• INC BL
• INC CX
• INC VARIABLE

AAA [ASCII Adjust Accumulator After Addition]

DAA [Decimal Adjust Accumulator After Addition]

 SUB Destination, Source
• SUB CX, BX
• SUB CH, AL
• SUB AX, 4563H
• SUB PRICES[BX], 04H

SBB Destination, Source

• SBB CX, BX
• SBB CH, AL
• SBB AX, 4563H
 DEC Destination
• DEC AL
• DEC BP
• DEC VARIABLE
NEG Destination
• NEG AL
• NEG BX
• NEG BYTE PTR[BX]
 CMP Destination, Source
• CMP AL, 01H
• CMP BH, CL
• CMP CX, TEMP_MIN
• CMP TEMP_MIN, CX

AAS [ASCII Adjust Accumulator For Subtraction]

DAS [Decimal Adjust Accumulator For Subtraction]
MUL Source
• MUL BH
• MUL CX
• MUL BYTE PTR[BX]

AAM
[BCD Adjust Accumulator After Multiply]
DIV Source
• DIV BH
• DIV CX
• DIV BYTE PTR[BX]

AAD
[Binary Adjust Accumulator Before Division]
CBW
Convert Signed Byte to Signed Word

CWD
Convert Signed Word to Signed Double Word
Bit Manipulation Instructions

Logical Shift Rotate

• NOT • SAL • ROL

• AND • SHL • RCL
• OR • SAR • ROR
• XOR • SHR • RCR
• TEST
NOT Destination
• NOT BX
• NOT BYTE PTR[BX]

AND Destination, Source

• AND BH, CL
• AND CX, [SI]
• AND BX, 00FFH
• AND DX, BX
OR Destination, Source
• OR BH, CL
• OR CX, [SI]
• OR BX, 00FFH
• OR DX, BX
XOR Destination, Source
• XOR BH, CL
• XOR BP, DI
• XOR DX, BX
TEST Destination, Source
• TEST BH, CL
• TEST CX, [SI]
• TEST BX, 00FFH
• TEST DX, BX
SAL / SHL Destination, Count
• SAL BX, 01
• SAL BP, CL
• MOV CL, 04H
• SAL AL, CL
C B7 B6 B5 B4 B3 B2 B1 B0

0 1 0 1 1 0 1 1 1

1 0 1 1 0 1 1 1 0
SHR Destination, Count
• SHR BP, 01
• SHR AL, CL

B7 B6 B5 B4 B3 B2 B1 B0 C

0 1 0 1 1 0 1 1 1 0

0 1 0 1 1 0 1 1 1
SAR Destination, Count
• SAR DI, 1
• SAR AL, 01

B7 B6 B5 B4 B3 B2 B1 B0 C

1 0 1 1 0 1 1 1 0

1 1 0 1 1 0 1 1 1
ROL Destination, Count
• ROL AX, 1
• ROL BL, CL

C B7 B6 B5 B4 B3 B2 B1 B0

0 1 0 1 1 0 1 1 1

1 0 1 1 0 1 1 1 1
RCL Destination, Count
• RCL AX, 1
• RCL BL, CL

C B7 B6 B5 B4 B3 B2 B1 B0

0 1 0 1 1 0 1 1 1

1 0 1 1 0 1 1 1 0
ROR Destination, Count
• ROR BL, 01
• ROR AL, CL

B7 B6 B5 B4 B3 B2 B1 B0 C

1 0 1 1 0 1 1 1 0

1 1 0 1 1 0 1 1 1
RCR Destination, Count
• RCR BL, 01
• RCR AL, CL

B7 B6 B5 B4 B3 B2 B1 B0 C

1 0 1 1 0 1 1 1 0

1 1 0 1 1 0 1 1 1
 Program Execution Transfer

CALL name of procedure

• CALL SQRT
• CALL BX
• CALL WORD PTR(BX)

RET
 Jump Instructions
• JMP label

Instruction Description (Jump if) Conditions

JA/JNBE Above/Below Not Equal C=0, Z=0
JAE/JNB Above or Equal/ Not Below C=0, Z=1

JB/JNAE Below/Not Above nor Equal C=1, Z=0

JBE/JNA Below or Equal/Not Above C=1, Z=1

JC Carry flag=1 C=1
JE/JZ Equal / Zero Z=1
 Jump Instructions
Instruction Description (Jump if) Conditions
JG/JNLE Greater/Not Less Than or C=O, Z=0
Equal
JGE/JNL Greater Than or Equal/Not S=O
Less Than
JL/JNGE Less Than/Not Greater S≠O
Than or Equal
JLE/JNG Less Than or Equal/Not S=O, Z=1
Greater Than
JNC No Carry C=0
JNE/JNZ Not Equal / Not Zero Z=0
 Jump Instructions
Instruction Description (Jump if) Conditions
JNO Not Overflow O=0
JNP/JPO Not Parity/Parity Odd P=0
JNS Not Sign S=0
JO Overflow O=1
JP/JPE Parity/Parity Even P=1
JS Sign Flag S=1
JCXZ CX is Zero CX=0
 Iteration Control Instructions

Instruction Description Conditions

for Exit
LOOP Loop through sequence of CX=0
instructions
LOOPE/ Loop through sequence of CX=0 or
instructions ZF=0
LOOPZ
LOOPNE/ Loop through sequence of CX=0 or
instructions ZF=1
LOOPNZ
Processor Control Instructions
• STC
• CLC
• CMC
• STD
• CLD
• STI
• CLI
External Hardware Synchronization
• HLT
• WAIT
• ESC
• LOCK
• NOP
 Interrupt Instructions
• INT
• INTO
• IRET
 References
• “Microprocessors and Interfacing” by Douglas
Hall, Tata McGraw Hill Publishing.