DIGITAL SYSTEM DESIGN

Building Block Circuits

¨  Rather than building systems at the gate level, often digital
systems are constructed from higher level, but still basic,
building block circuits.
¨  Multiplexers, decoders, flip-flops, registers, and counters are
examples of building blocks, which are subcircuits from
which complex circuits can be constructed.
¨  For many larger systems, the circuitry required can often be
divided into two Sub-systems: the datapath circuit; and the
control circuit.
¨  The datapath circuit is used to store and manipulate data
and to transfer data from one part of the system to another.
¨  Datapath circuits can comprise of building blocks such as
registers, shift registers, counters, multiplexers, decoders, etc.
Building Block Circuits
¨  The control circuit, usually an FSM, controls the operation of
the datapath circuit.
¨  In many applications, it is useful to be able to prevent the
data stored in a flip-flop from changing when an active
clock edge occurs.
¨  A simple example of the division of the data path and the
control path can be illustrated using a flip-flop with an
enable input.
¨  The data path consists of the flip-flop and its input, and the
control path consists of the enable input.
¨  The two paths exist independently of each other with the
enable (control path) controlling the flow of the data into the
flip-flop.
¨  It is also useful to be able to inhibit the shifting operation in
a shift register by using an enable input.
Algorithmic State Machine (ASM) charts
¨  State diagrams are not convenient to describe the
behavior of large state machines
¨  ASM charts are used to describe large machines

¤  Itis a type of flow chart

¤  Represents state transitions
¤  Represent generated outputs for an ASM

¨  ASM charts have three types of elements

¤  State box
¤  Decision box
¤  Conditional output box
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Elements used in ASM charts
State name

Output signals
0 (False) Condition 1 (True)
or actions
expression
(Moore type)

( ) State
(a) S bbox (b) Decision box

Conditional outputs
or actions
i (Mealy
( l type))

(c) Conditional output box

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ASM Šˆ™›
chart for a–™ ˆ š”—“Œ
simple FSM mzt
Reset

0
w
1
B

0
w
1

C
z

0 1
w
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State Diagram and its corresponding ASM chart
hztGŠˆ™›
Reset

Reset
A
w=1ez=0

w=0ez=0 A B w=1ez=1

w=0ez=0 0
!"
1

#"

0 1
!
!"
 Design Example: A Bit-Counting Circuit
¨  Using the concepts of the ASM and the separate data and control
circuits we can implement fairly complex systems.
¨  Suppose we wish to count the number of bits in a register that have
the value 1.
¨  Assume that the value A is stored in a register that can shift its
contents in the left to-right direction.
¨  Pseudo-code for the bit counter.

B=0;
while A ≠ 0 do
if a0 = 1 then
B=B+1;
End if;
Right-shift A ;
End while;
 ASM chart for the pseudo-code.
¨  s: input signal that indicates if A has Reset

been loaded
S1
¨  We can assume that the same clock Load A B m0 s: in
signal controls the changes in the state been
of the machine and changes in A and B. 0 We c
Therefore in state S2, the decision box 0 1 signa
s s of th
which tests whether A=0, occurs 1 Ther
simultaneously with the box that checks whic
the value of a0. S2 S3 simu
check
¨  If A=0, then the FSM will change to Shift right A Done
If A=
state S3 on the next clock edge (this state
also shifts A, which has no effect also
because A is already 0). 1 becau
B mB + 1 A = 0?
On th
¨  On the other hand, if A=0, then the 0
FSM
FSM does not change to S3 but remains rema
At th
in S2. At the same time A is shifted, and 0
a0 incre
B is incremented if a0 has the value 1.
1

ASM chart for the pseudo-co

 Digital System Design

AA Bit-Counting
Bit-Counting Circuit (data-path)
Circuit (data-path)
¨  •ForFor
thethe data-pathcircuit
data-path circuit a shift
a shift register
register which
which shifts
shifts leftleft
to- to-
right is required to implement A.
¨  right is required to implement A.
• It must have the parallel load capability and an enable
¨  It must have the parallel load capability and an enable input since
input since shifting should occur only in state S2.
shifting should occur only in state S2.
• In addition, a counter is needed for B, and it needs a
¨  In addition, a counter is needed for B, and it needs a parallel-load
parallel load capability to initialize the count to 0 in state
parallel-load
capability to initialize the count to 0 in state S1.
S1. Data 0
n log n
2
0 w LB L
LA L Shift EB E Counter
EA E
Clock
A log n
2
n

z a B
0
 ASM chart for the bit counter control circuit
Data 0 Reset
n log n
2
0 w LB L S1
LA L Shift EB E Counter
EA E LB
Clock
A log n
2
n 0
0 1
s s

1
S2 S3
z a B
0
EA Done

1
EB z

s: A is ready 0
a0
z: =1 when A = 0 (filled it)
1
 ASM chart for the bit counter control circuit
Data 0 Reset
n log n
2
0 w LB L S1
LA L Shift EB E Counter
EA E EA,LA EB,LB
Clock
A log n
2
n 0
0 1
s s
1

z a B S2 S3
0
EA Done

1
EB z

0
a0

1
 Shift-And-Add Multiplier
Shift-And-AddMultiplier.
Shift-And-Add Multiplier.
Decimal
Decimal Binary
Binary
13
13 11110011 A:A:Multiplicand
Multiplicand
uu11
11 uu11001111 B:B:Multiplier
Multiplier
13
13 11 110011
13
13 11110011
143
143 00000000
11110011
11000000 11111111 PP==Product
Product

Manualmethod
Manual method

Analgorithm
An algorithm
An formultiplication.
algorithm for
for multiplication.
multiplication.
PP == 00; ;
fori i== 00totonn––11do
for do
ififbbi i== 11then
then
PP == PP++AA; ;
endif;if;
end
Left-shift A; ;
Left-shift A
end for;
end for;
ASM chart for the multiplier Reset

S1 Reset

Load A P m0
Load B S1

Load A P m0
0
Load B
0 1
s 0 s
P = 0;
0 1
for i = 0 to n – 1 do 1s s
if bPi == 01 then
;
for i = 0 to n – 1 do 1
Pif=b P= +1 then
A; S2 S3
i
end if; P = P+ A; S2 left A , Shift right B
Shift S3 Done
endAif;;
Left-shift
Shift left A , Shift right B Done
end for; Left-shift A ;
end for;
1
P mP + A B = 0? 1
P mP + A B = 0?
0
0

0
0 b0b
0

11

ASM chart
ASM forforthe
chart themultiplier.
multiplier.
Datapath circuit for the multiplier.
LA 0 DataA LB DataB
n n n

L L
EA E Shift-left EB E Shift-right
register register

A B
Clock
2n n

Sum z b0
0
2n 2n
Psel 1 0
2n
DataP
EP E
Register
eg ste

2n

P
 ASM chart for the multiplier control circuit.
Reset

S1

Psel = 0 EP

ASM chart for the 0

s
multiplier control
1
circuit. 0
1
s

S2 S3

P l = 1 EA  EB
Psel D
Done

1
EP z

0
b0