Tutorial: Introduction to DSP using SysGen

and introductory assignment

Introduction
This tutorial will introduce the basic features of the Xilinx blockset for DSP design using
Simulink/Matlab. The Xilinx blockset is a library of arithmetic, logic and DSP functions
under Simulink, useful for design simulation and verification. In this library, the System
Generator token translates the designs to the FPGAs creating project files (HDL) that can
be later synthesized, simulated, implemented and downloaded to the FPGA using the
Xilinx ISE Project Navigator.

Tutorial Overview

We will explore the effects of different quantization and overflow schemes when dealing
with digital signals and FPGAs. Simulink uses a “double” format to represent numbers in
a simulation. A double is a “64-bit two’s complement floating point number”. The Xilinx
blockset uses an “n-bit fix point number” format, requiring a conversion between the
Xilinx blocks and the Simulink blocks.

-22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13
Value = -3.261108...
1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1
Format = Fix_16_13

Integer Fraction
(Sign: Fix = Signed Value
Format = Sign_Width_Decimal point from LSB Ufix = Unsigned Value)
Fig. 1. N-bit fix point point number example.

Xilinx Blockset  Matlab/Simulink I/0  Gateway In/Out

The Gateway In and Out blocks support parameters to control the conversion from
double precision to N-bit fixed point precision numbers. This parameters can be edited by
double clicking on the Gateway In block.

a) Output types:
 Boolean: Used to control ports like “CE” and “Enable”. It is a 1-bit unsigned
number that will always be set as High or Low.
 Signed (two’s complement)
 Unsgined

b) Quantization types:
 Truncate
  Round

c) Overflow
 Wrap
 Saturate
 Flag as error

Fig. 2. Xilinx Gateway In block parameters.

For the sampling rate, we must keep in mind that each signal must be sampled and each
block in a Simulink design has a “Sample Period” which corresponds to how often the
block’s function is calculated and the result outputted. Thus, the sample period must be
set explicitly for each block in the design. The System Generator token controls the
system sample period which can be set by double clicking on the System Generator
block.
When dealing with simple rate systems, the sample period will be the same as the sample
period set in the design. For multirate systems, the “Simulink System Period” in the
System Generator token is the global sample period and it must be set correctly for the
simulation to work. Therefore, for multirate systems every sample period in the design
must be a multiple of the system period.
 Fig. 3. The Xilinx System Generator token.

The Xilinx Blockset, Gateways

We will use the design in Fig. 5 to explain the different options for quantization and
overflow. We list the steps for setting up the simulation:

1. Open Matlab and launch Simulink by typing simulink at the Matlab command
prompt.
2. Look at the blocks available in the Simulink Library Browser. The following
elements (among others) should appear:
 Simulink (sources and sinks)
 Signal Processing Blockset
 Xilinx Blockset
  Xilinx Reference Blockset
3. Create a “new model” blank sheet, add the Sine Wave source and the Scope
sink element.
4. Add the Gateway In and Gateway Out from the Basic Elements on the
Xilinx Blockset. Connect the blocks as in figure 5.
5. Add the System Generator token from basic elements on the Xilinx Blockset
6. Change the working directory to C:\DSP_Spring07\Lab1\ and save the design
as quant_overf.mdl
7. Set the amplitude and frequency of the Sine Wave to 2 and 2*3 rad/sec
8. By double clicking on the Gateway In block, set the following parameters
 Output type: Signed
 Number of bits: 10
 Binary point: 6
 Quantization: Round
 Overflow: Wrap
 Sample period: 0.005 sec.
9. Double click on the System Generator token and set the Simulink Sample
Period to 0.005 sec.
10. Set the Simulation Stop time to 1 second, save and run the simulation.
11. Open the Scope, click on Autoscale and you should see two sine waves.
Figure 6.
Fig. 4. Simulink Library Browser with the Xilinx Blockset.
Fig. 5. Quantization and Overflow design example.
Fig. 6. Analog and Digital Sine Waves
1. Sampling rate, Quantization and Overflow
The Xilnx Gateway In acts as an A/D converter. Here, assume that a continuous, real-
valued function xa(t) acts as the input of the system. The output is a discrete-time
sequence, x(n), with values at integer multiples of the sample frequency, Ts, and
amplitude quantized to a finite set of possible values.
Perform the following changes on the previous example, comment on your results and
present plots for each one of these changes
a) Change the amplitude of the sine wave to nine and choose saturation as the
overflow option.
Note: You can change the range of the Y axis on the scope plot, by right
clicking on it, then clicking on “Axis Properties” and setting it to an
appropriate value.
b) Use Wrap as the overflow option.
c) Set the number of bits to eleven, and use Saturate as the overflow option.
What would you do to avoid the jagged pattern on the discrete-time sequence?
d) Using your previous parameters set the binary point to one and choose
“truncate” as the quantization option.

2. Implement a Type-I FIR Filter

With the help of the Xilinx FDA (Filter Design Analysis) tool, we will implement and
simulate a sixth order low pass filter with the following characteristics:
a) Separate multiplier and accumulator per filter coefficient
b) Low pass filter of order 6
c) Sampling frequency of 1kHz

Here are the steps:

1. On your home directory create …\DSP_Spring07\Library and save the files
dsp_fir.mdl and slblocks.m in this directory. Change the work directory to
…\DSP_Spring07\Lab1\ and launch Simulink.

2. In the MATLAB window, set the path by selecting File→Set Path→Add Folder and
navigate to the C:\DSP_Spring07\Library, click on OK, click on Save and then Close.

3. Open a new model file; add the Sixth Order FIR Filter block from the DSP Spring
07 Library located at the Simulink Library Browser window.

4. Add and connect two Sine Wave inputs, a Sum Block and the Xilinx Gateway In
block to a Sixth Order FIR Filter block. The input to the filter is the addition of the
two waves.

5. Add the Xilinx Gateway Out block to the design, and a Scope block. Double click
on the scope block, click on the Scope Parameters button and change the Number of
Axes option to two.
6. Add the System Generator block and the FDA tool block from the Xilinx Blockset
libraray, which are located under Basic Elements and DSP respectively.

7. Save the design as lab1_filter.mdl. Your screen should look as shown in Fig. 7.

8. Double click on the FDA tool and set the following parameters:

 Response type: Lowpass

 Design Method: FIR, Least-Squares.
 Filter Order: 6
 Frequency Specifications: Units normalized, wpass: 01 and wstop: 0.25

Fig. 7. Sixth Order FIR Filter.

9. Click on Design Filter and export the coefficients to the workspace. Use the menu
FileExport. A new window appears, on the Numerator field type filter_coeff

10. Change the simulation stop time to 0.7 sec, and set the sine’s frequencies to 2**5
rad/sec and 2**300 rad/sec.
11. Double click on the Xilinx Gateway In block and verify:
 Number of bits: 16
 Binary point: 14
 Quantization: Round
 Overflow: Saturate
 Sampling Frequency: 0.001 sec.

12. Double click on the System Generator token, and set the Sampling Frequency to
0.001 sec.

13. Run the simulation and open the Scope.

The Sixth Order Filter block was designed specially for this tutorial, the filter coefficients
are taken automatically from the variable filter_coeff when exported from the FDA tool
to the workspace.

Right click on the filter block and select Look under mask, so that a new window will
open.

a) From the filter model write down the difference equation.

b) Present the graph of the filter’s output.
c) This is a Type I FIR filter, look at the coefficients and think about the filter’s impulse
response. Is there a more efficient way of implementing the filter on an FPGA?
Present a schematic of your new design, describe its benefits, and simulate it on
Simulink. For block implementation, use the Xilinx blocks i.e Xilinx Delay, Mult,
AddSub, and Constant. Which can be found in the Xilinx Blockset under Simulink.

Note:
Present a report with answers, comments and graphs when necessary.